JP3258312B2 - Manufacturing system of thick film/thin film hybrid multilayer wiring board and electron beam lithography system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent connection failure, and at the same time to achieve the high density of not only an upper thin-film circuit but also thick-film one by providing a matching layer that absorbs the misalignment between circuits at the interface between a thick-film wiring board and a thin-film wiring circuit formed at the upper portion and electrically connects terminals. SOLUTION: A ceramic thick-film wiring board 10 is equipped with five aluminum substrates 11, an inner-layer conductor 12 and an alignment mark 15 of a surface are printed by paste such as tungsten and molybdenum on such aluminum substrate 11, and a via part 13 is formed in the thick-film wiring board 10. On the backside of the thick-film wiring board 10, a land 14 is formed while the via part 13 being exposed from the backside is covered. Also, on the surface of the thick-film wiring board 10, a connection conductor pad 16 is formed while electric connection is made to the via part 13 being exposed from the surface. The connection conductor pad 16 can be used as a matching layer 62 for carrying out the matching connection between a conductor 22 for wiring in a thin-film wiring board 20 being formed on the pad and the via part 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for multi-layer wiring and a module on which an LSI is mounted, and more particularly to a multi-layer thin film hybrid system suitable for high density, high reliability and high yield in manufacturing. The present invention relates to a wiring board manufacturing system and an electron beam drawing apparatus.

[0002]

2. Description of the Related Art The technology of mounting an LSI chip on one ceramic wiring board is becoming a mainstream mounting technology of a large-scale, high-speed digital system such as a large-sized computer. In addition, there have been remarkable technological advances in multilayer wiring boards used in this technology. For example, at present, a thick-film hybrid substrate is formed by forming a thick-film wiring board made of ceramics or glass ceramics as an insulating layer and tungsten or molybdenum as a wiring conductor by a green sheet method, and then forming a wiring portion on the upper surface by a thin-film method. The study of multilayer substrates has been actively pursued. One of the problems with this thick-film / thin-film hybrid multilayer substrate is that the sintering shrinkage variation in the process of forming the thick-film wiring board is large. As a result, a positional shift occurs between the patterns at the joint portion between the thick film wiring substrate and the thin film wiring portion, which causes a connection failure. Incidentally, at present, the limit of the dimensional tolerance from the central portion of the thick film wiring board to the peripheral portion thereof is limited to about ± 0.5%. Therefore, if the distance from the center to the periphery is 50 mm, a maximum displacement of ± 250 μm occurs.

FIG. 2 shows one prior art for solving the problem of poor connection caused by such a variation in the shrinkage ratio of a thick film wiring board (see Japanese Patent Application Laid-Open No. 58-73193). In FIG. 2, an alumina multilayer substrate (thick film wiring substrate) 1 has a ground made of a sintered body of tungsten, a power supply layer 2, and a via portion (thick film wiring terminal) 3 in its inner layer. The via portion 3 is formed by embedding a tungsten paste in a via hole of the alumina insulating layer 4, and its diameter is set to be large in consideration of variation in the shrinkage ratio of the thick film wiring board 1 in advance. For example, when the substrate size is 50 mm, it is 250 μm or more. Reference numeral 5 denotes an insulating layer made of polyimide, in which a coated prepolymer solution is thermally cured to completely polyimide, and then a via hole is formed by photolithography using a resist. Further, a wiring 6 is formed on the via hole and the insulating layer 5. These insulating layers 5 and wirings 6 are alternately formed to form a thin film wiring portion 7.
Are formed. In this thick-film wiring board, by setting the diameter of the via portion 3 to a large diameter (about 500 μm), it is possible to absorb a positional shift due to a variation in the shrinkage of the thick-film wiring board 1 and prevent poor connection. can do.

[0004] FIG. 3 shows that the via system has a thickness of 150 μm or less.
An example in which a circular metal pad 8 such as palladium having a diameter of about 1 mm and a film thickness of about 3 μm is formed on the upper end surface of the via portion 3 while maintaining the thickness at 200 μm. In this case, the thick metal wiring board 1 is formed by forming the circular metal pads 8.
Misalignment due to the variation in the shrinkage of the wire can be prevented, and a connection failure can be prevented (Japanese Unexamined Patent Publication No. 61-2)
No. 2691).

[0005]

Recent advances in high performance and high density of LSIs have been rapid. Even at present, LSI terminal pitch is about 450 μm and terminal diameter is about 200 μm. In order to achieve such high density, it is essential to increase the density not only in the upper thin film circuit but also in the thick film circuit. However, the above-described conventional substrate has the following disadvantages. That is, in the example of FIG.
In the example shown in FIG. 3, the diameter of the circular metal pad on the thick-film substrate is 1 mm, which is larger than the diameter of the via, which hinders the high density and high yield of the multilayer substrate. become. In order to further increase the density of the thick film circuit, the via diameter may be increased to about 0.5 mm as in the conventional example described above, or the circular conductor diameter on the thick film substrate may be increased to 1 mm and more than the via diameter. It is not allowed to expand. Unless these dimensions are maintained as they are or not reduced, it is impossible to increase the density of the substrate. However, it is obvious from the above description that when the diameter of the via or the diameter of the circular metal pad is reduced, the connection failure increases.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a connection failure due to a variation in shrinkage of a ceramic or glass-ceramic wiring board, that is, a thick-film wiring board, and to provide a high-density thick-film thin-film hybrid multilayer. An object of the present invention is to provide a substrate manufacturing system.

In order to achieve this object, in a thick-film thin-film hybrid multilayer wiring board in which a thin-film wiring circuit is formed on a thick-film wiring board, a displacement between the circuits is determined at an interface between the thick-film wiring circuit and the thin-film wiring circuit. A matching layer for absorbing and electrically connecting each terminal is provided, and a part of the conductor pad formed on the matching layer has an elliptical or band-like shape. Directly connected to at least two of the via holes on the surface of the thick film substrate, the via holes on the bottom surface of the thin film circuit, or the via holes formed in the matching layer, and the direct connection position with the via hole is the position of the conductive pad. It was not necessarily formed in the center but in the vicinity of the end.

The formation of the conductive pad connected to the via hole as described above can be achieved by the following method. That is, the position of the via hole on the surface of the thick film substrate is measured by selecting the via hole at the substrate end or the center of the substrate. The contracted state of each substrate is classified into several types of patterns. A connection conductor mask corresponding to each pattern is prepared, and this is used to form a connection conductor pad. In order to carry out this more efficiently, the following method was used.
(1) Based on the position of the thick film wiring terminal and the position of the thin film wiring,
A connection conductor pad corresponding to each substrate and each terminal is formed by an electron beam drawing method. (2) On the basis of the positions of the thick-film wiring terminals and the positions of the thin-film wiring, connection conductor pads corresponding to individual substrates and terminals are formed by a dot printer type printing machine.

Further, in order to increase the density and improve the substrate yield, the diameter of the via hole of the signal wiring in the thick film wiring board is set to 50 μm to 150 μm. Further, in order to easily detect the position of a via hole or the like from an optical or secondary electron image, five or more position detection marks are formed on the surface of the thick film wiring substrate on which the thin film circuit is formed before firing the substrate. It was to be. In some cases, the position detection mark can be replaced with a thick film wiring terminal exposed on the thin film side surface of the thick film wiring substrate.

In order to easily achieve high-density wiring, the shape of the connection conductor pads is made elliptical or band-like, and the width of the connection conductor pads is set to 50 μm to 500 μm. Also, the material of the connection conductor pad is silver / palladium,
It is made of at least one metal selected from platinum, copper, aluminum, gold, nickel, chromium, tungsten, and molybdenum.

[0011]

The position detection mark on the surface of the thick film wiring board is different from the alignment mark of a normal mask or screen, and has the following three points.
Has two roles. That is, an index of positioning of a thin film circuit pattern to be superimposed on a thick film wiring board, quantitative determination of a shrinkage distribution of the thick film substrate, and detection / estimation of a position of each thick film conductor terminal based on the above. In order to achieve these functions, at least one position detection mark at the center of the substrate is required. If the temperature distribution during firing is not uniform, the substrate shrinks in a complicated manner, so that more position detection marks are required. In some cases, the position of the thick film conductor terminal (via itself) is used as the position detection mark. Is also required. One end of the connection conductor pad needs to be connected to the thick film wiring terminal of the thick film substrate, and the other end needs to be connected to the thin film wiring terminal thereon. To realize this, the positional relationship of the thin film wiring terminals is known from the created thin film pattern, and the position of the thick film wiring terminal of the thick film substrate can be detected by a position detection method based on the position detection mark. . Based on this, a connection conductor pad is formed as described below.

The displacement of the thick film wiring terminals is classified into several types of patterns, and a mask corresponding to each pattern is prepared.
Using this, a connection conductor pad is formed. Based on the positions of the thick-film wiring terminals and the positions of the thin-film wiring, connection conductor pads corresponding to individual substrates and terminals are formed by an electron beam drawing method. Based on the positions of the thick-film wiring terminals and the positions of the thin-film wiring, connection conductor pads corresponding to individual substrates and terminals are formed by a dot printer type printing machine.

The material of the connection conductor pad is silver / palladium, platinum, copper, aluminum, gold, nickel,
Silver / palladium, platinum, copper, tungsten, molybdenum, gold, and thin film wiring used as a conductor material for a thick film substrate by being formed of at least one metal selected from chromium, tungsten, and molybdenum. Compatible with copper, gold, and aluminum used as circuit conductor materials, ensuring long-term life (thick film)
A hybrid multilayer wiring board can be realized. The above is also applicable to the electrical connection between layers in the thin film layer. In particular, when the fluctuation of the shrinkage rate of the thick film substrate is large and the fluctuation cannot be completely absorbed by only one layer, the fluctuation can be absorbed in several layers.

[0014]

[Embodiment 1] Hereinafter, the present invention will be specifically described with reference to the embodiment shown in FIG. FIG. 1 describes a method of manufacturing a thick-film thin-film multilayer wiring board. The ceramic thick film wiring board 10 includes five alumina substrates 11, and an inner layer conductor 12 and a positioning mark 1 on a surface of each alumina substrate 11 by a paste such as tungsten or molybdenum.
5 is printed, and the individual alumina substrates 11 are laminated and then sintered. In the ceramic thick film wiring board 10, via portions (ceramic wiring terminal portions) 13 are provided.
Are formed. The via portion 13 is formed by embedding a paste of tungsten or molybdenum in a via hole formed so as to penetrate each alumina substrate 11 and then sintering the paste. A land 14 is formed on the back surface (lower surface) of the substrate 10 so as to cover the via portion 13 exposed therefrom.

A connection conductor pad 16 is formed on the surface (upper surface) of the ceramic thick film wiring board 10 so as to be electrically connected to the via portion 13 exposed therefrom. The shape of the connection conductor pad 16 is an elliptical shape or a band shape having a semicircle at both ends, and the maximum value of the width is 50 μm to 500 μm. The connection conductor pad 16 serves as a matching layer 62 for performing a matching connection between the wiring conductor 22 in the thin film wiring board 20 formed thereon and the via portion 13. When the size of the substrate 10 is 100 mm square, the diameter of the via portion 13 is about 50 to 150 μm.

The method of forming the connection conductor pad 16 for matching is performed as follows. (1) Before the deposition of the connection conductor pad 16, the position of the alignment mark 15, and in some cases, the position of the main via portion are detected by using a pattern recognition technique of a secondary electron image of an electron beam or an optical image. (2) A metal film to be a connection conductor pad is formed on a substrate. In this case, the metal film is formed wider in consideration of the shrinkage ratio of the ceramic substrate. In some cases, a metal film is formed on the entire surface in the vicinity of the via portion. There are the following two types of film formation methods. That is, when the film is formed by printing: a film is formed by a printing method using at least one of gold, silver / palladium, platinum, and copper, and then fired. The film is formed by a thin film technique such as vapor deposition or sputtering. Case: Aluminum, gold, copper, nickel,
It is formed by vapor deposition and sputtering using at least one of chromium. At the time of film formation, the alignment mark must be in a state of appearing on the substrate surface or being covered with a transparent film. (3) A negative type resin is applied on the metal film to be the connection conductor pad 16, which has sensitivity to the electron beam, is cured by the irradiation of the electron beam, and is not dissolved by the subsequent developing operation. (4) The alignment mark obtained in (1), and in some cases, the deviation of the position of the main via portion from the specified position is obtained, and the connection enabling electrical connection with the thin film circuit formed thereon is obtained. In order to form a conductive pad, a negative type resin on the pattern of the connecting conductive pad is patterned and irradiated with an electron beam. (5) The negative type resin is developed using a developing solution, and the portion of the resin not irradiated with the electron beam is removed.
(6) Using an etchant suitable for etching a film-forming metal such as nitric acid, a portion of the metal film whose surface is not covered with the resin is removed. (7) Heat treatment of the remaining metal film to connect the connection conductor pads 16 densely and firmly to the ceramic substrate
To form The thin film circuit 20 formed thereon is formed by a normal thin film technique using a polyimide resin, silicon oxide, or the like as the insulating layer 21 and aluminum, gold, copper, or the like as the conductor 22. The connection terminals 31 of the LSI 30 are connected to the pads 32 formed on the uppermost part of the thin film circuit by soldering 32.
And so on to complete the module.

Here, it will be explained that the method of determining the position of the connection conductor pad pattern 16 according to the present invention is conceptually completely different from the method of determining the position in the conventional electron beam writing apparatus.

FIG. 1 also shows the structure of a thin film wiring portion on a ceramic wiring substrate when a pad pattern is formed by the pattern position determining method of the present invention, as described above. This shows a case where a pad pattern is formed. In the conventional electron beam writing method,
As described in Japanese Patent Application Laid-Open No. 190-190, the position of one or a plurality of alignment marks 15 is detected, and the position of a pad pattern to be drawn next is obtained by interpolation from the coordinates to perform drawing. That is, the pad pattern is drawn according to the existing pattern. According to this method, as shown in FIG. 4, the pad 16 ′ is positioned on the existing via portion 13 and is formed symmetrically (concentrically) with respect to the via portion 13. For this reason, a portion that is not connected to the standard position of the conductor 22 determined from the position of the connection pad 23 with the LSI 30, or that the connection is incomplete, the electrical conduction may be partially broken (the leftmost pad pattern is an example). there were.

On the other hand, according to the method of the present invention, the position of the via portion 13 is determined by detecting the standard mark, and the position of the conductor 22 determined from the terminal position of the upper LSI 30, which is the desired standard pattern, is finally connected. The pad pattern 16 is drawn as described above. Pad 1 in this way
By forming 6, a connection pattern free from connection failure can be formed as shown in FIG. FIG. 5 shows an example of an apparatus for drawing a connection conductor pad pattern using an electron beam. The mirror body 40 is evacuated to a vacuum enough for the electron beam to travel. The electron beam 43 emitted from the electron gun 41 is converted into an electron lens 42
The beam is irradiated onto a thick-film wiring board (sample) 47 mounted on a sample stage 46 via a beam blanker 44 and a deflector 45. Sample size is 100 × 100
mm ² . The electron beam can be deflected over a range of 100 × 100 mm 2 in accordance with an instruction from the computer 49, thereby drawing a pattern of the connection conductor pad 16 on the thick film wiring board 47.

Now, as described above, the thick film wiring board 47
Is shrunk by firing. This shrinkage ratio varies from substrate to substrate, and may vary within a plane even within the same substrate. Therefore, the position where the pad pattern 16 is drawn is fine and needs to be determined prior to drawing. In the present embodiment, when forming the via portion 13 in FIG. 1, the alignment mark 15 whose relative position to the via portion 13 is known is formed in advance. FIG.
Shows an example in which five alignment marks 15 are provided. Prior to drawing, the contracted state of the substrate is scanned with an electron beam on these marks, and the reflected electrons are detected by a detector 4.
8 to determine by detection. FIG. 7 shows an example of a method for estimating the position of the via section 13 from the backscattered electron detection signal Se.

As shown in FIG. 7A, when the alignment mark 15 on the substrate 47 is scanned by the electron beam 43,
The reflected electron signal 61 stronger than the edges b and c of the mark 15
Is obtained. The output signal Se of the detector 48 is as shown in FIG. The center coordinates of the mark can be obtained from the two peak positions b and c of the detection signal.

In FIG. 7A, reference numeral 60 denotes a resist layer for forming a pattern of the connection conductor pad 16. When the energy of the electron beam 43 is sufficiently high and the beam penetrates to the mark 15 at the bottom of the resist, the resist 60 may be left as it is, but when the energy is low and the two- or three-layer resist process is used, the incident electron
Does not reach In such a case, the resist around the mark part is thinned by means such as using an ion beam in advance, or
Alternatively, the mark may be completely removed to expose the mark. Thus, five coordinates of the mark 15 in FIG. 6 are obtained. Assuming that the position where the mark should originally be is 15 ', if the coordinates of the mark at the center are matched with the position where the mark should be,
For example, as shown in FIG. 6, it can be seen that the mark at the peripheral portion is located at a position 15 shifted inward from the position 15 'which should be originally due to the overall contraction of the substrate. From this, it is possible to predict the contraction rate of the substrate 10 in both the X and Y directions. That is, the original position 1 of the via portion 13
In contrast to 3 ′, the positions are shifted to 13 positions on the contracted substrate. In FIG. 1, the position P ′ which should be originally exists from the position of the connection terminal 23 to the LSI
0 is a known position (standard pattern position) determined according to the design of 0. On the other hand, the via position P existing on the substrate can be calculated from the measured value as described above.
These calculations are performed by the CPU 49. The difference DP = P′−P between the via position P ′ input to the drawing data memory 50 and the detected existing via position P is calculated, and P and DP are sent to the coordinate data generation unit 51.

These data are stored in the generator 51 for all vias. Based on this data, the pattern of the connection pads 16 is drawn by electron beam on the sample substrate 47. In drawing, the coordinate data 52 from the coordinate data generation unit 51 is converted into a deflection voltage to be applied to the deflector 45 via a D / A conversion unit 53, while the beam control unit 54
Generates a blanking voltage 57 to be applied to the blanker via a beam amplifier 56. The resist used for drawing can be either a positive type or a negative type.

In the above description, the electron beam is 100 m
It was possible to deflect over the range of mx 100 mm. However, it is generally not easy to deflect such a large area with the beam narrowed down. In this case, a so-called step-and-repeat method using both beam deflection and stage movement may be used. In the above embodiment,
Although five marks are represented over the entire area of 100 × 100 mm ² , when the contraction varies as a whole, it is necessary to detect the marks more finely. FIG. 8 is a diagram illustrating an embodiment in such a case. The thick film thin film multilayer wiring board 10 has a size of 100 × 100 mm ² ,
The substrate 10 is formed with via portions 13 having a diameter of 50 μm at a design pitch of 150 μm.

In this embodiment, a case where the via portion itself is used as a positioning mark instead of a special positioning mark will be described. The substrate 10 is divided into a plurality of blocks 63 each having a size of 10 × 10 mm ² , and the position of the via portion 13 in each block is measured to determine the deviation from the original position. No. 16 was formed. By adopting such a method, the memory circuit for storing the position of the via portion can be made as small as 1/100 of the method without block division. By calibrating the pattern formation position for each block, a highly accurate connection pad pattern 16 can be obtained.
Can be formed.

FIG. 9 shows another embodiment according to the present invention. The thick film thin film multilayer wiring board 10 is 100 ×
100 mm ² in size, and the substrate has a diameter of 50 μm.
m via portions 13 are formed with a design pitch of 150 μm. In the present embodiment, the following method was adopted, noting that the deviation of the actual via portion 13 formed on the substrate 10 from the reference pattern position 13 'depends on the distance from the substrate center. That is, as shown in FIG. 3B, the length L of the connection pad pattern 16 from the via portion 13 to its standard position 13 ′ is determined by the pitch of the via portion 13 (ie, the pitch of the via portion 13).
The substrate 10 was divided into nine blocks 63 'as shown in FIG.

As a result, in the block A, the deviation of the via portion from the original position was 150 μm or less, so that the positional deviation was corrected with a single connection pattern. In the block B, since the size of the deviation was 150 to 300 μm, the position of the via portion 13 was corrected using the two-layer connection pattern. Similarly, in block C, 300 to 4
The displacement of 50 μm was corrected with three layers. By using the above-described method, it is not necessary to form a long connection pattern on the substrate 10, so that the connection pattern forming process can be simplified and the yield can be improved.

FIG. 10 shows another embodiment according to the present invention. The thick-film thin-film multilayer wiring board 10 has 100
× 100 mm 2, and the substrate has a diameter of 50 mm.
A via portion 13 of μm is formed with a design pitch of 150 μm. LSI chips are to be arranged on the substrate 10 at positions spaced from each other as shown by 64 in FIG. Therefore, in the present embodiment, the above-described divided block is divided as indicated by 64 corresponding to the mounting position of each LSI chip. By doing so, it is possible to avoid forming a connection pattern for a via portion existing outside a block unnecessary for wiring,
Further, the formation of the correction connection pattern is also facilitated.

FIG. 11 is a diagram for explaining another embodiment of the present invention. When the deviation of the via portion formed on the substrate 10 shown in FIG. 8 from the standard position is measured, the deviation amount is shown in FIG.
As shown by b and c, it was found that the substrate 10 had regularity with the center 0 as the origin. Thus, consider the x-y coordinate system with the center of the substrate as the origin, the length L of the connection _{patterns, Δx ij = ax ij + by} ij + cx ij 2 + dy ij 2 + e Δy ij = fx ij + gy ij + hx ij 2 + ky _ij ² + m L = (Δx _ij ² + Δy _ij ² ) ^0.5 (where i, j indicate the via portion position with reference to the substrate center of the (i, j) th via portion). did. Here, the coefficients a to m were obtained by approximating the shift amounts shown in FIG. 11 by the least square method. According to the above method, the length L of the connection pattern can be analytically determined, and the pattern forming process can be simplified.

If the amount of deviation of the via portion from the reference position depends on the distance from the substrate center 0 as shown in FIG. 11, the substrate 10 is divided into a plurality of blocks 63 as shown in FIG. The block may be divided, and the inside of each block may be further divided into smaller sub-blocks (not shown). By performing the multiple division in this way, it is possible to perform position-dependent correction for each sub-block, and to perform drawing using a fixed correction amount within the same sub-block. Simplification and shortening of time were realized.

FIG. 12 shows an embodiment in which a matching layer 62 is provided to perform correction. In this embodiment, since the positional displacement between the via portion 13 and the wiring conductor 22 is large, the wiring for matching is changed to the X direction pattern 16 _X and the Y direction pattern 16 _Y.
In two layers, upper and lower. 16 _C is connecting conductor part between the two layers, 16 _I denotes an insulating layer. A wiring conductor 22 was provided on the two matching layers to connect with the LSI chip. When the lengths L _X and L _Y of the connection patterns in the two matching layers are still long, the matching layers may be further multilayered so that the pattern length in each layer is equal to or less than the pitch D of the via portion.

In the above embodiment, the thick film wiring board 1
In order to correct the distortion of 0, a new matching pattern 16 was provided as shown in FIG. 1 or a matching layer 62 was provided as shown in FIG.
By changing the drawing data of the middle wiring layer, the distortion on the side of the thick film wiring board 10 can be corrected and matched connection can be made. The position of the via portion on the thick film wiring board 10 is measured by one of the methods described later, and the position data of the wiring layer in the thin film wiring board 20 is changed so as to match the measured data. The change of the drawing pattern data is performed on the pattern data of the power supply wiring, the signal wiring, the metal pad, and the like in the thin film wiring layer. For example, after measuring the strain of the thick film wiring board 10 and dividing it in the X direction and the Y direction in the same manner as the method shown in FIG. 12, after changing the data of the position of the wiring conductor 22 by the distance corresponding to LX and LY, This creates a pattern for the wiring conductor 22. At the same time, other connection wiring layers in the thin film wiring board 20 connected to this are also created by changing data by a distance corresponding to the connection wiring layer. At this time, it is important that the size of the data to be changed is smaller than the via pitch D so that even the closest wirings do not come into contact with each other.

Next, measures against defects such as disconnection and short circuit of the via portion will be described. By some method as described later,
By detecting a disconnection of a via portion in the thick film wiring substrate 10 and a short circuit with another portion, and changing drawing data of a wiring layer in the thin film wiring substrate 20 so as to avoid use of the disconnected via portion and the shorted via portion. Even if there is a defect in the thick film wiring board 10, it operates normally. It is possible to produce a thick film thin film multilayer wiring board. FIG. 13 shows an example. Of the vias A, B, C, D, and E existing in the thick film wiring board 10, the via B was broken, and the via C was short-circuited with the via B. Therefore, connection between the vias B and C and the wiring on the thin film wiring board side is avoided, and vias A and D existing close to each other are used as shown in the figure. Therefore, the drawing data is changed and the connection pattern is changed as shown in the figure.

In the above, the connection position was corrected or changed by changing the existing drawing data based on the existing thin-film wiring board design data. However, the connection position was not changed but was completely new. It can be implemented by providing a correction layer for generating a connection pattern for performing a matching or a connection change. Further, the matching layer 62 described in the embodiment of FIGS. 1 and 12 may include the function of changing the drawing data and the function of changing the pattern by the correction layer. The above description is based on the result of the defect inspection in the thick film wiring board 10, but before connecting the final LSI, that is,
After the thin film wiring board 20 is formed on the thick film wiring board 10, a disconnection and a short circuit are inspected, and the drawing data is changed based on the inspection result, and the LSI is connected to the LSI 30 via a correction pattern (correction layer). A connection may be implemented.

Next, an energy beam used as a pattern forming means will be described. An electron beam, a light beam, or an ion beam can be used for the pattern forming means of the pattern forming apparatus described above. These pattern forming apparatuses also include a means for narrowing the beam and a deflecting means for deflecting and moving the narrowed beam to an arbitrary position on the sample. By these two means, it is possible to form a very fine pattern having a line width of about 10 nm for an electron beam, about 100 nm for light, or about several tens nm for an ion beam. . Further, an electron beam, an ion beam, or a light beam can be used for the above-mentioned dimension measuring means. Of course, these dimension measuring means also include a converging means and a deflecting means.

Although it has been described above that pattern formation and position measurement are performed using the same electron beam, an electron beam for measurement may be specially provided. FIG. 14 shows this embodiment. An electron beam mirror for measurement is provided beside the electron beam mirror for pattern formation (only the focusing lens 65 and the deflector 45 are shown in the figure). The electron beam mirror for measurement includes an electron gun 69 for measurement, a focusing lens 67 for measurement, a deflection coil 68 for measurement, and a secondary electron detector 66. The optical axis positions of the pattern-forming electron beam mirror and the measurement electron beam mirror on the sample substrate 47 are separated by a certain distance (L), but this value can be corrected by measuring in advance. . The advantage of this method is that
1) The pattern forming electron beam 43 and the measurement electron beam 71 can be set to different electron beam energies.
2) A dedicated electron optical system can be used for the measurement electron beam system so that a smaller electron beam diameter than that of the pattern formation electron beam system can be obtained. 3) Position measurement can be performed simultaneously with pattern formation, so that time can be reduced. In the description, the electron beam is also used for measurement, but as described above, another beam, for example, a light beam or an ion beam may be used.

Sample (substrate) 47 as an object to be measured
Is mounted on a stage 46 whose position is precisely measured by a laser interferometer or the like and whose position is controlled with good reproducibility by a stage control system 59. An existing pattern on the substrate is precisely measured from the movement of the stage 46 and a detection signal of secondary electrons (or reflected electrons) obtained by scanning of the measurement electron beam 71. The measurement method will be described later. If the existing pattern on the sample (substrate) 47 corresponds to the front and back pattern images, such as through holes, the pattern dimension can be measured from the back surface of the substrate. FIG.
Is an embodiment in which pattern dimension measurement is performed from the back side. The components are the same as in FIG. The advantage of this method is that, in addition to the advantage described with reference to FIG. 14, the dimensions can be measured even when the resist 71 is thickly applied on the existing pattern.

In the pattern formation according to the present invention, a new pattern is formed on the existing pattern by using an electron beam or the like. Performing pattern formation on it is meaningless. That is, the yield is reduced in the final stage. Therefore, if the pattern is formed while avoiding the heat of deterioration, the yield can be increased. The device of the present invention has a function of detecting a defective portion, and can perform pattern formation avoiding the defective portion. For detecting a defective portion, 1) use an electron beam for pattern formation, 2) provide an electron beam device dedicated for inspection,
3) An electron beam device dedicated for inspection may be provided on the back surface side. The methods 2) and 3) can be used also as an electron beam device for dimension measurement.

FIG. 16 shows an embodiment in which an electron beam for pattern formation is used for inspection. The potential of the potential supply power supply 75 is applied to the via 13 in the substrate from the lower surface side of the sample substrate 72 via the brush 73 and the electrode 74. The applied potential may be DC or AC. In the case of AC, synchronous detection becomes possible. The detection of a defective portion is performed by the following method. An electron beam 43 for pattern formation is scanned on the substrate 72, and a secondary electron scanning image is formed using the potential measurement display device 76. When the sample to which the potential is applied is observed with a secondary electron image, a bright and dark contrast appears. This is a phenomenon well known as potential contrast. When a potential is applied from the rear surface, what potential distribution appears on the upper surface of the substrate 72 is known from the design specifications of the wiring in the substrate. Therefore, the broken or shorted portion of the substrate can be known from the expected signal waveform and the observed signal waveform. As shown in FIG. 16, a reflection grid 78 is placed in front of the secondary electron detector 66, and a negative potential is applied to the reflection grid 78, whereby the potential contrast on the secondary electron image obtained can be enhanced.

The above description is based on the electron beam 43 for pattern formation.
Has been described as an embodiment in which the electron beam is also used as an electron beam for inspection. However, as described above, an electron beam device dedicated for inspection may be provided. First, FIG. 17 shows an embodiment in the case where it is provided on the front side of the substrate. Although this figure shows an example in which an electron beam device dedicated for inspection is provided, it is more effective to use the electron beam device for dimension measurement also. In this case, a reflection grid 78 is provided in front of the secondary electron detector 66. Then, a positive potential is applied to the reflective grid 78 when used for dimension measurement, and a negative potential is applied for inspection. Further, since the main body of the substrate 72 to be measured is an insulator such as ceramics, it is necessary to use a low energy electron beam of 1 kV or less even in the case of inspection in order to avoid charging the insulator surface. The inspection method is the same as that described with reference to FIG.

Next, FIG. 18 shows an embodiment of a method of performing inspection from the back surface of the substrate. Also in this case, it can be used also as the electron beam apparatus for dimension measurement shown in FIG. The front surface of the secondary electron detector 66 is also provided with a reflection grid 78 for enhancing the potential contrast. When the inspection is performed from the back surface, the electron beam 43 for pattern formation is used as means for applying a potential to the via 13. First, the pattern forming electron beam 43 is applied to the substrate 73.
Scan up. If the energy of the electron beam 43 for pattern formation is 1 kV or more, the via 13 which is insulated from the others by electron irradiation is charged to a negative potential. The subsequent detection method is the same as the method described with reference to FIGS. In this manner, disconnection and short-circuit can be inspected by the inspection-dedicated electron beam device provided on the back surface.

The measurement of the position coordinates of vias used as fiducial marks formed on the surface of the thick film wiring board using the position coordinate measuring device described above can have several variations. The following shows it. FIG. 19 shows a cross-sectional view of the thick film wiring board. The converged electron beam 43 is scanned from above as shown in the figure, the generated secondary electrons are detected, and the via position coordinates are measured. The secondary electron signal has a waveform as shown in FIG. 20 because the generation efficiency varies depending on the shape and material of the sample. When the electron beam is focused, the result is as shown in FIG. 3B. When each peak value is detected, each via 13 is automatically determined from the relative relationship with the scanning area of the electron beam (FIG. 3A). Can be determined. By measuring the position coordinates of all the vias in this way, highly accurate position coordinates can be obtained. Further, when the secondary electron signal is detected with the lens convergence condition at the final stage of the electron beam being defocused, the result is as shown in FIG. When an arbitrary slice level is set for this waveform and converted into a 1/0 pulse waveform, the waveform becomes as shown in FIG. 4D, whereby the presence / absence and position of the via can be easily determined. Under this condition, scanning can be performed with the electron beam coarsened two-dimensionally, and the measurement time can be reduced. As a method of further shortening the time, when measuring the tendency of the overall distortion of the thick-film wiring board, it is clear that the object can be achieved even by measuring several specially selected side fixed points.

Further, as shown in FIG. 21, a plurality of arbitrary reference marks 15 are set on the thick film wiring board 10, and the object can be achieved by measuring the reference marks.
As an example, a cross mark is used as a reference mark.
FIG. 22 shows the relationship between the electron beam scanning and the secondary electron signal waveform at that time. The coordinates of the center position of the marker can be measured by the same method as described above from the secondary electron signal waveform of FIG. 2B obtained corresponding to the electron beam scanning of FIG.

[0044]

The following effects can be obtained by employing the pattern forming method of the present invention.

First, the connection conductor pattern is formed by patterning the connection conductor pattern in consideration of the connection position with the thin film circuit formed thereon even if the shrinkage ratio of each ceramic or glass ceramic substrate is varied. This can prevent poor connection between the ceramic or glass-ceramic circuit and the thin-film circuit formed thereon, which occur conventionally.

Second, the connection conductor pattern has been changed from a conventional circular pattern having a diameter of 1000 μm to a band-shaped pattern having a width of 50 μm to 500 μm, thereby increasing the density of the conductor wiring in the substrate. Further, high-density mounting of a module such as an LSI on a substrate becomes possible.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a method of manufacturing a thick-film thin-film multilayer wiring board according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a conventional technique.

FIG. 3 is an explanatory diagram of a conventional technique.

FIG. 4 is an explanatory diagram of a conventional technique.

FIG. 5 is a schematic configuration diagram of an example of a pattern drawing apparatus using an electron beam used in the embodiment of the present invention.

FIG. 6 is an explanatory diagram of an example of a pattern matching method in the pattern forming method of the present invention.

FIG. 7 is an explanatory diagram of a pattern position detection method using an electron beam used in the present invention.

FIG. 8 is an explanatory diagram of one embodiment of a pattern forming method according to the present invention.

FIG. 9 is an explanatory diagram of one embodiment of a pattern forming method according to the present invention.

FIG. 10 is an explanatory diagram of one embodiment of a pattern forming method according to the present invention.

FIG. 11 is an explanatory diagram of one embodiment of a pattern forming method according to the present invention.

FIG. 12 is an explanatory diagram of another example of the pattern matching method according to the present invention.

FIG. 13 is an explanatory diagram of another example of the pattern matching method according to the present invention.

FIG. 14 is a partial schematic configuration diagram showing another configuration example of the pattern forming apparatus according to the present invention.

FIG. 15 is a partial schematic configuration diagram illustrating another configuration example of the pattern forming apparatus according to the present invention.

FIG. 16 is a partial schematic configuration diagram showing another configuration example of the pattern forming apparatus according to the present invention.

FIG. 17 is a partial schematic configuration diagram illustrating another configuration example of the pattern forming apparatus according to the present invention.

FIG. 18 is a partial schematic configuration diagram illustrating another configuration example of the pattern forming apparatus according to the present invention.

FIG. 19 is an explanatory diagram of a method of measuring pattern position coordinates used in the present invention.

FIG. 20 is an explanatory diagram of a method of measuring pattern position coordinates used in the present invention.

FIG. 21 is an explanatory diagram of a method of measuring pattern position coordinates used in the present invention.

FIG. 22 is an explanatory diagram of a method of measuring pattern position coordinates used in the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Thick film wiring board, 11 ... Alumina substrate, 12 ... Inner layer conductor, 13 ... Via part, 14 ... Land, 15 ... Alignment mark, 16 ... Connection conductor pad, 20 ... Thin film wiring board, 21 ... Insulating layer, 22 ... wiring conductors, 23 ... pads, 3
0: LSI, 31: LSI terminal, 32: solder, 62: matching layer.

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 21/027 H05K 3/10 C 23/12 H01L 21/30 541K H05K 3/10 23/12 N (72) Inventor Satoru Fukuhara 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. 292 Yoshida-cho, Totsuka-ku, Hitachi, Ltd.Production Technology Research Laboratory, Hitachi, Ltd. (72) Inventor Naka Yokono 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Hitachi, Ltd. 292 Yoshida-cho, Totsuka-ku, Hitachi Inside Hitachi, Ltd. Production Technology Laboratory (72) Inventor Hidetaka Shigi No. 1, Horiyamashita, Hadano-shi, Nara Prefecture, Kanagawa Plant, Hitachi, Ltd. (56) References JP-A-64-11328 (JP, A) JP-A-56-1225836 (JP, A) JP-A-58-73193 (JP) JP-A-62-272588 (JP, A) JP-A-58-73196 (JP, A) JP-A-63-144599 (JP, A) JP-A-62-14010 (JP, A) 62-156900 (JP, A) Japanese Utility Model Showa 62-84974 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H05K 3/46 G03F 7/20 G21K 5/04 H01L 21 / 027 H01L 23/12 H05K 3/10

Claims (4)

(57) [Claims] 1. A ceramic multilayer wiring board in which a plurality of alignment marks are provided at least at the periphery of an upper surface so as to reflect a contracted state from an original position and a plurality of via portions guided from a lower surface to an upper surface are embedded. Mark position detecting means for detecting the position of each of the plurality of alignment marks on the upper surface, a film forming apparatus for forming a conductive film on the upper surface of the ceramic multilayer wiring board, and a film formed by the film forming apparatus. A resin is applied on the conductive film, and the applied resin is drawn or exposed based on the position of each alignment mark detected by the mark position detecting means, and is developed to form a resin pattern. Lithography means, and an etching apparatus for etching the conductive film using a resin pattern formed by the lithography means as a mask, A matching conductor pattern forming system which is formed by matching and connecting each matching conductor pattern having an area larger than the area of each via portion in the multi-layered multilayer wiring board to each via portion, and each of the matching conductor pattern forming systems formed by the matching conductor pattern forming system. As each wiring conductor pattern is connected to the matching conductor pattern,
Forming a thin-film multilayer wiring circuit in which each of the wiring conductor patterns is embedded in an insulating material in a plurality of layers at standard positions based on the original positions of the respective alignment marks on the upper surface of the ceramic multilayer wiring board; A thin-film multilayer wiring circuit forming system connected to each of the wiring conductor patterns on the upper surface of the multilayer wiring circuit and arranging and forming a plurality of connection terminals for connecting and mounting a semiconductor element. This is a system for manufacturing thick-film thin-film hybrid multilayer wiring boards. 2. A ceramic multilayer wiring board in which a plurality of alignment marks are provided at least on the periphery of an upper surface reflecting a contracted state from an original position and a plurality of via portions guided from the lower surface to the upper surface are embedded. An inspection device for inspecting whether a buried via portion has a disconnection defect or a short-circuit defect, and a mark position detecting means for detecting a position of each of a plurality of alignment marks on the upper surface of the ceramic multilayer wiring board. ,
A film forming apparatus for forming a conductive film on the upper surface of the ceramic multilayer wiring substrate; and a resin applied to the conductive film formed by the film forming apparatus, and the mark position detecting means for the applied resin. Lithography means for drawing or exposing based on the position of each alignment mark detected by the method, developing and forming a resin pattern, and etching the conductive film using the resin pattern formed by the lithography means as a mask. A matching conductor pattern forming system for matching and forming each matching conductor pattern having an area larger than the area of each via portion in the ceramic multilayer wiring board to each of the via portions. As each wiring conductor pattern is connected to each matching conductor pattern formed by the forming system,
Forming a thin-film multilayer wiring circuit in which each of the wiring conductor patterns is embedded in an insulating material in a plurality of layers at standard positions based on the original positions of the respective alignment marks on the upper surface of the ceramic multilayer wiring board; A plurality of connection terminals connected to the respective wiring conductor patterns and for connecting and mounting a semiconductor element are formed and formed on the upper surface of the multilayer wiring circuit, and the vias embedded in the ceramic multilayer wiring board by the inspection apparatus are further formed. When it is inspected that a disconnection defect or a short-circuit defect exists in the portion, the wiring conductor pattern connected to each of the connection terminals in the thin-film multilayer wiring circuit from a defective via portion to a normal via portion in the ceramic multilayer wiring board. A system for manufacturing a thick-film / thin-film hybrid multilayer wiring board, comprising: a thin-film multilayer wiring circuit forming system for changing connection. 3. An inspection apparatus comprising: a stage on which the ceramic multilayer wiring board is mounted; a potential applying means for applying a potential to a via portion of the ceramic multilayer wiring board mounted on the stage; An electron beam irradiation optical system for deflecting and irradiating the focused electron beam to the via portion to which a potential is applied by the means, and the electron beam irradiation optical system deflecting and irradiating the focused electron beam according to the potential distribution of the existing pattern. 3. The system according to claim 2, further comprising a detector for detecting a secondary electron or a reflected electron and outputting a detection signal. 4. The matching conductor pattern forming system according to claim 1, wherein
The lithography means uses an electron beam to
The electron beam drawing apparatus for drawing
Manufacture of thick film hybrid multilayer wiring board Motomeko 1 or 2, wherein
System .