JP3258081B2 - Viterbi decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a maximum likelihood decoder for decoding convolutionally encoded information, and more particularly to a Viterbi decoder effective for a magnetic recording and reproducing apparatus such as a digital VTR.

[0002]

2. Description of the Related Art In recent years, Viterbi decoding has been widely used as one of the maximum likelihood decoding methods for performing decoding while maximizing information contained in a signal. This Viterbi decoding is more widely used in the communication field than in the past. Research is being done. On the other hand, digital VTRs that have been actively researched and developed recently
Since it is necessary to record a digital television signal having several times the amount of information as compared with a conventional analog signal, it is necessary to extremely increase the recording density. As a result, the S / N ratio of the reproduced signal is considerably reduced, and the conventional bit-by-bit decoding becomes extremely difficult. Therefore, there is a demand for performing decoding by effectively utilizing information contained in such a low S / N reproduction signal as much as possible.
Among them, the Viterbi decoding is a decoding method that has attracted attention because it is theoretically clear that the S / N is effectively improved by about 3 dB. The case where Viterbi decoding is used for decoding NRZI and interlibrated NRZI will be described as the simplest application.

In the NRZI, as represented by a precode block shown in FIG. 9, an exclusive OR operation of an input signal a _k and a delayed signal b _k-1 is performed to generate b _k , and this is recorded in a magnetic recording device.

B _k = a _k (+) b _k−1 (1) When this is reproduced, the reproduced signal z _k becomes b _k −b _k−1 because the magnetic recording system has a differential characteristic. This signal system has two states Sk = {+ 1, -1}.

Z _k = b _k −b _k−1 (2) FIG. 10 shows this in a state transition diagram. When the reproduction signal z is +2, the state S changes from −1 to +1 and when the reproduction signal z is −2, The state S transitions from +1 to −1, and when 0, no state transition occurs. When the reproduced signal does not include noise, the detected signal is one of z _k = {− 2, 0, +2}, and thus the state transition is uniquely determined. However, as shown in the following equation (3): The signal y _k actually detected includes noise _nk .

Y _k = z _k + n _k (3) If the noise has a Gaussian distribution, the Euclidean distance between y _k and z _k , that is, z _k that minimizes (y _k −z _k ) ² is transmitted. It is possible to perform maximum likelihood decoding by estimating that The maximum value of the sum of {− (Euclidean distance)} up to state j at time k is called a metric of state j, and is represented by L _K ^j . When the metric of the state i at the time k-1 is L _k-1 ⁱ , the metric L _K ^j of the state j at the time k is represented by the following equation.

L _K ^j = max ｛L _k−1 ⁱ − (y _k −z _k ^ij ) ² ｝ (4) At this time, L _K ^j is given. From state i at time k−1 to state j at time k Is stored as a “survival path”, and the Viterbi decoding is performed cyclically in each state j at each time k. In the case of NRZI, as described above, the number of states is 2, so i (or j) = ｛+ 1,
-1}, and reference z _k ^ij = {+ 2, 0, -2}
It is. This is represented by a trellis diagram as shown in FIG.

[0008] As described above, Viterbi decoding is the maximum likelihood decoding which can decode a detected signal sequence into a signal sequence having the shortest distance and, therefore, the most probable signal sequence. Can be. Therefore, a large effect can be expected in a system having a low S / N such as a digital VTR. By the way, in order for Viterbi decoding to function effectively, it is necessary to make it possible to assume that the noise _nk has a Gaussian distribution centered on the reference level z _k, as is apparent from equation (3). If the detected signal y _k has a level fluctuation other than the signal z _k and the Gaussian noise _nk , the meaning of the metric is lost,
Normal decoding becomes impossible. Therefore, a gain control loop circuit is indispensable at the previous stage of the Viterbi decoder in order to sufficiently suppress such level fluctuation.

FIG. 12 is a block diagram of a Viterbi decoder and a reproducing system using the Viterbi decoder. The reproduced signal is firstly suppressed in level fluctuation by an AGC (automatic gain controller) 61, adjusted in signal characteristics by an EQ (equalizer) 62, and then converted into a 6-bit digital signal by an ADC (analog / digital converter) 37. And input to the Viterbi decoder. (Digital E
If Q is used, the ADC is placed before it. It is known that, when performing Viterbi decoding, 6 sampling bits are sufficient. In the Viterbi decoder, first, a branch metric calculation circuit 38 calculates a distance between input digital data and a reference level for each transition, that is, a branch metric. Next ACS
The (Add-Compare-Select) circuit 40, each branch metric after being compared is added to the path metric 39, resulting in maximum metric "survivor path" is stored in the path memory 41, also the path metric by this maximum metric 39 To update. The data can be decoded by sequentially reading the contents of the path memory 41.

On the other hand, in the case of the interleaved NRZI, as shown in FIG. 13, recording is performed after performing a precode for delaying by two bits. Therefore, if the even-numbered bit string and the odd-numbered bit string are clearly separated, each can be regarded as an NRZI, so that the decoding is independently performed by the two Viterbi decoders to form one decoded bit sequence. This block diagram is shown in FIG. Here, FIG.
Are provided, and even-numbered column data and odd-numbered column data digitized by shifting the sample time by one bit time T are decoded by independent Viterbi decoders. Path memory 5 from AGC 42
Up to 3 is basically the same as FIG. The data series decoded by each decoder is finally converted into one decoding sequence by the parallel / serial converter 54. By performing decoding processing in parallel using two decoders in this manner, AD
The operating speed required for C or the decoder can be halved.

[0011]

The greatest concern when using Viterbi decoding in a digital VTR is the level fluctuation described above. This is because a VTR that scans a soft magnetic tape at a high speed and reproduces a weak signal has a characteristic that a reproduction signal level largely fluctuates due to a slight change in a slight gap between the tape and the head. . (This is well known as a spacing effect.) Therefore, it is considered inevitable that an AGC having higher performance than that used in a communication system or the like is required.

However, according to recent research, in high-speed running reproduction required for a digital VTR such that the relative speed between a magnetic tape and a reproducing head exceeds 10 m / s, it is very instantaneous (for example, in a time of about 100 ns). It has been reported that relatively small level fluctuations (herein referred to as short dropouts) of about 2 dB frequently occur, and this is a main cause of errors. Conventionally, it has been extremely difficult for an AGC to have such a high-speed response and to operate stably, so that it has not been possible to effectively apply Viterbi decoding to a digital VTR.

The present invention has been made in view of the above problems, and has as its object to provide a Viterbi decoder suitable for a digital VTR, adapted immediately to a level change.

[0014]

In order to achieve the above object, according to the present invention, means for holding a reference level used for branch metric calculation is provided, and a reference level Z corresponding to a surviving path selected by the ACS is read. However, an operation of ((n-1) Z + Y) / n (n> 1) is performed with respect to this and the input signal level Y, and a recurrence operation reference updating means is provided for setting the result as a new reference level. When the input signal is sampled with 6 bits, n = 4.

Further, when the input analog signal sequence is converted into a plurality of digital signal sequences and each digital signal sequence is decoded, the branch metric calculation is performed based on the reference level held by only one reference level holding means. And changes the reference level sequentially by calculating the reference level and the input level corresponding to the selected surviving path.

[0016]

According to the present invention constructed as described above, the reference level instantaneously adapts to the short dropout, and always maintains the optimum level, whereby the influence of the short dropout can be minimized. , VTR can be significantly reduced in error with respect to the VTR. Also,
By setting n = 4 when input data is sampled with 6 bits, it is possible to update the reference level with a minimum hardware scale and not hinder Viterbi decoding.

Further, even when one input analog signal sequence is time-divided into a plurality of sequences and decoded in parallel as in the case of an interleaved NRZI, it is possible to update the reference level with good followability and perform correct decoding. it can.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a first embodiment of a magnetic recording / reproducing apparatus including a Viterbi decoder to which the present invention has been applied.

In FIG. 1 , the amplitude of a reproduced input signal is suppressed to some extent by an AGC 1 , a waveform is equalized by an EQ 2, and 6-bit digital data is obtained by an ADC 3.
Up to this point, it is almost the same as the conventional example.

The Viterbi decoder has a reference memory 4 holding a level to be a reference, and a branch metric circuit 5 outputs a branch metric in each state according to a reference value and input data. In the NRZI decoding example used in the description of the conventional example, the reference value for transition from state i to state j at time k is a level corresponding to Z _k ^ij .

The details of the initial setting of the reference value will now be described. Since the VTR can obtain a reproduction signal only during a period in which the rotary head is in contact with the tape, the VTR becomes an intermittent signal as shown in FIG. A reproduction signal is extracted from this signal in accordance with the reproduction gate shown in FIG.
(C)). In this embodiment, a specific pattern pilot signal for reference setting of the Viterbi decoder is reproduced in an initial portion of the reproduced signal, that is, in a hatched portion in FIG. The level fluctuation is averaged by the specific pattern pilot reproduction signal, and the influence of waveform interference and nonlinear distortion that cannot be eliminated by the equalizer can be ignored and compensated. In the present embodiment, {0, +2, 0,
-2, 0, ...}. As soon as the reproduction signal is generated, the initialization control signal 11 is generated, the path metric 7 is cleared, and the reference level is loaded from the initial value memory 10 to the reference memory 4.
In the present embodiment, the initial value is {+2, 0, -2}. Using this as the initial value Z, the reference memory is corrected by the specific pattern pilot reproduction signal Y. Then, the Viterbi decoding is started when the path metric 7 is cleared again by the decoding start signal 12 at an appropriate position. This initial setting is not limited to the method shown in the present embodiment, and may be performed a plurality of times during a continuous reproduction signal, and the timing may be at the center or the last part of the reproduction signal.

Returning to the operation of the Viterbi decoder, the branch metric circuit 5 determines the branch metric with the input data Y _{k for} each state, that is, ｛− (Y
_k− Z _k ^ij ) ²計算 is calculated. The ACS 6 adds the path metric L _k−1 ⁱ obtained from the path metric 7 and the branch metric according to the equation (4), updates the path metric 7 with the largest metric as the next path metric L _k ⁱ , and updates the surviving path. Is stored in the path memory 8. Then, a decoded signal 13 is obtained by sequentially reading the path memory 8. At this time, the reference value Z _k ^ij corresponding to the surviving path selected by the ACS 6 is called from the reference memory 4, and the reference update circuit 9 performs the next operation with the input level Y _k to update the reference level. .

Z _{k + 1} ^ij = (Y _k + (n−1) Z _k ^ij ) / n (5) FIG. 4 is a block diagram of the reference update circuit 9. The input signal level _Yk is determined by a synchronous clock (C
By LK), is buffered with a D flip-flop (FF) 31, by subtracting the reference value Z _k ^ij subtractor 32, is the 1 / n by the divider 34 after being buffered again DFF33. In fact, if n is chosen to be a power of two (2 ^m ), divider 34 only shifts the data by m bits. By adding Z _k ^ij to the result by the adder 35, the right side of the equation (5) can be generated.

(Y _k −Z _k ^ij ) / n + Z _k ^ij = right side of equation (5) (6) The reference level can be updated by buffering this in the DFF 36 and setting it as the next Z _{k + 1} ^ij. . Next, the fluctuation of the reference level depending on the value of n will be described.

FIG. 5 shows how the short dropout phenomenon is simulated. Since the input signal is sampled in 6 bits, the digital data is 0 to 6 bits.
Take 3 levels. Here, it is assumed that the central 32 levels are continuous, and the S / N at this level is set to 20 dB. The number of samples is 500. In the period of 100 to 200 samples and 300 to 400 samples, the level drops to 24 due to short dropout. This 100 sample period is 100Mbps
Is equivalent to 1 μs. FIGS. 6 to 8 show variations of the reference level according to the embodiment of the present invention with respect to such an input.
This is the case for 2, 4, and 8. The ideal reference level change is 32 for samples 0 to 100, 24 for samples 100 to 200, and so on. n =
According to FIG. 6 in the case of No. 2, it can be clearly understood that the response of the change of the reference level is quick and follows the signal change of several samples. However, in this case, since the change in the reference level is greatly affected by noise, the change in the reference level is an obstacle to Viterbi decoding. In FIG. 8 where n = 8, there is almost no influence of noise, but the change time of the reference level exceeds 100 samples, so that short dropout cannot be completely compensated. Thus, in the embodiment of the present invention, n shown in FIG.
= 4 was used.

As a result, the change of the reference level becomes 10 samples (about 100 ns at 100 Mbps).
Further, the influence of noise could be reduced to less than 1 dB.

As a method of controlling a reference value based on past input data, a method described in Japanese Patent Application Laid-Open No. 62-18118 is known as a known technique. The technique described in this publication takes a simple average value of past data and controls a reference value according to the average value. On the other hand, in the present embodiment, since the reference value is changed by the recurrence formula based on the past data, each data can be weighted. Therefore, it is possible to quickly respond to a sudden change in the reference value.

Next, a description will be given of a second embodiment in which the present invention is applied to an interlibrated NRZI. FIG. 2 is a block diagram showing the configuration of the second embodiment. This is a Viterbi detector for the interleaved NRZI taken up in the conventional example. As shown in FIG. 14, the input analog signal sequence has two ADCs 16 and 1 having different sampling timings.
The data is digitized at 7 and separated into an even bit string and an odd bit string. Of course, the digital signal by one ADC can be temporally switched to separate even and odd bit strings. After being decoded by the NRZI Viterbi detector, they are combined into one decoded bit string. At this time, two Viterbi detectors are
It is of course conceivable to use the Viterbi detector according to the present invention described in the above.
Obviously, the number of sets is required, the circuit becomes large-scale, and the followability is deteriorated because the originally continuous reference level fluctuation is detected separately in the even bit string and the odd bit string. Therefore, according to claim 3, only one reference memory 27 and reference updating circuit 26 are provided, so that the reference levels used in the two Viterbi detectors can be held and sequentially corrected. The input changeover switches 29 and 30 are connected to a Viterbi detector for even-numbered bit strings or a Viterbi detector for odd-numbered bits according to the processing timing of data divided into even-numbered bit strings and odd-numbered bit strings. That is, when an even-numbered bit is input, the reference update circuit obtains this input by the switch 29, and obtains the path information in which the ACS is selected by the switch 30 to update the reference memory. Is switched, the reference memory is updated again.
Thereafter, by repeating this, the reference memory is updated each time data is input to either side, so that the reference memory can be updated quickly, and the reference memory can be corrected with good followability to the short dropout. .

[0029]

As described above, according to the present invention, the operation of the formula (5) is performed from the reference value and the input data, and the reference value is successively updated by the recurrence operation, so that the short dropout is prevented. The influence can be eliminated and proper Viterbi decoding can be performed, and the decoding capability when the Viterbi decoder is applied to a VTR can be dramatically improved.

Further, when the data is sampled with 6 bits, by setting n in equation (5) to 4, it is possible to easily follow a short dropout of several tens of symbols by simple hardware and to reduce noise. The effect is obtained that a Viterbi decoder that is not easily affected can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a Viterbi decoder according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a Viterbi decoder according to a second embodiment of the present invention.

FIG. 3 is a time chart showing a reproduction signal and an initialization bilot signal.

FIG. 4 is a block diagram showing a detailed configuration of a reference update circuit.

FIG. 5 is a characteristic diagram showing a simulation data sequence of short dropout.

FIG. 6 is an explanatory diagram showing a change in a reference value due to a recurrence operation when n = 2.

FIG. 7 is an explanatory diagram showing a change in a reference value due to a recurrence operation when n = 4.

FIG. 8 is an explanatory diagram showing a change in a reference value due to a recurrence operation when n = 8.

FIG. 9 is a block diagram showing a signal system of NRZI.

FIG. 10 is a state diagram of NRZI.

FIG. 11 is a trellis diagram of NRZI.

FIG. 12 is a block diagram showing a configuration of a conventional Viterbi decoder and a reproduction system for NRZI.

FIG. 13 is a diagram showing a precoded block of an interleaved NRZI.

FIG. 14 is a block diagram showing the configuration of a conventional Viterbi decoder and a reproduction system for an interleaved NRZI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Automatic gain control means (AGC) 2 Equalizer (EQ) 3 Analog-digital converter (ADC) 4 Reference memory 5 Branch metric calculation circuit 6 Addition / comparison / selection circuit (ACS) 7 Path metric memory 8 Path memory 9 Reference update circuit 10 Initial value memory 11 Initial setting control signal 12 Decoding start signal 13 Decoded signal 31, 33, 36 D flip-flop 32 Subtractor 34 Divider (or bit shift means) 35 Adder

Claims (3)

(57) [Claims] A reference level storage unit for storing a reference level; a branch metric calculation unit for performing a branch metric calculation based on the reference level held by the reference level storage unit; a path metric storage unit for holding a path metric; Surviving path selection and storage means for selecting and storing a surviving path based on the branch metric and the path metric held by the path metric storing means, and a path metric for updating the next path metric based on the branch metric and the path metric Updating means; calculating a reference level corresponding to the selected surviving path and an input level to obtain a new reference level; and sequentially changing the reference level held by the reference level holding means to a new reference level. And means for changing the recurrence calculation standard. The calculation criterion changing unit calculates the recurrence calculation formula Z _{k + 1} ^ij = (Y _k + (n−1) Z _k ^ij ) / n (where Y _k is the input level at time k, and Z _k ^ij is the state i at time k. A reference level for the transition from to state j, where n is a predetermined number of samplings and n> 1), to obtain a new reference level Z _{k + 1} ^ij . 2. The recurrence calculation reference changing means includes a subtraction means for obtaining a difference between a current reference value Z _k and a current input data Y _k, and a difference between the current reference value Z _k and a predetermined sampling number n (n> n).
1) dividing means for dividing the result by the reference value Z _k
2. A Viterbi decoder according to claim 1, further comprising: adding means for adding the result to the next reference value Z _{k + 1} . 3. A plurality of Viterbi decoders according to claim 1, wherein an input analog signal sequence is converted into a plurality of digital signal sequences and decoding is performed on each digital signal sequence. The branch metric calculation is performed based on the reference level held by the one reference level holding unit, and the calculation of the reference level and the input level corresponding to the surviving path selected by the single recurrence calculation reference changing unit is performed. A Viterbi decoder for sequentially changing a reference level.