JP3257062B2 - Current source circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current source circuit using MOS transistors used in the fields of electronic equipment and communication.

[0002]

2. Description of the Related Art In recent years, a current source circuit using a MOS transistor has been required in the field of electronics and the like.

A conventional current source circuit using a MOS transistor will be described below. FIG. 4 is a configuration diagram of a current source circuit using a conventional MOS transistor, where R is a resistor, and M1 and M6 are of the same type having first conductive characteristics.
MOS transistor, V _DD power supply terminal belonging, V _O is the output terminal, V _GS is the MOS transistors M1 and M6
Is the gate-source voltage .

In this current source circuit, first, when a voltage is applied to the power supply terminal V _DD , the MOS transistor M1 operates in a saturation region, and a current I _DS flowing through the MOS transistor M1 appears. Here, M described by three terminals
The OS transistor is located in the bulk where the channel is formed.
Since a reference potential such as ground is given, the potential of the bulk
There is no back gate effect caused by fluctuation . Also,
A phenomenon similar to the Early effect in an bipolar transistor.
Is the channel length modulation effect in MOS transistors
However, this channel length modulation effect is
Because it is caused by fluctuations in the drain-to-drain potential,
It can be ignored by increasing the value of the tunnel length . Further, the output terminal V _O is set to a voltage high enough to keep the MOS transistor M6 in a saturated state.

In this example, V _DD = RI _DS + V _GS I _DS = K (V _GS -V _T ) ² .

Here, K is a proportionality constant representing the characteristics of the MOS transistor, called a gain factor, and is expressed by the following equation.

K = (μ _n C _ox ) / 2 · (W / L ′) where μ _n : electron mobility C _ox : oxide film capacity W: gate width L ′: effective gate length where V _O > when the V _G over V _T, MOS transistor M
6, the MOS transistors M1 and M6 operate at a current mirror ratio of 1. Therefore, the current I _OUT appearing at the output terminal is I _OUT = I _DS . For example,
V _DD = 5 (V), V _T = 1 (V), K = 100 (μA /
V ² ) and R = 30 (kΩ), V _GS = 2 (V) and I _DS = 100 (μA). Further, when the output current is V _O > 1 (V), the MOS transistors M1,
Propagated by the current mirror circuit composed of M6,
_OUT = 100 (μA).

[0008]

The size of the 0005, however the output current in the conventional arrangement described above, variations in the MOS transistor characteristics, have the disadvantage that particularly greatly affected by the-threshold voltage V _T and the gain factor K Was. This-threshold voltage V _T and the gain factor K
Is generally known to vary by about ± 30%.

Here, the threshold voltage V _T is
The output current I _OUT when the standard value 1 (V) of V _T if I _STD, V _T is V _T standard 1.5 (V) from 0.5 (V)
When varies ± 50% with respect to the value, the ratio I _OUT / I _STD in the range of 1.15 0.85 in the conditions applied in the calculation example of the conventional art and the output current I _OUT to the above I _STD Vary. The (I _OUT / I _STD) characteristics for the V _T shown in solid lines (1) in FIG.

The proportional constant K representing the characteristics of the MOS transistor is a standard value of K of 1.00 × 10 ⁻⁴ (A / V ² ).
_Assuming that the output current I _OUT at the time of is I _STD , K is 5.00.
× 10 ^-5 (A / V ² ) to 2.00 × 10 ^-4 (A / V ² )
Varies with time in, I _OUT / I _STD in the above calculation example the same conditions, vary in the range of 1.1 to 0.88. To the K
The corresponding (I _OUT / I _STD ) characteristic is shown by the solid line (1) in FIG.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a current source circuit using a MOS transistor capable of absorbing variations in MOS transistor characteristics _VT and K.

[0012]

In order to achieve this object, a current source circuit using a MOS transistor according to the present invention comprises:
A MOS transistor is connected in parallel to the output MOS transistor of a current source circuit using a conventional MOS transistor, and the increase and decrease of the output current are output via a current mirror circuit composed of reverse type MOS transistors, a load and the MOS transistor. By adding a feedback circuit to the circuit that defines the current, a configuration is provided that reduces the variation in the ratio between the output current I _OUT and the reference current I _STD .

[0013]

With this configuration, it is possible to reduce the influence on the output current due to variations in the characteristics _VT and K of the MOS transistor.

[0014]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a current source circuit using MOS transistors according to an embodiment of the present invention. In Figure 1, R ₂ is resistance, M2, M3 are MOS transistors, M4, M5 is a MOS transistor M2 is opposite type of MOS transistor.

In the current source circuit of this embodiment, first, M
A MOS transistor M is connected in parallel with the OS transistor M6.
1 and a MOS transistor M2 of the same size as
The output current is fed back by the MOS transistor M3 via a current mirror circuit having a current mirror ratio of 1 constituted by the OS transistors M4 and M5.

In this embodiment, V _DD = RI + V _GS V _GS3 = R ₂ I _DS I = I _DS + I _DS3 V _GS = (I _STD / K) ^1/2 + V _T V _GS3 = (I _DS3 / K ₃ ) ^1/2 + V _T

First, when a voltage is applied to the power supply terminal V _DD , the MOS transistor M1 operates in a saturation region. When a current I _DS flowing through the MOS transistor M1 increases, a current mirror circuit formed by the MOS transistors M4 and M5 is activated. Via M
The gate voltage of the OS transistor M3 increases, and the current I _DS3 of the MOS transistor M3 increases. Therefore, feedback is applied to reduce I _DS . Conversely, when I _DS flowing through the MOS transistor M1 decreases, the gate voltage of the MOS transistor 3 decreases via the current mirror circuit, and the current I _DS3 of the MOS transistor 3 decreases. Therefore, feedback that increases I _DS is applied.

By returning to the reference current in this manner, an output current I _{OUT which} is not affected by variations in MOS transistor characteristics appears.

Here, when V _O > V _G -V _T , the MOS transistor M6 performs a saturation operation, and the MOS transistor M2 and the MOS transistor M6 operate at a current mirror ratio of 1.

Therefore, the current I _OUT appearing at the output terminal
Becomes I _OUT = I _DS . For example, I _STD = 100 (μ
A), V _DD = 5 (V), V _T = 1 (V), K = 100
(ΜA / V ² ), V _GS = 2 (V), and if R = 25 (kΩ) and R ₂ = 20 (kΩ), I _DS3
= 20 (μA) and K ₃ = 20 (μA / V ² ).

At this time, the threshold voltage V
_T is the output current I _OUT when the standard value 1 (V) of V _T I
When _STD, V _T is V at 1.5 (V) from 0.5 (V)
When there is a variation of ± 50% with respect to the _T standard value , (I _OUT / I
_STD ) varies from 0.97 to 1 and falls within about 1/10 of the conventional example. For this V _T (I _OUT / I
_STD ) characteristics are shown by the broken line (2) in FIG.

The proportional constant K representing the characteristics of the MOS transistor is a standard value of 1.00 × 10 ⁻⁴ ( A / V ² ).
If the output current IOUT at this time is ISTD, K is from 5.00 × 10 ⁻⁵ (A / V ² ) to 2.00 × 10
^-4 ( A / V ² ), I _OUT / _ISTD becomes 0.
It fluctuates in the range of 95 to 1, and falls within about 1/5 of the conventional example. Shows the (I _OUT / I _STD) characteristics for the K in broken line in FIG. 3 (2).

As described above, according to the present embodiment, the variation of I _OUT / _ISTD can be reduced by feeding back the output current.

In the description of this embodiment, N channels M
Although the example using the OS transistor has been described, it goes without saying that a P-channel MOS transistor may be used as the reference MOS transistor.

In the description of this embodiment, MOS transistors M1, M2, M6 and MOS transistors M4, M4
Although M5 has the same dimensions, those dimensions can be appropriately determined by a circuit.

[0027]

As described above, according to the present invention, by providing feedback of the output current, it is possible to realize a current source circuit using an excellent MOS transistor capable of reducing the variation of the output current.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a current source circuit using a MOS transistor according to an embodiment of the present invention.

With respect to FIG. 2 _{V T (I OUT / I STD} ) characteristic diagram

FIG. 3 is a characteristic diagram of (I _OUT / I _STD ) with respect to K.

FIG. 4 is a configuration diagram of an example of a conventional current source circuit.

[Explanation of symbols]

R, R ₂ resistance M1 to M6 MOS transistor V _DD power supply terminal V _O output terminal

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-218012 (JP, A) JP-A-3-16406 (JP, A) JP-A-4-186906 (JP, A) JP-A 63-218 6908 (JP, A) JP-A-63-245509 (JP, A) JP-A-4-160511 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03F 1 / 42-3 / 52

Claims (2)

(57) [Claims] A gate and a source commonly connected to each other;
A first terminal connected to the power supply terminal and a second terminal connected to the first MOS transistor;
A first resistor connected to the gate and drain of the transistor; and a MOS transistor pair.
One of the transistors is directly connected to the second MOS transistor.
Connect the second MOS transistor from the other transistor
A current mirror that outputs a current corresponding to the transistor current
Circuit and the other MOS transistor of the current mirror circuit
A second resistor connected in series with the first resistor and a voltage generated at the second resistor applied between the gate and the source.
MOS transistor for generating drain current
And the drain current of the fourth MOS transistor
1 and the connection of the first MOS transistor.
Current path to be output, and an output terminal for outputting the current of the third MOS transistor.
And the first to fourth MOS transistors are of the first conductivity type M
OS transistor, which is a transistor of the current mirror circuit.
The transistor pair is a second conductivity type MOS transistor.
And a current source circuit. 2. A mirror ratio of the current mirror circuit 1
The current source circuit according to claim 1, wherein