JP3257045B2 - Semiconductor laser - Google Patents

Semiconductor laser

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Publication number
JP3257045B2
JP3257045B2 JP18977492A JP18977492A JP3257045B2 JP 3257045 B2 JP3257045 B2 JP 3257045B2 JP 18977492 A JP18977492 A JP 18977492A JP 18977492 A JP18977492 A JP 18977492A JP 3257045 B2 JP3257045 B2 JP 3257045B2
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JP
Japan
Prior art keywords
layer
buried layer
type
semiconductor
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP18977492A
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Japanese (ja)
Other versions
JPH0637392A (en
Inventor
辰也 竹内
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of JPH0637392A publication Critical patent/JPH0637392A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は活性層を含むメサを迂回
して埋込み層中を流れるリーク電流が小さい半導体レー
ザに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser having a small leakage current flowing in a buried layer by bypassing a mesa including an active layer.

【0002】半導体レーザでは,発光効率を向上してし
きい値電流を低減し,出力を増大するために,活性層を
含むメサを高抵抗層で埋込み,電流をメサに集中する構
造が多く用いられている。
2. Description of the Related Art In a semiconductor laser, a structure in which a mesa including an active layer is buried in a high-resistance layer and a current is concentrated on the mesa is often used in order to improve luminous efficiency, reduce a threshold current, and increase output. Have been.

【0003】かかる構造の半導体レーザは,埋込み層の
電気抵抗が小さい場合には,メサを迂回するリーク電流
が多くなり発光効率が低下する。このため,半導体レー
ザの製造の際に生ずる埋込み層の抵抗の低下を防止し,
メサを迂回して埋込み層中を流れるリーク電流を小さく
する必要がある。
In the semiconductor laser having such a structure, when the electric resistance of the buried layer is small, the leakage current bypassing the mesa increases and the luminous efficiency decreases. For this reason, it is possible to prevent a decrease in the resistance of the buried layer which occurs during the manufacture of the semiconductor laser,
It is necessary to reduce the leak current flowing in the buried layer bypassing the mesa.

【0004】[0004]

【従来の技術】図3は,従来の半導体レーザ断面図であ
り,メサストライプ構造の埋込み型半導体レーザを表し
ている。
2. Description of the Related Art FIG. 3 is a sectional view of a conventional semiconductor laser, showing a buried semiconductor laser having a mesa stripe structure.

【0005】従来の半導体レーザは,図3を参照して,
半導体基板1上に形成されたストライプ状のメサ7が高
抵抗層8により埋め込まれ,メサ7の上面及び基板の下
面にそれぞれ上電極9及び下電極10が設けられる。
A conventional semiconductor laser is shown in FIG.
A stripe-shaped mesa 7 formed on the semiconductor substrate 1 is filled with a high-resistance layer 8, and an upper electrode 9 and a lower electrode 10 are provided on the upper surface of the mesa 7 and the lower surface of the substrate, respectively.

【0006】基板1はn型半導体結晶,例えばInP等
の化合物半導体を用いることができる。メサ7は,基板
上に順次堆積された,n型InGaAsPからなるガイ
ド層2,InGaAsPからなる活性層3,クラッド層
4として例えばZnを添加したInPからなるp型半導
体層4,p型InGaAsPからなるコンタクト層5を
有する。
As the substrate 1, an n-type semiconductor crystal, for example, a compound semiconductor such as InP can be used. The mesa 7 comprises a guide layer 2 made of n-type InGaAsP, an active layer 3 made of InGaAsP 3, a p-type semiconductor layer 4 made of, for example, Zn-doped InP, and a p-type InGaAsP deposited as a cladding layer 4 on the substrate. Having a contact layer 5.

【0007】メサ7を埋め込む高抵抗層8には,深いア
クセプタ準位を形成する不純物を添加してキャリア濃度
を低くした高抵抗の半導体,例えばFeを添加したIn
Pが用いられる。
The high-resistance layer 8 in which the mesas 7 are buried is doped with an impurity for forming a deep acceptor level to reduce the carrier concentration.
P is used.

【0008】かかる埋込み型半導体レーザでは,上下電
極9,10間を流れる電流は高抵抗層8に阻まれ,活性
層を含むメサ7に集中して流れるため電流の利用効率が
高い。
In such a buried semiconductor laser, the current flowing between the upper and lower electrodes 9 and 10 is blocked by the high resistance layer 8 and flows intensively into the mesa 7 including the active layer, so that the current utilization efficiency is high.

【0009】しかし,埋込み層8を堆積するとき,メサ
7の側壁に表出するp型半導体層4と埋込み層8とが接
触するために,p型半導体層4中の不純物が埋込み層8
に拡散する。
However, when the buried layer 8 is deposited, the p-type semiconductor layer 4 exposed on the side wall of the mesa 7 and the buried layer 8 come into contact with each other, so that impurities in the p-type semiconductor layer 4 are removed.
To spread.

【0010】このp型不純物は埋込み層8中の深いアク
セプタによっては補償されないためメサ7の近傍の埋込
み層8がp型導電型に変換される結果,埋込み層8の電
流阻止機能が低下しリーク電流が増加するのである。
Since the p-type impurity is not compensated by the deep acceptor in the buried layer 8, the buried layer 8 in the vicinity of the mesa 7 is converted into the p-type conductivity. The current increases.

【0011】[0011]

【発明が解決しようとする課題】上述したように従来の
構造の半導体レーザでは,メサと接触する埋込み層にメ
サに含まれるp型半導体層中の不純物が拡散して埋込み
層の抵抗が低下するため,埋込み層の電流阻止機能が低
下しリーク電流が増加するという問題がある。
As described above, in the semiconductor laser having the conventional structure, the impurity in the p-type semiconductor layer contained in the mesa diffuses into the buried layer in contact with the mesa, and the resistance of the buried layer decreases. Therefore, there is a problem that the current blocking function of the buried layer is reduced and the leak current is increased.

【0012】本発明は,埋込み層に含まれる深いアクセ
プタ準位を形成する不純物をp型半導体層に添加するこ
とにより,埋込み層へのp型不純物の拡散を阻止して埋
込み層の抵抗の低下を防ぐことにより,埋込み層を流れ
るリーク電流が小さく発光効率の良い半導体レーザを提
供することを目的とする。
According to the present invention, by adding an impurity which forms a deep acceptor level contained in a buried layer to a p-type semiconductor layer, diffusion of the p-type impurity into the buried layer is prevented, thereby lowering the resistance of the buried layer. Therefore, it is an object of the present invention to provide a semiconductor laser having a small leakage current flowing through a buried layer and having a high luminous efficiency.

【0013】[0013]

【課題を解決するための手段】図2は本発明の実施例の
製造工程図であり,図2(a)〜(d)は半導体レーザ
の製造工程を示す断面を,図2(d)は完成した半導体
レーザの断面を表している。
FIGS. 2A to 2D are cross-sectional views showing a manufacturing process of a semiconductor laser according to an embodiment of the present invention, and FIGS. 1 shows a cross section of a completed semiconductor laser.

【0014】上記課題を解決するために,本発明は図2
(d)を参照して,第一の構成は,p型半導体層4を有
して半導体基板1上に形成されたメサ7と,深いアクセ
プタ準位を形成する不純物が添加されたIII-V 化合物半
導体からなり,該メサ7の側壁に表出する該p型半導体
層4の端面に接して該メサ7を埋め込む高抵抗の埋込み
層8とを有し,該p型半導体層4は,該埋込み層8に添
加されて深いアクセプタ準位を形成する該不純物元素が
添加されてなることを特徴として構成し,及び,第二の
構成は,第一の構成の半導体レーザにおいて,該半導体
基板1はInPからなり,該p型半導体層4は,p型不
純物としてZn,Cd及びMgのうち少なくとも一つの
元素が添加されたIII-V 化合物半導体からなり,該埋込
み層8はInPおよびGaAsのうちの何れか又はそれ
らの混晶からなり,該埋込み層8に添加され深いアクセ
プタ準位を形成する該不純物元素は,Fe,Co及びC
uのうちの何れかの元素であることを特徴として構成す
る。
In order to solve the above problems, the present invention is based on FIG.
Referring to (d), the first configuration is a mesa 7 formed on a semiconductor substrate 1 having a p-type semiconductor layer 4 and a III-V doped with an impurity for forming a deep acceptor level. A high-resistance buried layer 8 which is made of a compound semiconductor and embeds the mesa 7 in contact with an end face of the p-type semiconductor layer 4 exposed on the side wall of the mesa 7; The buried layer 8 is characterized by being doped with the impurity element forming a deep acceptor level. The second configuration is a semiconductor laser of the first configuration. Is made of InP, the p-type semiconductor layer 4 is made of a III-V compound semiconductor to which at least one of Zn, Cd and Mg is added as a p-type impurity, and the buried layer 8 is made of InP and GaAs. Or a mixed crystal thereof, The impurity element which forms an added deep acceptor level INCLUDED layer 8, Fe, Co, and C
It is characterized by being any element of u.

【0015】[0015]

【作用】図1は本発明の原理説明図であり,p型半導体
層とその上に堆積された埋込み層の深さ方向の不純物濃
度分布を表している。なお,図1の不純物濃度分布は,
以下に述べる試料についてSIMS(二次イオン質量ス
ペクトル)法により測定した結果であり,本発明の発明
者が明らかにしたものである。また,図中Zn,Feの
濃度について,それぞれZn,Feの記号を付して明瞭
にしている。
FIG. 1 is an explanatory view of the principle of the present invention, and shows the impurity concentration distribution in the depth direction of a p-type semiconductor layer and a buried layer deposited thereon. The impurity concentration distribution in FIG.
It is the result of having measured the sample described below by SIMS (secondary ion mass spectrum) method, and it was made clear by the inventor of the present invention. In the drawing, the Zn and Fe concentrations are clearly indicated by the symbols of Zn and Fe, respectively.

【0016】試料は,MOCVD(有機金属化学的気相
堆積)法によりInP基板上にZnをp型不純物として
含むInPからなる厚さ2μmのp型半導体層を堆積
し,続けてMOCVD法によりFeを深いアクセプタ準
位を形成する不純物として含むInPからなる厚さ1μ
mの埋込み層を堆積して作成した。
As a sample, a 2 μm-thick p-type semiconductor layer made of InP containing Zn as a p-type impurity is deposited on an InP substrate by MOCVD (metal organic chemical vapor deposition), and subsequently, Fe is deposited by MOCVD. Of 1 μm thick made of InP containing impurities as impurities for forming a deep acceptor level
m buried layers were deposited.

【0017】図1(a)は,p型半導体層に埋込み層と
同じ濃度のFeを添加した場合である。p型半導体層と
埋込み層との界面で,Znの拡散は生じていない。これ
に対して図1(b)は,p型半導体層にFeが添加され
ていない場合である。p型半導体層と接する埋込み層中
にp型半導体層中のZn不純物が拡散している。
FIG. 1A shows the case where Fe is added to the p-type semiconductor layer at the same concentration as that of the buried layer. No diffusion of Zn occurs at the interface between the p-type semiconductor layer and the buried layer. On the other hand, FIG. 1B shows a case where Fe is not added to the p-type semiconductor layer. Zn impurities in the p-type semiconductor layer are diffused in the buried layer in contact with the p-type semiconductor layer.

【0018】従来の半導体レーザは,このp型半導体層
にFeが添加されていない場合と同様に,Feが添加さ
れていない埋込み層がp型半導体層に接して堆積される
構造であるため,埋込み層にp型不純物が拡散し,埋込
み層の抵抗が低下する。
The conventional semiconductor laser has a structure in which a buried layer to which Fe is not added is deposited in contact with the p-type semiconductor layer, as in the case where Fe is not added to the p-type semiconductor layer. The p-type impurity diffuses into the buried layer, and the resistance of the buried layer decreases.

【0019】本発明は,かかる事実に基づき考案され
た。即ち,本発明は,図2(d)を参照して,深いアク
セプタ準位を形成する不純物を,埋込み層8に添加して
高抵抗とする一方,予めp型半導体層4にも同じ深いア
クセプタ準位を形成する不純物を添加するもので,これ
によりp型半導体層4中のp型不純物が埋込み層8に拡
散することを防止するのである。
The present invention has been devised based on this fact. That is, according to the present invention, referring to FIG. 2 (d), an impurity which forms a deep acceptor level is added to the buried layer 8 to increase the resistance, while the same deep acceptor is previously formed in the p-type semiconductor layer 4. The impurity which forms a level is added, thereby preventing the p-type impurity in the p-type semiconductor layer 4 from diffusing into the buried layer 8.

【0020】なお,p型半導体層4に深いアクセプタ準
位を形成する不純物を添加しても,同じ導電型の不純物
であるから補償されることはなく,p型半導体の導電型
が変換するという不都合は生じない。
It should be noted that even if an impurity which forms a deep acceptor level is added to the p-type semiconductor layer 4, it is not compensated because the impurity is of the same conductivity type, and the conductivity type of the p-type semiconductor is changed. No inconvenience occurs.

【0021】従って,本発明によれば,埋込み層8の抵
抗の低下は起こらず,常に高抵抗の埋込み層8が保持さ
れるから,メサ7を迂回して埋込み層8を流れるリーク
電流は少ない。従って,高い発光効率を有する半導体レ
ーザが実現される。
Therefore, according to the present invention, since the resistance of the buried layer 8 does not decrease and the buried layer 8 having a high resistance is always maintained, the leakage current flowing through the buried layer 8 bypassing the mesa 7 is small. . Therefore, a semiconductor laser having high luminous efficiency is realized.

【0022】上述したp型半導体層にFeを添加したと
き,埋込み層へのp型不純物の拡散が阻止されるのは,
本発明の発明者により以下の機構によると考えられてい
る。図1(b)を参照して,埋込み層中のFeはp型拡
散層に均一濃度で拡散している。他方,p型拡散層中の
p型不純物であるZnは,Feの拡散と交換して埋込み
層中に拡散している。
When Fe is added to the above-described p-type semiconductor layer, the diffusion of the p-type impurity into the buried layer is prevented.
The following mechanism is considered by the inventor of the present invention. Referring to FIG. 1B, Fe in the buried layer is diffused into the p-type diffusion layer at a uniform concentration. On the other hand, Zn as a p-type impurity in the p-type diffusion layer is diffused into the buried layer in exchange for the diffusion of Fe.

【0023】この事実は,深いアクセプタ準位を形成す
る不純物であるFeがp型半導体中に容易に拡散するこ
とにより,このFeの拡散との相互拡散によりZnが埋
込み層に拡散することを示唆している。
This fact suggests that Fe, which is an impurity forming a deep acceptor level, easily diffuses into the p-type semiconductor, and that Zn diffuses into the buried layer by mutual diffusion with the diffusion of Fe. are doing.

【0024】本発明では,p型半導体層に予めFeが添
加されているため,埋込み層とのFe濃度の差が小さ
く,埋込み層からp型半導体層へのFeの拡散が抑制さ
れる。このため,Feとの相互拡散により拡散するZn
もまた拡散が抑制されるのである。
In the present invention, since Fe is previously added to the p-type semiconductor layer, the difference in Fe concentration from the buried layer is small, and the diffusion of Fe from the buried layer to the p-type semiconductor layer is suppressed. Therefore, Zn diffused by interdiffusion with Fe
Again, diffusion is suppressed.

【0025】上述のFeを含むInP中での拡散は,他
のp型不純物, 例えばCd,BeについてJ.Crystal Gr
owth vol. 11(1992)p75 に同様に生ずることが記載され
ており, MgについてPaper presented of 6th Semi-in
sulating III-V Materials,Toront,Canada,(1990)p137
に記載されている。
The above-mentioned diffusion in InP containing Fe is caused by other p-type impurities, such as Cd and Be, by J. Crystal Gr.
owth vol. 11 (1992) p75 describes that the same occurs. For Mg, Paper presented of 6th Semi-in
sulating III-V Materials, Toront, Canada, (1990) p137
It is described in.

【0026】従って,Znについて上述した拡散機構
は,Cd,Be及びMgについても同様であり,本発明
を適用することができる。さらに,上述の拡散はFeの
他,化合物半導体において深いアクセプタとなる不純
物,なかでもIII-V 化合物半導体例えばGaAs若しく
はInPaAs又はこれらの混晶において III族を置換
するII族の不純物,例えばCo,Cuについても同様に
生ずる。
Therefore, the diffusion mechanism described above for Zn is the same for Cd, Be and Mg, and the present invention can be applied. Further, the above-mentioned diffusion may be caused by impurities which become deep acceptors in compound semiconductors, in particular, III-V compound semiconductors such as GaAs or InPaAs or group II impurities which replace group III in mixed crystals thereof, such as Co and Cu, in addition to Fe. Occurs similarly.

【0027】従って,本発明は,これら上記のIII-V 化
合物半導体を埋込み層又はp型半導体層とし,深いアク
セプタとなる上記 III族を置換するII族の不純物を添加
する場合にも適用されるのである。
Therefore, the present invention is also applicable to a case where the above-mentioned III-V compound semiconductor is used as a buried layer or a p-type semiconductor layer and a group II impurity which replaces the above-mentioned group III, which becomes a deep acceptor, is added. It is.

【0028】[0028]

【実施例】本発明を実施例の製造工程を参照して説明す
る。本発明に係るメサストライプ埋込み型半導体レーザ
を製造するには,図2(a)を参照して,先ず,例えば
n型InPからなる半導体基板1上にMOCVD(有機
金属化学的気相堆積)法により,ガイド層2としてSn
を1×1017cm-3添加した厚さ0.2μmのn型InG
aAsPを,活性層3として厚さ0.1μmのn型In
GaAsPを,クラッド層となるべきp型半導体層4と
してZnを5×1017cm-3及びFeを6×1016cm-3
加した厚さ1.5μmのInPを,コンタクト層5とし
てZnを1×1019cm-3添加した厚さ0.2μmのIn
GaAsを,順次堆積する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the manufacturing steps of the embodiments. To manufacture a mesa stripe embedded semiconductor laser according to the present invention, referring to FIG. 2A, first, an MOCVD (organic metal chemical vapor deposition) method is performed on a semiconductor substrate 1 made of, for example, n-type InP. As a result, Sn
Is added to 1 × 10 17 cm −3 and a 0.2 μm-thick n-type InG
aAsP is used as an active layer 3 with an n-type In layer having a thickness of 0.1 μm.
GaAsP is used as a p-type semiconductor layer 4 to be a cladding layer, 1.5 μm thick InP to which Zn is added at 5 × 10 17 cm −3 and Fe is added at 6 × 10 16 cm −3 , and Zn is used as a contact layer 5. 0.2 μm thick In added with 1 × 10 19 cm −3
GaAs is sequentially deposited.

【0029】次いで,図2(b)を参照して,コンタク
ト層5の上に幅2μmのストライプ状のSiO2 マスク
6を形成し,マスク6を用いた硫酸系の及び塩酸系のエ
ッチャントによる上記堆積層の選択的エッチングによ
り,高さ2μm,幅1.5μmのメサ7を形成する。
Then, referring to FIG. 2B, a stripe-shaped SiO 2 mask 6 having a width of 2 μm is formed on the contact layer 5, and the above-mentioned process is performed using a sulfuric acid-based and hydrochloric acid-based etchant using the mask 6. A mesa 7 having a height of 2 μm and a width of 1.5 μm is formed by selective etching of the deposited layer.

【0030】次いで,図2(c)を参照して,メサ7の
側壁を埋め込むInPをMOCVD法により堆積し埋込
み層8とする。このとき,マスク6は埋込み層の選択的
堆積のためにも用いられる。堆積温度は例えば600℃
とすることができる。また,埋込み層8には例えば濃度
6×1016cm-3のFeを添加し,キャリアが補償された
高抵抗半導体とする。
Next, referring to FIG. 2C, InP for burying the sidewall of the mesa 7 is deposited by MOCVD to form a buried layer 8. At this time, the mask 6 is also used for selective deposition of the buried layer. The deposition temperature is, for example, 600 ° C.
It can be. The buried layer 8 is doped with, for example, Fe having a concentration of 6 × 10 16 cm −3 to provide a carrier-compensated high-resistance semiconductor.

【0031】次いで,図2(d)を参照して,マスク6
を除去したのち,例えば金属を蒸着して,メサ7の上面
に接し埋込み層8表面に延在する電極9及び基板の裏面
に密着する電極10を形成する。さらにメサ7と垂直面
で劈開し共振器長が300μmのチップとして半導体レ
ーザを完成する。
Next, referring to FIG.
After the removal, a metal is deposited, for example, to form an electrode 9 in contact with the upper surface of the mesa 7 and extending on the surface of the buried layer 8 and an electrode 10 in close contact with the back surface of the substrate. Further, the semiconductor laser is completed as a chip having a cavity length of 300 μm by cleavage along a plane perpendicular to the mesa 7.

【0032】本実施例に係る半導体レーザでは,最高出
力が30mWであった。これは同じ形状の従来の半導体レ
ーザの最高出力25mWと比較して20%増加している。
The maximum output of the semiconductor laser according to the present embodiment was 30 mW. This is 20% higher than the maximum output of 25 mW of the conventional semiconductor laser of the same shape.

【0033】[0033]

【発明の効果】本発明によれば,メサに含まれるp型半
導体層に埋込み層に添加される補償用不純物と同じ不純
物を添加することにより,埋込み層屁のp型不純物の拡
散を抑制することができるから埋込み層の抵抗の低下が
防止され,活性層を含むメサを迂回して埋込み層を流れ
るリーク電流が小さく,発光効率の高い半導体レーザを
提供することができるから,電子機器の性能向上に寄与
するところが大きい。
According to the present invention, the diffusion of the p-type impurity in the buried layer is suppressed by adding the same impurity as the compensation impurity added to the buried layer to the p-type semiconductor layer included in the mesa. This can prevent a decrease in the resistance of the buried layer, and can provide a semiconductor laser with a high luminous efficiency, with a small leakage current flowing through the buried layer bypassing the mesa including the active layer, thereby improving the performance of electronic devices. It greatly contributes to improvement.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.

【図2】 本発明の実施例の工程図FIG. 2 is a process diagram of an embodiment of the present invention.

【図3】 従来の半導体レーザ断面図FIG. 3 is a sectional view of a conventional semiconductor laser.

【符号の説明】[Explanation of symbols]

1 基板 2 ガイド層 3 活性層 4 p型半導体 5 コンタクト層 6 マスク 7 メサ 8 埋込み層 9,10 電極 Reference Signs List 1 substrate 2 guide layer 3 active layer 4 p-type semiconductor 5 contact layer 6 mask 7 mesa 8 buried layer 9, 10 electrode

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 p型半導体層を有して半導体基板上に形
成されたメサと,深いアクセプタ準位を形成する不純物
が添加されたIII-V 化合物半導体からなり,該メサの
壁に表出する該p型半導体層の端面に接して該メサを
め込む高抵抗の埋込み層とを有し, 該p型半導体層は、該埋込み層に添加されて深いアクセ
プタ準位を形成する該不純物が添加されていることを特
徴とする半導体レーザ。
1. A a p-type and main support formed on a semiconductor board on a semiconductor layer, a deep acceptor level III-V compound impurities which form is added semiconductor, side該Me Sa writing <br/> Me embedding the該Me support in contact with the end face of the p-type semiconductor layer exposed in <br/> walls and a high resistance of the buried layer, the p-type semiconductor layer,該埋inclusive layer a semiconductor laser, characterized in that the impure product to form a deep acceptor level is added is added to.
【請求項2】 請求項1記載の半導体レーザにおいて, 該半導体基板はInPからなり, 該p型半導体層は,p型不純物としてZn,Cd及びM
gのうち少なくとも一つの元素が添加されたIII-V 化合
物半導体からなり, 該埋込み層はInPおよびGaAsのうちのいずれか又
はそれらの混晶からなり, 該埋込み層に添加され深いアクセプタ準位を形成する該
不純物は,Fe,Co及びCuのうちの何れかの元素で
あることを特徴とする半導体レーザ。
2. A semiconductor laser according to claim 1, wherein said semiconductor base plate is made of InP, the p-type semiconductor layer, Zn as p-type impurity, Cd and M
g of a III-V compound semiconductor to which at least one element is added. The buried layer is made of any one of InP and GaAs or a mixed crystal thereof, and has a deep acceptor level added to the buried layer. the <br/> impure product to be formed, a semiconductor laser which is a one element selected from Fe, Co and Cu.
JP18977492A 1992-07-17 1992-07-17 Semiconductor laser Expired - Fee Related JP3257045B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18977492A JP3257045B2 (en) 1992-07-17 1992-07-17 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18977492A JP3257045B2 (en) 1992-07-17 1992-07-17 Semiconductor laser

Publications (2)

Publication Number Publication Date
JPH0637392A JPH0637392A (en) 1994-02-10
JP3257045B2 true JP3257045B2 (en) 2002-02-18

Family

ID=16246975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18977492A Expired - Fee Related JP3257045B2 (en) 1992-07-17 1992-07-17 Semiconductor laser

Country Status (1)

Country Link
JP (1) JP3257045B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086199A (en) 2004-09-14 2006-03-30 Mitsubishi Electric Corp Semiconductor optical device and manufacturing method therefor
JP2008244264A (en) * 2007-03-28 2008-10-09 Fujitsu Ltd Semiconductor optical device and method for manufacturing the same

Also Published As

Publication number Publication date
JPH0637392A (en) 1994-02-10

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