JP3255162B2 - Semiconductor manufacturing apparatus and semiconductor manufacturing method - Google Patents

Semiconductor manufacturing apparatus and semiconductor manufacturing method

Info

Publication number
JP3255162B2
JP3255162B2 JP35187799A JP35187799A JP3255162B2 JP 3255162 B2 JP3255162 B2 JP 3255162B2 JP 35187799 A JP35187799 A JP 35187799A JP 35187799 A JP35187799 A JP 35187799A JP 3255162 B2 JP3255162 B2 JP 3255162B2
Authority
JP
Japan
Prior art keywords
tape
pressing
semiconductor chip
sample
semiconductor manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP35187799A
Other languages
Japanese (ja)
Other versions
JP2001160569A (en
Inventor
武彦 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP35187799A priority Critical patent/JP3255162B2/en
Publication of JP2001160569A publication Critical patent/JP2001160569A/en
Application granted granted Critical
Publication of JP3255162B2 publication Critical patent/JP3255162B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体製造装置及
び半導体製造方法に関し、特に、半導体チップと配線パ
ターンが形成されたテープとの張り付けに用いて好適な
半導体製造装置及び半導体製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus and a semiconductor manufacturing method, and more particularly to a semiconductor manufacturing apparatus and a semiconductor manufacturing method suitable for attaching a semiconductor chip and a tape on which a wiring pattern is formed.

【0002】[0002]

【従来の技術】従来、LSI、IC等の半導体チップ
と、その内部端子と外部端子とを結ぶ配線パターンが設
けられたテープとを張り合わせるには、表面が平坦で厚
みが均一な緩衝材を用いて行っていた。ここで、従来の
半導体チップの張り付け装置について、図4を参照して
説明する。図4は、従来の半導体チップの張り付け装置
を模式的に示す図であり、(a)は断面図を、(b)は
緩衝材に加わる圧力を示す図である。
2. Description of the Related Art Conventionally, in order to bond a semiconductor chip such as an LSI or an IC with a tape provided with a wiring pattern connecting an internal terminal and an external terminal, a buffer material having a flat surface and a uniform thickness is used. I was using it. Here, a conventional semiconductor chip attaching apparatus will be described with reference to FIG. 4A and 4B are diagrams schematically showing a conventional semiconductor chip attaching device, wherein FIG. 4A is a cross-sectional view, and FIG. 4B is a diagram showing a pressure applied to a cushioning material.

【0003】図4(a)に示すように、半導体チップ3
に配線パターンが設けられた樹脂テープを貼り付けるに
は、ステージ5上に表面が平坦で厚さが均一な緩衝材1
cを設置し、その上に樹脂テープ2を仮止めした半導体
チップ3を、樹脂テープ2側が下になるようにして置
き、半導体チップ3の上から加圧手段4を用いて加圧す
ることによって行っていた。
[0003] As shown in FIG.
In order to attach a resin tape provided with a wiring pattern to the surface, a buffer material 1 having a flat surface and a uniform thickness is placed on the stage 5.
c, and the semiconductor chip 3 with the resin tape 2 temporarily fixed thereon is placed with the resin tape 2 side facing down, and the semiconductor chip 3 is pressed from above the semiconductor chip 3 using the pressing means 4. I was

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の構成では、加圧時に緩衝材1cが変形し、半
導体チップ3下部の緩衝材1cが押し下げられることに
よって半導体チップ3周辺の緩衝材1cがせり上がり、
その結果、半導体チップ3に加わる圧力が不均一になっ
てしまうという問題があった。
However, in such a conventional structure, the cushioning material 1c is deformed at the time of pressurization and the cushioning material 1c under the semiconductor chip 3 is pushed down, so that the cushioning material 1c around the semiconductor chip 3 is pressed. Soaring,
As a result, there is a problem that the pressure applied to the semiconductor chip 3 becomes uneven.

【0005】特に、緩衝材1cの材質、形状、押圧の強
さによっては、半導体チップ3外周部と緩衝材1cとの
間に隙間8が発生して圧力が低下し、張り合わせが不十
分になってしまうという問題があった。また、このよう
な場合には、圧力が低下した半導体チップ3外周部と樹
脂テープ2との間に気泡9が発生し、実装時の加熱で気
泡9がふくらみ、半導体チップ3と樹脂テープ2とが接
続不良を起こしてしまうという問題があった。
[0005] In particular, depending on the material, shape, and pressing strength of the cushioning material 1c, a gap 8 is generated between the outer peripheral portion of the semiconductor chip 3 and the cushioning material 1c, so that the pressure decreases and the lamination becomes insufficient. There was a problem that would. In such a case, bubbles 9 are generated between the outer peripheral portion of the semiconductor chip 3 in which the pressure is reduced and the resin tape 2, and the bubbles 9 are expanded by heating during mounting, and the semiconductor chip 3 and the resin tape 2 are separated from each other. However, there is a problem that a connection failure occurs.

【0006】ここで、緩衝材1cに加わる圧力の分布を
示す図4(b)を参照すると、半導体チップ3の両端に
相当する部分の圧力が、隙間8の発生によって一旦低下
していることがわかる。なお、図の横軸は横方向の位置
を示し、縦軸は樹脂テープ2に加わる圧力の大きさを示
している。
Here, referring to FIG. 4B showing the distribution of the pressure applied to the cushioning material 1 c, it can be seen that the pressure at the portions corresponding to both ends of the semiconductor chip 3 has once decreased due to the formation of the gap 8. Understand. The horizontal axis in the figure indicates the position in the horizontal direction, and the vertical axis indicates the magnitude of the pressure applied to the resin tape 2.

【0007】本発明は、上記問題点に鑑みてなされたも
のであって、その主たる目的は、LSI、IC等の半導
体チップに、その内部端子と外部端子を結ぶ配線パター
ンが形成された樹脂テープを均一に張り合わせることが
できる半導体製造装置及び半導体製造方法を提供するこ
とにある。
The present invention has been made in view of the above problems, and a main object of the present invention is to provide a resin tape in which a wiring pattern connecting internal terminals and external terminals is formed on a semiconductor chip such as an LSI or IC. It is an object of the present invention to provide a semiconductor manufacturing apparatus and a semiconductor manufacturing method capable of uniformly bonding semiconductor devices.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、第1の視点において、固定台の上に載置
された試料を該試料の上方に設けた加圧手段によって加
圧する加圧装置において、前記固定台と前記試料との
間、又は、前記加圧手段と前記試料との間の少なくとも
一方に、前記試料と接する面側に所定の深さの溝が格子
状に形成された緩衝材を備え、前記緩衝材の格子状の溝
で区分けされた各々の領域が、加圧によって前記溝を埋
めるように押し潰されることによって、前記試料を均一
に押圧するものである。
In order to achieve the above object, according to the present invention, in a first aspect, a sample placed on a fixed base is pressurized by a pressing means provided above the sample. In the pressing device that presses, a groove having a predetermined depth is formed in a lattice shape on the surface side in contact with the sample, at least between the fixing table and the sample, or at least one between the pressing unit and the sample. With the formed cushioning material, each region divided by the lattice-like grooves of the cushioning material is crushed so as to fill the grooves by applying pressure, thereby uniformly pressing the sample. .

【0009】また本発明は、第2の視点において、固定
台の上に載置された試料を該試料の上方に設けた加圧手
段によって加圧する加圧装置において、前記固定台と前
記試料との間、又は、前記加圧手段と前記試料との間の
少なくとも一方に、前記試料と接する面側に所定の高さ
の突部が2次元配列された緩衝材を備え、前記緩衝材の
2次元配列された前記突部が、加圧によって押し潰され
て平坦化することによって、前記試料を均一に押圧する
ものである。
According to a second aspect of the present invention, there is provided a pressurizing apparatus for pressurizing a sample placed on a fixed base by a pressurizing means provided above the sample in a second viewpoint. Or at least one between the pressurizing means and the sample, a cushioning material having projections of a predetermined height two-dimensionally arranged on a surface side in contact with the sample, The projections arranged one-dimensionally are crushed by pressure and flattened, thereby uniformly pressing the sample.

【0010】また本発明は、第3の視点において、ステ
ージ上に載置された、配線パターンが形成されたテープ
と半導体チップとを、その上方に設けた加圧手段によっ
て加圧することにより張り合わせる半導体製造装置にお
いて、前記ステージと前記テープとの間に、前記テープ
と接する面側に所定の深さの溝が格子状に形成された緩
衝材を備え、該緩衝材が、前記加圧手段の押圧によっ
て、前記溝を埋めるように弾性変形するものである。
According to a third aspect of the present invention, in a third aspect, the tape on which the wiring pattern is formed and the semiconductor chip mounted on the stage are attached to each other by pressing the semiconductor chip with a pressing means provided above the tape. In the semiconductor manufacturing apparatus, between the stage and the tape, there is provided a cushioning material in which a groove of a predetermined depth is formed in a lattice shape on a surface side in contact with the tape, and the cushioning material is By pressing, the groove is elastically deformed so as to fill the groove.

【0011】本発明は、第4の視点において、ステージ
上に載置された、配線パターンが形成されたテープと半
導体チップとを、その上方に設けた加圧手段によって加
圧することにより張り合わせる半導体製造装置におい
て、前記ステージと前記テープとの間に、前記テープと
接する面側に所定の高さの突部が2次元配列された緩衝
材を備え、該緩衝材が、前記加圧手段の押圧によって、
前記突部を押し広げるように弾性変形するものである。
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising a semiconductor chip and a tape mounted on a stage, on which a wiring pattern is formed, and the semiconductor chip being pressed by a pressing means provided above the semiconductor chip. In the manufacturing apparatus, between the stage and the tape, there is provided a cushioning material in which projections of a predetermined height are two-dimensionally arranged on a surface side in contact with the tape, and the cushioning material is pressed by the pressing means. By
The protrusion is elastically deformed so as to push it apart.

【0012】[0012]

【発明の実施の形態】本発明に係る半導体製造装置は、
その好ましい一実施の形態において、ステージ(図2の
5)上に所定の深さの溝(図2の6)が格子状に形成さ
れた緩衝材(図2の1a)を設置し、その上に配線パタ
ーンが形成された樹脂テープ(図2の2)と半導体チッ
プ(図2の3)とを置き、上方から加圧手段(図2の
4)によって加圧するに際し、半導体チップ下部の緩衝
材のみが溝を埋めるように押し潰されることによって、
樹脂テープを均一に押圧するものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor manufacturing apparatus according to the present invention
In a preferred embodiment, a cushioning material (1a in FIG. 2) in which grooves (6 in FIG. 2) having a predetermined depth are formed in a grid on a stage (5 in FIG. 2) is placed. A resin tape (2 in FIG. 2) on which a wiring pattern is formed and a semiconductor chip (3 in FIG. 2) are placed, and when pressure is applied from above by a pressing means (4 in FIG. 2), a buffer material under the semiconductor chip is used. Only by being crushed to fill the groove,
This is to press the resin tape uniformly.

【0013】本構成の緩衝材1aを用いた場合、図2に
示すように、半導体チップ3下部の緩衝材1aだけが変
形するとともに、半導体チップ3の下では変形により溝
6の隙間が埋められることにより半導体チップ3の下面
を均等に押すことができる。従って、従来のように半導
体チップ3の周辺部の圧力が低下し、半導体チップ3と
樹脂テープ2との間に気泡8が発生するという問題が生
じることなく、半導体チップ3に樹脂テープ2を均一に
張り付けることができる。
When the cushioning member 1a of this configuration is used, as shown in FIG. 2, only the cushioning member 1a below the semiconductor chip 3 is deformed, and under the semiconductor chip 3, the gap of the groove 6 is filled by the deformation. Thus, the lower surface of the semiconductor chip 3 can be pressed evenly. Therefore, the resin tape 2 can be uniformly applied to the semiconductor chip 3 without the problem that the pressure around the semiconductor chip 3 decreases as in the related art and the bubbles 8 are generated between the semiconductor chip 3 and the resin tape 2. Can be attached to

【0014】[0014]

【実施例】上記した本発明の実施の形態についてさらに
詳細に説明すべく、本発明の実施例について図面を参照
して以下に説明する。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

【0015】[実施例1]本発明の第1の実施例に係る
半導体製造装置ついて、図1及び図2を参照して説明す
る。図1は、本発明の第1の実施例に係る半導体製造装
置の構成を示す斜視図である。また、図2は、半導体チ
ップと樹脂テープとを張り合わせる様子を示す図であ
り、(a)は加圧前の状態を示す断面図、(b)は加圧
後の状態を示す断面図、(c)は樹脂テープに加わる圧
力を示す図である。
[Embodiment 1] A semiconductor manufacturing apparatus according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view showing a configuration of a semiconductor manufacturing apparatus according to a first embodiment of the present invention. 2A and 2B are views showing a state in which a semiconductor chip and a resin tape are bonded to each other. FIG. 2A is a cross-sectional view showing a state before pressing, FIG. 2B is a cross-sectional view showing a state after pressing, (C) is a diagram showing the pressure applied to the resin tape.

【0016】まず、図1を参照して本発明の第1の実施
例に係る半導体製造装置の構成について説明すると、本
実施例の半導体製造装置は、ステージ5と緩衝材1aと
加圧機構4とを有し、ステージ5上に置かれた緩衝材1
aには、格子状の溝6が設けられている。また、緩衝材
1aの上には、LSI、IC等の半導体チップ3とその
内部端子と外部端子を結ぶための配線パターンが設けら
れ、半導体チップ3と貼り合わされる面に接着剤が塗布
されている樹脂テープ2が設置される。
First, the configuration of a semiconductor manufacturing apparatus according to a first embodiment of the present invention will be described with reference to FIG. 1. The semiconductor manufacturing apparatus according to the present embodiment includes a stage 5, a buffer 1a, and a pressing mechanism 4 And the cushioning material 1 placed on the stage 5
A is provided with a lattice-shaped groove 6. Further, a semiconductor chip 3 such as an LSI or an IC and a wiring pattern for connecting the internal terminal and the external terminal are provided on the buffer material 1a, and an adhesive is applied to a surface to be bonded to the semiconductor chip 3. Is installed.

【0017】次に、本実施例の動作について、図2を参
照して説明する。図2(a)に示すように、ステージ5
上に溝6が上面を向くように緩衝材1aを配置し、その
上に樹脂テープ2と半導体チップ3とをこの順に位置あ
わせして配置する。その後、図2(b)に示すように、
半導体チップ3上部に設けた加圧手段4により、半導体
チップ3上面から圧力を加える。
Next, the operation of this embodiment will be described with reference to FIG. As shown in FIG.
The cushioning material 1a is arranged so that the groove 6 faces the upper surface, and the resin tape 2 and the semiconductor chip 3 are arranged thereon in this order. Then, as shown in FIG.
Pressure is applied from the upper surface of the semiconductor chip 3 by the pressurizing means 4 provided above the semiconductor chip 3.

【0018】半導体チップ3と樹脂テープ2が密着し、
半導体チップ3の下部の領域の緩衝材1aだけが押し下
げられると、その部分の緩衝材1aは変形して横に広が
り、溝6の隙間を埋める。このように溝6の隙間が埋め
られることにより、緩衝材1aは樹脂テープ2の下面全
体を均等に押すことができ、樹脂テープ2を半導体チッ
プ3に均一に張り付けることができる。
The semiconductor chip 3 and the resin tape 2 come into close contact with each other,
When only the cushioning material 1a in the lower area of the semiconductor chip 3 is pushed down, the cushioning material 1a in that portion is deformed and spreads laterally, filling the gap of the groove 6. By filling the gaps of the grooves 6 in this manner, the cushioning material 1 a can uniformly push the entire lower surface of the resin tape 2, and the resin tape 2 can be stuck to the semiconductor chip 3 uniformly.

【0019】この時の圧力分布を図2(c)を参照して
説明する。図の横軸は横方向の位置を示し、縦軸は樹脂
テープ2に加わる圧力の大きさを示している。図2
(c)に示すように、半導体チップ3下部の緩衝材1a
は押し潰されて横方向に広がり、均一に半導体チップ3
に接触することになるために、半導体チップ3の端部に
おいて圧力が低下するという問題を回避することができ
る。
The pressure distribution at this time will be described with reference to FIG. The horizontal axis in the figure indicates the position in the horizontal direction, and the vertical axis indicates the magnitude of the pressure applied to the resin tape 2. FIG.
As shown in (c), the buffer 1a under the semiconductor chip 3
Are crushed and spread in the lateral direction, and the semiconductor chip 3 is uniformly
, The pressure drop at the end of the semiconductor chip 3 can be avoided.

【0020】ここで、緩衝材1aとしては、可逆的に弾
性変形するものであればよく、その材質、溝6の幅、深
さ等は、張り合わせるチップの大きさ、印加圧力等の条
件に応じて適宜定めることができる。また、溝6の間隔
を最適化することにより、半導体チップ3の形状によら
ず、均一の圧力で樹脂テープ2の張り合わせを行うこと
が可能になる。
Here, the buffer material 1a may be any material as long as it can be elastically deformed reversibly, and its material, the width and depth of the groove 6, etc. are determined according to conditions such as the size of the chip to be bonded and the applied pressure. It can be determined as appropriate. By optimizing the interval between the grooves 6, the resin tapes 2 can be bonded with a uniform pressure regardless of the shape of the semiconductor chip 3.

【0021】なお、発明者が行った実験によれば、緩衝
材1aの材料として、厚さ約1mmのシリコンゴムを用
いた場合に、温度が260℃、圧力が40kgf/cm2の条
件で熱圧着して、半導体チップ3と樹脂テープ2とを均
一に貼り合わせることができた。
According to an experiment conducted by the inventor, when silicone rubber having a thickness of about 1 mm was used as the material of the buffer material 1a, thermocompression bonding was performed at a temperature of 260 ° C. and a pressure of 40 kgf / cm 2. As a result, the semiconductor chip 3 and the resin tape 2 were uniformly bonded.

【0022】[実施例2]次に、本発明の第2の実施例
に係る半導体製造装置ついて、図3を参照して説明す
る。図3は、半導体チップと樹脂テープとを張り合わせ
る様子を示す図であり、(a)は加圧前の状態を示す断
面図、(b)は加圧後の状態を示す断面図、(c)は樹
脂テープに加わる圧力を示す図である。第2の実施例
と、前記した第1の実施例とは、緩衝材の表面構造が異
なるのみであり、その他の材質、製造方法等について
は、前記した第1の実施例と同様である。
Embodiment 2 Next, a semiconductor manufacturing apparatus according to a second embodiment of the present invention will be described with reference to FIG. 3A and 3B are views showing a state in which a semiconductor chip and a resin tape are bonded to each other. FIG. 3A is a cross-sectional view showing a state before pressing, FIG. 3B is a cross-sectional view showing a state after pressing, and FIG. () Is a diagram showing the pressure applied to the resin tape. The second embodiment is different from the first embodiment only in the surface structure of the cushioning material, and the other materials, manufacturing method, and the like are the same as those in the first embodiment.

【0023】本発明の第2の実施例に係る半導体製造装
置の構成は、ステージ5と緩衝材1bと加圧機構4とを
有し、ステージ5上に置かれた緩衝材1bには、2次元
配列された突部7が設けられている。また、緩衝材1b
の上には、LSI、IC等の半導体チップ3とその内部
端子と外部端子を結ぶための配線パターンが設けられ、
半導体チップ3と貼り合わされる面に接着剤が塗布され
ている樹脂テープ2が設置される。
The configuration of the semiconductor manufacturing apparatus according to the second embodiment of the present invention has a stage 5, a buffer 1b, and a pressure mechanism 4, and the buffer 1b placed on the stage 5 has Protrusions 7 arranged in a dimension are provided. Also, cushioning material 1b
A wiring pattern for connecting a semiconductor chip 3 such as an LSI or an IC and its internal terminals and external terminals is provided on the
A resin tape 2 having an adhesive applied to a surface to be bonded to the semiconductor chip 3 is provided.

【0024】次に、本実施例の動作について、図3を参
照して説明する。図3(a)に示すように、ステージ5
上に突部7が上面を向くように緩衝材1bを配置し、そ
の上に樹脂テープ2と半導体チップ3とをこの順に位置
あわせして配置する。その後、図3(b)に示すよう
に、半導体チップ3上部に設けた加圧手段4により、半
導体チップ3上面から圧力を加える。
Next, the operation of this embodiment will be described with reference to FIG. As shown in FIG.
The buffer material 1b is arranged so that the protrusion 7 faces the upper surface, and the resin tape 2 and the semiconductor chip 3 are arranged thereon in this order. Thereafter, as shown in FIG. 3B, pressure is applied from above the semiconductor chip 3 by the pressurizing means 4 provided above the semiconductor chip 3.

【0025】半導体チップ3と樹脂テープ2が密着し、
半導体チップ3の下部領域の緩衝材1bだけが押し下げ
られると、その部分の突部7は弾性変形して横に広が
り、突部7の周囲の凹部を埋めて平坦な形状になる。こ
のように凹部の隙間が埋められることにより、緩衝材1
bは樹脂テープ2の下面全体を均等に押すことができ、
樹脂テープ2を半導体チップ3に均一に張り付けること
ができる。
The semiconductor chip 3 and the resin tape 2 come into close contact with each other,
When only the cushioning material 1b in the lower region of the semiconductor chip 3 is pushed down, the protrusion 7 at that portion is elastically deformed and spreads laterally, filling the recess around the protrusion 7 to have a flat shape. By filling the gaps of the recesses in this manner, the cushioning material 1
b can evenly press the entire lower surface of the resin tape 2,
The resin tape 2 can be uniformly attached to the semiconductor chip 3.

【0026】この時の圧力分布は、図3(c)に示すよ
うに、半導体チップ3下部の緩衝材1bは押し潰されて
横方向に広がり、均一に半導体チップ3に接触すること
になるために、半導体チップ3の端部において圧力が低
下するという問題を回避することができる。
As shown in FIG. 3C, the pressure distribution at this time is such that the buffer material 1b under the semiconductor chip 3 is crushed and spreads in the lateral direction, so that the buffer material 1b comes into uniform contact with the semiconductor chip 3. In addition, it is possible to avoid the problem that the pressure drops at the end of the semiconductor chip 3.

【0027】ここで、緩衝材1bとしては、可逆的に弾
性変形するものであればよく、その材質、突部7等の形
状等は、張り合わせるチップの大きさ、印加圧力等の条
件に応じて適宜定めることができることは、前記した第
1の実施例と同様である。
Here, the cushioning material 1b may be any material as long as it can be elastically deformed reversibly, and its material, the shape of the protrusion 7, etc., depend on the size of the chip to be bonded, the applied pressure, and other conditions. It is the same as in the first embodiment that can be determined as appropriate.

【0028】[0028]

【発明の効果】以上説明したように、本発明の半導体製
造装置によれば、半導体チップと樹脂テープを均一に張
り合わせることができ、実装後の接続信頼性を向上させ
ることができるという効果を奏する。
As described above, according to the semiconductor manufacturing apparatus of the present invention, the semiconductor chip and the resin tape can be uniformly bonded, and the connection reliability after mounting can be improved. Play.

【0029】その理由は、加圧によって溝で分割された
領域又は突部の緩衝材が各々押し広げられ、半導体チッ
プの全域が均一に緩衝材に接触し押圧されるため、半導
体チップと樹脂テープの間に気泡等が発生することが無
く、実装時の加熱で気泡がふくれることによる接続不良
を防ぐことができるためである。
The reason is that the cushioning material in the area divided by the groove or the projection is pushed out by pressurization, and the entire area of the semiconductor chip is uniformly contacted with the cushioning material and pressed. This is because no bubbles or the like are generated during the mounting, and a connection failure due to the bubbles rising due to heating during mounting can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】発明の一実施例に係る半導体製造装置の構成を
模式的に説明するための斜視図である。
FIG. 1 is a perspective view schematically illustrating a configuration of a semiconductor manufacturing apparatus according to one embodiment of the present invention.

【図2】発明の一実施例に係る半導体製造装置の機能を
説明するための図であり、(a)、(b)は断面図、
(c)は圧力分布図である。
FIGS. 2A and 2B are diagrams for explaining functions of the semiconductor manufacturing apparatus according to one embodiment of the present invention, wherein FIGS.
(C) is a pressure distribution diagram.

【図3】発明の一実施例に係る半導体製造装置の機能を
説明するための図であり、(a)、(b)は断面図、
(c)は圧力分布図である。
FIGS. 3A and 3B are diagrams for explaining functions of the semiconductor manufacturing apparatus according to one embodiment of the present invention, in which FIGS.
(C) is a pressure distribution diagram.

【図4】従来の半導体製造装置の機能を説明するための
図であり、(a)は断面図、(b)は圧力分布図であ
る。
4A and 4B are diagrams for explaining functions of a conventional semiconductor manufacturing apparatus, wherein FIG. 4A is a cross-sectional view and FIG. 4B is a pressure distribution diagram.

【符号の説明】[Explanation of symbols]

1a、1b、1c 緩衝材 2 樹脂テープ 3 チップ 4 加圧機構 5 ステージ 6 溝 7 突起 8 隙間 9 気泡 DESCRIPTION OF SYMBOLS 1a, 1b, 1c Buffer material 2 Resin tape 3 Chip 4 Pressure mechanism 5 Stage 6 Groove 7 Projection 8 Gap 9 Air bubble

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】固定台の上に載置された試料を該試料の上
方に設けた加圧手段によって加圧する加圧装置におい
て、 前記固定台と前記試料との間、又は、前記加圧手段と前
記試料との間の少なくとも一方に、前記試料と接する面
側に所定の深さの溝が格子状に形成された緩衝材を備
え、前記緩衝材の格子状の溝で区分けされた各々の領域
が、加圧によって前記溝を埋めるように押し潰されるこ
とによって、前記試料を均一に押圧することを特徴とす
る加圧装置。
1. A pressurizing device for pressurizing a sample placed on a fixed table by a pressurizing means provided above the sample, wherein the pressurizing means is provided between the fixed table and the sample or the pressurizing means. And at least one between the sample and the sample, provided with a buffer material in which a groove of a predetermined depth is formed in a lattice shape on the surface contacting the sample, each of which is divided by the lattice-like groove of the buffer material A pressing device, wherein the sample is pressed uniformly by crushing an area to fill the groove by pressing.
【請求項2】固定台の上に載置された試料を該試料の上
方に設けた加圧手段によって加圧する加圧装置におい
て、 前記固定台と前記試料との間、又は、前記加圧手段と前
記試料との間の少なくとも一方に、前記試料と接する面
側に所定の高さの突部が2次元配列された緩衝材を備
え、前記緩衝材の2次元配列された前記突部が、加圧に
よって押し潰されて平坦化することによって、前記試料
を均一に押圧することを特徴とする加圧装置。
2. A pressurizing apparatus for pressurizing a sample placed on a fixed base by a pressurizing means provided above the sample, wherein the pressurizing means is provided between the fixed base and the sample or the pressurizing means. At least one between the sample and the sample, provided with a cushioning material in which projections of a predetermined height are two-dimensionally arranged on the surface side in contact with the sample, the projections two-dimensionally arranged of the cushioning material, A pressing device, wherein the sample is pressed uniformly by being crushed and flattened by pressing.
【請求項3】ステージ上に載置された、配線パターンが
形成されたテープと半導体チップとを、その上方に設け
た加圧手段によって加圧することにより張り合わせる半
導体製造装置において、 前記ステージと前記テープとの間に、前記テープと接す
る面側に所定の深さの溝が格子状に形成された緩衝材を
備え、該緩衝材が、前記加圧手段の押圧によって、前記
溝を埋めるように弾性変形することを特徴とする半導体
製造装置。
3. A semiconductor manufacturing apparatus for bonding a tape, on which a wiring pattern is formed, and a semiconductor chip, which are mounted on a stage, to each other by pressing by a pressing means provided above the tape. Between the tape and the tape, a buffer material having a groove of a predetermined depth is formed in a lattice shape on the surface contacting the tape, and the buffer material fills the groove by the pressing of the pressing means. A semiconductor manufacturing apparatus characterized by being elastically deformed.
【請求項4】ステージ上に載置された、配線パターンが
形成されたテープと半導体チップとを、その上方に設け
た加圧手段によって加圧することにより張り合わせる半
導体製造装置において、 前記ステージと前記テープとの間に、前記テープと接す
る面側に所定の高さのの突部が2次元配列された緩衝材
を備え、該緩衝材が、前記加圧手段の押圧によって、前
記突部を押し広げるように弾性変形することを特徴とす
る半導体製造装置。
4. A semiconductor manufacturing apparatus for bonding a tape, on which a wiring pattern is formed, and a semiconductor chip, which are mounted on a stage, to each other by pressurizing the tape by a pressurizing means provided above the stage. Between the tape and the tape, there is provided a cushioning material in which projections of a predetermined height are two-dimensionally arranged on a surface side in contact with the tape, and the cushioning material pushes the projection by the pressing of the pressing means. A semiconductor manufacturing apparatus characterized by being elastically deformed so as to expand.
【請求項5】前記緩衝材の前記溝又は前記突部を形成す
る領域が、前記半導体チップと前記テープとの接触面よ
りも大きい、請求項3又は4に記載の半導体製造装置。
5. The semiconductor manufacturing apparatus according to claim 3, wherein a region of the buffer material where the groove or the protrusion is formed is larger than a contact surface between the semiconductor chip and the tape.
【請求項6】前記緩衝材が、シリコンゴムを含む部材よ
りなる請求項3乃至5のいずれか一に記載の半導体製造
装置。
6. The semiconductor manufacturing apparatus according to claim 3, wherein said cushioning member is made of a member containing silicon rubber.
【請求項7】ステージ上に載置された、配線パターンが
形成されたテープと半導体チップとを、その上方に設け
た加圧手段によって加圧することにより張り合わせる半
導体製造方法において、 前記ステージと前記テープとの間に、前記テープと接す
る面側に所定の深さの溝が格子状に形成された緩衝材を
備え、該緩衝材の前記溝が埋まるように、前記加圧手段
によって押圧することを特徴とする半導体製造方法。
7. A semiconductor manufacturing method in which a tape and a semiconductor chip on which a wiring pattern is formed, which is mounted on a stage, are bonded by pressing with a pressing means provided above the semiconductor chip. Between the tape and the tape, a buffer material having a groove of a predetermined depth formed in a lattice shape on a surface side in contact with the tape is provided, and the pressing means is pressed so that the groove of the buffer material is filled. A semiconductor manufacturing method characterized by the above-mentioned.
【請求項8】ステージ上に載置された、配線パターンが
形成されたテープと半導体チップとを、その上方に設け
た加圧手段によって加圧することにより張り合わせる半
導体製造方法において、 前記ステージと前記テープとの間に、前記テープと接す
る面側に所定の高さのの突部が2次元配列された緩衝材
を備え、該緩衝材の前記突部が潰れて平坦化するよう
に、前記加圧手段によって押圧することを特徴とする半
導体製造方法。
8. A semiconductor manufacturing method for bonding a tape, on which a wiring pattern is formed, and a semiconductor chip mounted on a stage by pressing with a pressing means provided above the semiconductor chip, wherein the stage and the semiconductor chip are bonded to each other. A cushioning material is provided between the tape and the tape, the protrusion having a predetermined height being two-dimensionally arranged on a surface side in contact with the tape, and the cushioning material is crushed and flattened. A method for manufacturing a semiconductor, comprising pressing by a pressure means.
JP35187799A 1999-09-24 1999-12-10 Semiconductor manufacturing apparatus and semiconductor manufacturing method Expired - Fee Related JP3255162B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35187799A JP3255162B2 (en) 1999-09-24 1999-12-10 Semiconductor manufacturing apparatus and semiconductor manufacturing method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11-269657 1999-09-24
JP26965799 1999-09-24
JP35187799A JP3255162B2 (en) 1999-09-24 1999-12-10 Semiconductor manufacturing apparatus and semiconductor manufacturing method

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Publication Number Publication Date
JP2001160569A JP2001160569A (en) 2001-06-12
JP3255162B2 true JP3255162B2 (en) 2002-02-12

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