JP3149631B2 - Semiconductor device, its mounting apparatus and its mounting method - Google Patents

Semiconductor device, its mounting apparatus and its mounting method

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Publication number
JP3149631B2
JP3149631B2 JP16160693A JP16160693A JP3149631B2 JP 3149631 B2 JP3149631 B2 JP 3149631B2 JP 16160693 A JP16160693 A JP 16160693A JP 16160693 A JP16160693 A JP 16160693A JP 3149631 B2 JP3149631 B2 JP 3149631B2
Authority
JP
Japan
Prior art keywords
substrate
mounting
semiconductor device
die bond
paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16160693A
Other languages
Japanese (ja)
Other versions
JPH0758134A (en
Inventor
貞幸 角
茂成 高見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP16160693A priority Critical patent/JP3149631B2/en
Publication of JPH0758134A publication Critical patent/JPH0758134A/en
Application granted granted Critical
Publication of JP3149631B2 publication Critical patent/JP3149631B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/30155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体素子、特に、セ
ンサー素子などの三次元微細加工素子チップを実装した
半導体装置及びその実装装置及びその実装方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which a three-dimensional microfabricated device chip such as a sensor device is mounted, and more particularly to a mounting device and a mounting method thereof.

【０００２】[0002]

【従来の技術】本願発明は、チップ状の半導体素子、特
に、センサー素子などの三次元微細加工素子チップを実
装した半導体装置及びその実装装置及びその実装方法に
関するものである。まず、その半導体装置に実装する半
導体素子として赤外線検出素子を例にとり図５に基づき
説明する。図において、（ａ）は斜視図、（ｂ）は A-A
断面図である。１は半導体素子である赤外線検出素子、
２は略正方形平板状の半導体基板、３は半導体基板１上
に形成された熱絶縁膜、４は熱絶縁膜３上に形成され、
赤外線を感知する略正方形平板状のサーミスタ、５はボ
ンディングワイヤが接合されるボンディングパッド、６
はサーミスタ４とボンディングパッド５を接続する配
線、２ａはサーミスタ４の下方に形成された略四角錐台
状の空隙部である。サーミスタ４の下方の半導体基板部
分は除去されて空隙部２ａが形成されている。このよう
に構成することによって、サーミスタ４は熱絶縁膜３に
しか接しなくなるので、赤外線を吸収してサーミスタ４
で発生した熱が伝導によって逃げにくくなり、赤外線検
出の感度を高めることができる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted with a chip-shaped semiconductor element, in particular, a three-dimensional microfabricated element chip such as a sensor element, a mounting apparatus and a mounting method thereof. First, an infrared detecting element will be described as an example of a semiconductor element mounted on the semiconductor device with reference to FIG. In the figure, (a) is a perspective view, (b) is AA
It is sectional drawing. 1 is an infrared detecting element which is a semiconductor element,
2 is a semiconductor substrate having a substantially square plate shape, 3 is a thermal insulating film formed on the semiconductor substrate 1, 4 is formed on the thermal insulating film 3,
A thermistor having a substantially square plate shape that senses infrared rays; 5, a bonding pad to which a bonding wire is bonded;
Is a wiring connecting the thermistor 4 and the bonding pad 5, and 2a is a substantially truncated pyramid-shaped space formed below the thermistor 4. The portion of the semiconductor substrate below the thermistor 4 is removed to form a gap 2a. With this configuration, the thermistor 4 comes into contact only with the heat insulating film 3, so that it absorbs infrared rays and
Makes it difficult for the heat generated in the device to escape due to conduction, thereby increasing the sensitivity of infrared detection.

【０００３】次に、従来、チップ状の半導体素子を基板
（ステム）に実装するダイボンド工程で使用されていた
実装装置（ダイボンダ）の一例を図６に示す。但し、基
板を搬送する搬送ステージ及びその周辺部分と、ダイボ
ンドペーストを供給する装置の部分のみを示すことと
し、その他の部分については、図示及びその説明を省略
する。Next, FIG. 6 shows an example of a mounting apparatus (die bonder) conventionally used in a die bonding step of mounting a chip-shaped semiconductor element on a substrate (stem). However, only the transfer stage for transferring the substrate and its peripheral portion, and the portion of the device for supplying the die bond paste are shown, and illustration and description of other portions are omitted.

【０００４】図６において、７はチップ状の赤外線検出
素子を実装する基板を搬送する搬送ステージで、その搬
送ステージ７の上面には長尺状のキャリアフィルム８が
治具により固定されており、そのキャリアフィルム８上
には、長手方向に規則的に基板９が配置されている。In FIG. 6, reference numeral 7 denotes a transfer stage for transferring a substrate on which a chip-shaped infrared detecting element is mounted. On the upper surface of the transfer stage 7, a long carrier film 8 is fixed by a jig. On the carrier film 8, a substrate 9 is regularly arranged in the longitudinal direction.

【０００５】一方、ダイボンドペーストを供給する装置
の部分は、円板状で上面に平面視略Ｏ字状の溝１０ａが
形成されたエポキシテーブル１０と、そのエポキシテー
ブル１０の溝１０ａ内に溜められたダイボンドペースト
１１と、そのエポキシテーブル１０の溝１０ａの底面と
の間に一定間隙が形成されるように配置された略四角錐
台状のスキージ１２と、搬送ステージ７上の基板９とエ
ポキシテーブル１０間を移動するホルダー１３と、その
ホルダー１３の先端に取り付けられ、ダイボンドペース
ト１１を基板９上に転写する転写ピン１４から構成され
ている。ホルダー１３は、搬送ステージ７上の基板９と
エポキシテーブル１０間を移動できるように、水平及び
垂直方向に移動可能に構成されている。また、円板状の
エポキシテーブル１０は、その中心軸回りに回動可能に
構成されている。On the other hand, the part of the device for supplying the die bond paste is a disk-shaped epoxy table 10 having an upper surface formed with a substantially O-shaped groove 10a, and is stored in the groove 10a of the epoxy table 10. A substantially square truncated pyramid squeegee 12 arranged so as to form a fixed gap between the die bond paste 11 and the bottom surface of the groove 10 a of the epoxy table 10, the substrate 9 on the transfer stage 7, and the epoxy table It comprises a holder 13 that moves between 10 and transfer pins 14 that are attached to the tip of the holder 13 and transfer the die bond paste 11 onto the substrate 9. The holder 13 is configured to be movable in the horizontal and vertical directions so as to be able to move between the substrate 9 on the transfer stage 7 and the epoxy table 10. The disk-shaped epoxy table 10 is configured to be rotatable around its central axis.

【０００６】転写ピン１４の例を図７に示す。（ａ）は
正面図、（ｂ）は下面図である。図に示す例では、直方
体状の台部１４ａの底面に平面視略四角形の板状の転写
部１４ｂが形成されており、その転写部１４ｂの平坦な
底面１４ｃがダイボンドペーストを付着させる面となる
ように構成されている。FIG. 7 shows an example of the transfer pin 14. (A) is a front view, (b) is a bottom view. In the example shown in the figure, a substantially rectangular plate-shaped transfer portion 14b is formed on the bottom surface of the rectangular parallelepiped base portion 14a, and the flat bottom surface 14c of the transfer portion 14b is a surface to which the die bond paste is adhered. It is configured as follows.

【０００７】以上のように構成された実装装置のボンデ
ィングペースト供給動作について図８に基づき説明す
る。図において、９は赤外線検出素子を実装する基板、
１０はダイボンドペーストを溜めておくためのエポキシ
テーブル、１１はダイボンドペースト、１２はエポキシ
テーブル１０の溝１０ａ内に溜められたダイボンドペー
スト１１の表面を平坦化するスキージ、１４は転写ピン
で、基板９とエポキシテーブル１０と転写ピン１４につ
いては、それぞれの中央部での断面を示している。The bonding paste supply operation of the mounting apparatus configured as described above will be described with reference to FIG. In the figure, 9 is a substrate on which an infrared detecting element is mounted,
10 is an epoxy table for storing the die bond paste, 11 is the die bond paste, 12 is a squeegee for flattening the surface of the die bond paste 11 stored in the groove 10a of the epoxy table 10, 14 is a transfer pin, The cross section at the center of each of the epoxy table 10 and the transfer pin 14 is shown.

【０００８】まず、エポキシテーブル１０を回転させる
と、エポキシテーブル１０の平面視略Ｏ字状の溝１０ａ
内に溜められたペースト状のダイボンドペースト１１
は、スキージ１２によってその表面が平坦化され、溝１
１ａ内で所定の深さになる。次に、転写ピン１４の底面
１４ｃに、ダイボンドペースト１１が付着するように図
６に示したホルダー１３が移動する。その後、ホルダー
１３が基板９上に移動して転写ピン１４の底面１４ｃに
付着したダイボンドペースト１１が基板９上のチップ実
装位置に転写される。その転写されたダイボンドペース
ト１１上に赤外線検出素子のチップが配置された後、加
熱処理が行われて基板９への赤外線検出素子の実装が完
了する。First, when the epoxy table 10 is rotated, a substantially O-shaped groove 10a in plan view of the epoxy table 10 is formed.
Die bond paste 11 stored inside
Is flattened by the squeegee 12 and the groove 1
It becomes a predetermined depth within 1a. Next, the holder 13 shown in FIG. 6 moves so that the die bond paste 11 adheres to the bottom surface 14c of the transfer pin 14. Thereafter, the holder 13 moves onto the substrate 9 and the die bond paste 11 attached to the bottom surface 14c of the transfer pin 14 is transferred to the chip mounting position on the substrate 9. After the chip of the infrared detecting element is arranged on the transferred die bond paste 11, a heating process is performed to complete the mounting of the infrared detecting element on the substrate 9.

【０００９】上記に示したダイボンダの転写ピン１４の
転写面である底面１４ｃは平坦であり、赤外線検出素子
のチップ底面のほぼ全面にダイボンドペーストを塗布し
て基板９と接合していた。これは、通常のＩＣチップを
ダイボンドする場合は、ＩＣチップの裏面が電極を構成
しており、基板と電気的接続を取らなければならなかっ
たり、ＩＣチップの放熱性を高める必要性があったから
である。The bottom surface 14c, which is the transfer surface of the transfer pin 14 of the die bonder described above, is flat, and a die bond paste is applied to almost the entire bottom surface of the chip of the infrared detecting element and joined to the substrate 9. This is because when a normal IC chip is die-bonded, the back surface of the IC chip constitutes an electrode, and it is necessary to make an electrical connection with the substrate or to increase the heat dissipation of the IC chip. It is.

【００１０】[0010]

【発明が解決しようとする課題】上記に示したような従
来の実装装置（ダイボンダ）を用いて、図５に示した赤
外線検出素子１をダイボンディングする場合の問題点を
図９及び図１０に基づいて説明する。図９は基板９上の
ダイボンドペースト転写位置を示す平面図で、図７に示
した転写ピン１４を用いた場合、略正方形状に示された
赤外線検出素子の実装領域１５に対し、その領域の略全
域にダイボンドペースト１１が塗布されることを示した
ものである。図１０は基板９上に塗布されたダイボンド
ペースト１１上に赤外線検出素子１を配置した状態を示
す断面図である。図１０に示すように、実装領域１５の
略全域にダイボンドペースト１１を塗布した場合、赤外
線検出素子１の空隙部２ａから熱絶縁膜３にまでダイボ
ンドペースト１１の這い上がりが発生するため、赤外線
を吸収することによってサーミスタ４で発生した熱がダ
イボンドペースト１１を介して基板９に逃げやすくなっ
てしまうため素子感度の低下を招いていた。FIGS. 9 and 10 show the problems when the infrared detecting element 1 shown in FIG. 5 is die-bonded using the conventional mounting device (die bonder) as described above. It will be described based on the following. FIG. 9 is a plan view showing the transfer position of the die bond paste on the substrate 9. When the transfer pin 14 shown in FIG. 7 is used, the mounting area 15 of the infrared detection element shown in a substantially square shape is This shows that the die bond paste 11 is applied to substantially the entire area. FIG. 10 is a cross-sectional view showing a state in which the infrared detecting element 1 is arranged on the die bond paste 11 applied on the substrate 9. As shown in FIG. 10, when the die bond paste 11 is applied to substantially the entire area of the mounting area 15, the die bond paste 11 creeps up from the gap 2 a of the infrared detecting element 1 to the heat insulating film 3. Absorption causes heat generated by the thermistor 4 to easily escape to the substrate 9 via the die bond paste 11, resulting in a decrease in device sensitivity.

【００１１】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、赤外線検出素子等の三次
元微細加工素子チップへの余分なダイボンドペーストの
這い上がりを無くし、素子特性の低下を防止することが
できる半導体装置及びその実装装置の構造と、その半導
体装置の実装方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prevent the excess die bond paste from creeping up on a three-dimensional microfabricated device chip such as an infrared detecting device, and to improve device characteristics. It is an object of the present invention to provide a semiconductor device capable of preventing the deterioration, a structure of a mounting device thereof, and a mounting method of the semiconductor device.

【００１２】[0012]

【課題を解決するための手段】上記課題を解決するた
め、請求項１記載の半導体装置は、三次元微細加工部を
有する半導体素子をダイボンドペーストを介して基板上
に実装した半導体装置において、前記ダイボンドペース
トが前記基板上の前記半導体素子の実装位置で前記三次
元微細加工部外周に局所的に、少なくとも前記半導体素
子のワイヤボンディングパッドの下方位置近傍に配置さ
れていることを特徴とするものである。In order to solve the above-mentioned problems, a semiconductor device according to the first aspect of the present invention has a three-dimensional microfabricated part.
A semiconductor device having a semiconductor element mounted on a substrate via a die bond paste, wherein the die bond paste is tertiary at a mounting position of the semiconductor element on the substrate.
The semiconductor device is characterized in that it is arranged locally on the outer periphery of the microfabricated portion at least in the vicinity of a position below the wire bonding pad of the semiconductor element.

【００１３】請求項２記載の半導体装置の実装装置は、
三次元微細加工部を有する半導体素子をダイボンドペー
ストを介して基板上に実装する半導体装置の実装装置に
おいて、前記ダイボンドペーストを前記基板上の前記半
導体素子の実装位置で前記三次元微細加工部外周に局所
的に、少なくとも前記半導体素子のワイヤボンディング
パッドの下方位置近傍に供給することを特徴とするもの
である。According to a second aspect of the present invention, there is provided a semiconductor device mounting apparatus,
In a semiconductor device mounting apparatus for mounting a semiconductor element having a three-dimensional fine processing portion on a substrate via a die bond paste, the die bond paste is mounted on the outer periphery of the three-dimensional fine processing portion at a mounting position of the semiconductor element on the substrate. It is characterized in that it is supplied locally at least in the vicinity of a position below the wire bonding pad of the semiconductor element.

【００１４】請求項３記載の半導体装置の実装方法は、
三次元微細加工部を有する半導体素子をダイボンドペー
ストを介して基板上に実装する半導体装置の実装方法に
おいて、前記ダイボンドペーストを前記基板上の前記半
導体素子の実装位置で前記三次元微細加工部外周に局所
的に、少なくとも前記半導体素子のワイヤボンディング
パッドの下方位置近傍に供給して実装を行うことを特徴
とするものである。According to a third aspect of the present invention, there is provided a semiconductor device mounting method comprising:
In a semiconductor device mounting method of mounting a semiconductor element having a three-dimensional microfabricated portion on a substrate via a die bond paste, the die bond paste is mounted on the outer periphery of the three-dimensional microfabricated portion at a mounting position of the semiconductor element on the substrate. The semiconductor device is characterized in that the semiconductor device is locally supplied and mounted at least in the vicinity of a position below the wire bonding pad of the semiconductor element.

【００１５】[0015]

【作用】図１に示すように、基板上において、実装する
赤外線検出素子のワイヤボンディングパッドの下方位置
にのみダイボンドペーストを局所的に供給してダイボン
ディングすることによって、赤外線検出素子への余分な
ダイボンドペーストの這い上がりを防止することができ
る。赤外線検出素子のワイヤボンディングパッド位置で
は、赤外線検出素子と基板間にダイボンドペーストが介
在するため、ワイヤーボンディングの際、赤外線検出素
子のワイヤボンディングパッド位置にかかる外力によっ
て赤外線検出素子のチップが割れることもない。また、
ワイヤーボンディングパッド位置にかかる超音波エネル
ギーを拡散させてしまうことがないためワイヤーボンデ
ィング不良を招くこともない。As shown in FIG. 1, the die bonding paste is locally supplied only to the position below the wire bonding pad of the infrared detecting element to be mounted on the substrate, and die bonding is performed. It is possible to prevent the die bond paste from climbing up. At the wire bonding pad position of the infrared detecting element, since the die bond paste is interposed between the infrared detecting element and the substrate, the chip of the infrared detecting element may be broken by an external force applied to the position of the wire bonding pad of the infrared detecting element during wire bonding. Absent. Also,
Since the ultrasonic energy applied to the position of the wire bonding pad is not diffused, a wire bonding failure does not occur.

【００１６】[0016]

【実施例】図５に示した赤外線検出素子のような三次元
微細加工素子は、チップ裏面で基板と電気的接続を得る
必要がなく、放熱する必要もないのでチップ裏面全面に
ダイボンドペーストを塗布する必要がない。しかし、ダ
イボンド工程後のワイヤーボンディング工程では、ワイ
ヤーボンディング時の超音波エネルギーの拡散を防止す
ると共にチップの破損を防止するため、チップのボンデ
ィングパッド位置では、赤外線検出素子はダイボンドペ
ーストにて基板と接着され、支持されていることが必要
である。また、センサー素子等の多くの三次元微細加工
素子はＣＡＮ封止されるが、この場合、チップ周辺を完
全に樹脂封止する場合に比べ、耐振動性が問題となり重
要な評価項目となるので、この耐振動性の試験に耐え得
るダイボンド強度も必要である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A three-dimensional microfabricated element such as an infrared detecting element shown in FIG. 5 does not require electrical connection with the substrate on the back surface of the chip and does not need to radiate heat, so that a die bond paste is applied to the entire back surface of the chip. No need to do. However, in the wire bonding process after the die bonding process, the infrared detecting element is bonded to the substrate with a die bonding paste at the bonding pad position of the chip to prevent the diffusion of ultrasonic energy during wire bonding and to prevent chip breakage. Needs to be supported and supported. In addition, many three-dimensional microfabricated elements such as sensor elements are sealed with CAN. In this case, vibration resistance becomes a problem and becomes an important evaluation item compared with the case where the chip periphery is completely sealed with resin. A die bond strength that can withstand the vibration resistance test is also required.

【００１７】図５に示した赤外線検出素子の場合、これ
らの条件を満たすためには、図１に示すようにしてダイ
ボンディングを行えばよい。（ａ）は赤外線検出素子の
ワイヤボンディングパッドの下方位置にのみ局所的にダ
イボンドペーストを塗布して赤外線検出素子を基板に実
装した状態を示す斜視図である。本願発明の半導体装置
は、チップ状の半導体素子と基板を接合するダイボンド
ペーストの位置に特徴を有するものであるので、従来と
同等構成については同符号を付すこととする。図におい
て、赤外線検出素子１は、基板９上にダイボンドペース
ト１１を介して接合されているが、ダイボンドペースト
１１は、赤外線検出素子１の外周の４辺のそれぞれの中
央近傍に形成されたワイヤボンディングパッド５の下方
の基板上にのみ、平面視略円形状に供給されている。
（ｂ）は B-B断面図で、赤外線検出素子１は基板９上に
局所的に供給されたダイボンドペースト１１によって基
板９に接合されているが、赤外線検出素子１の空隙部２
ａへのダイボンドペースト１１の余分な這い上がりは発
生していない。図２は赤外線検出素子１の実装位置１５
に対するダイボンドペースト１１の塗布位置を示した平
面図である。このようにダイボンドペースト１１の塗布
位置を限定することによって、図１（ｂ）に示すよう
に、赤外線検出素子１の空隙部２ａに対するダイボンド
ペースト１１の余分な這い上がりを防止することができ
る。この場合、赤外線検出素子１の実装位置１５に対し
て、図２に示すような位置にダイボンドペースト１１を
塗布すればよいことになる。In the case of the infrared detecting element shown in FIG. 5, in order to satisfy these conditions, die bonding may be performed as shown in FIG. (A) is a perspective view showing a state in which a die bonding paste is locally applied only to a position below a wire bonding pad of the infrared detection element and the infrared detection element is mounted on a substrate. Since the semiconductor device of the present invention is characterized by the position of the die bond paste for joining the chip-shaped semiconductor element and the substrate, the same reference numerals are given to the same components as those in the related art. In the figure, the infrared detecting element 1 is bonded on a substrate 9 via a die bonding paste 11, and the die bonding paste 11 is formed by wire bonding formed near the center of each of four sides on the outer periphery of the infrared detecting element 1. It is supplied in a substantially circular shape in plan view only on the substrate below the pad 5.
(B) is a cross-sectional view taken along the line BB, in which the infrared detecting element 1 is bonded to the substrate 9 by a die bond paste 11 locally supplied on the substrate 9, and the gap 2 of the infrared detecting element 1 is formed.
No extra crawling of the die bond paste 11 to a occurs. FIG. 2 shows a mounting position 15 of the infrared detecting element 1.
FIG. 3 is a plan view showing a coating position of a die bond paste 11 with respect to FIG. By limiting the application position of the die bond paste 11 in this way, as shown in FIG. 1B, it is possible to prevent the die bond paste 11 from creeping over the gap 2a of the infrared detecting element 1. In this case, the die bonding paste 11 may be applied to a position as shown in FIG. 2 with respect to the mounting position 15 of the infrared detecting element 1.

【００１８】図２に示した位置にダイボンドペーストを
転写する場合の転写ピンの一例を図３に示す。（ａ）は
転写ピンの正面図、（ｂ）は下面図である。直方体状の
転写ピン１６の底面には、基板のダイボンドペースト塗
布位置（赤外線検出素子のワイヤボンディングパッド位
置）に対応した位置に、略直方体状の突起１７が形成さ
れており、その突起１７の底面１７ａがダイボンドペー
ストを付着させる転写面となるように構成されている。FIG. 3 shows an example of a transfer pin for transferring the die bond paste to the position shown in FIG. (A) is a front view of a transfer pin, (b) is a bottom view. On the bottom surface of the rectangular transfer pin 16, a substantially rectangular projection 17 is formed at a position corresponding to the die bond paste application position (the wire bonding pad position of the infrared detecting element) on the substrate. 17a is configured to be a transfer surface to which the die bond paste is adhered.

【００１９】図３に示した転写ピン１６を取り付けた実
装装置（ダイボンダ）のボンディングペースト供給動作
について図４に基づき説明する。従来例と同等構成につ
いては同符号を付すこととする。エポキシテーブル１０
が回転すると、エポキシテーブル１０の溝１１ａ内に溜
められたダイボンドペースト１１は、スキージ１２によ
ってその表面が平坦化され、溝１１ａ内で所定の深さに
なる。次に、ホルダー１３の先端に取り付けられた転写
ピン１６底面の突起１７の底面１７ａ及び側面の一部に
のみダイボンドペースト１１が付着するようにホルダー
１３が移動する。その後、ホルダー１３は基板９上に移
動して、転写ピン１６底面の突起１７に付着したダイボ
ンドペースト１１を基板９上のチップ実装位置に転写す
る。The bonding paste supply operation of the mounting apparatus (die bonder) to which the transfer pins 16 shown in FIG. 3 are attached will be described with reference to FIG. The same components as those in the conventional example are denoted by the same reference numerals. Epoxy table 10
When is rotated, the surface of the die bond paste 11 stored in the groove 11a of the epoxy table 10 is flattened by the squeegee 12, and has a predetermined depth in the groove 11a. Next, the holder 13 is moved so that the die bond paste 11 adheres only to a part of the bottom surface 17a and the side surface of the projection 17 on the bottom surface of the transfer pin 16 attached to the tip of the holder 13. Thereafter, the holder 13 moves onto the substrate 9, and transfers the die bond paste 11 attached to the projection 17 on the bottom surface of the transfer pin 16 to a chip mounting position on the substrate 9.

【００２０】以上のように、図３に示したような転写ピ
ンを取りつけた実装装置を用いて、上記のようにダイボ
ンドペーストを転写することによって、図２に示した塗
布位置にダイボンドペーストを局所的に供給することが
できる。As described above, the die bonding paste is transferred to the application position shown in FIG. 2 by transferring the die bonding paste as described above using the mounting apparatus having the transfer pins as shown in FIG. Can be supplied.

【００２１】なお、転写ピンの形状は、実施例に限定さ
れず、チップ形状に応じて変えればよい。また、実施例
では、ダイボンドペーストは転写ピンにより基板上に供
給されたがディスペンサー等により供給することもでき
るので、実装装置の構成及びその実装方法は実施例に限
定されるものではない。The shape of the transfer pin is not limited to the embodiment but may be changed according to the shape of the chip. Further, in the embodiment, the die bonding paste is supplied onto the substrate by the transfer pin, but can be supplied by a dispenser or the like. Therefore, the configuration of the mounting apparatus and the mounting method are not limited to the embodiment.

【００２２】[0022]

【発明の効果】以上のように、本願発明の半導体装置及
びその実装装置及び実装方法によれば、三次元微細加工
素子チップの三次元微細加工部への余分なダイボンドペ
ーストの付着が防止できるので、センサー素子等の三次
元微細加工素子チップの性能を損なうことなく、従来の
ダイボンダを用いて三次元微細加工素子チップの実装を
行うことができる。As is evident from the foregoing description, according to the semiconductor device and the mounting apparatus and mounting method of the present invention, the attachment of extra die bonding paste to the three-dimensional microfabrication portion of the three-dimensional microfabricated <br/> device chip since but prevented, without impairing the three-dimensional micro-fabricated device chip performance of such sensor elements, it is possible to implement a three-dimensional micro-fabricated device chip using a conventional die bonder.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本願発明に係る半導体装置の半導体素子実装状
態を示す内部構造図であり、（ａ）は斜視図、（ｂ）は
B-B断面図である。FIGS. 1A and 1B are internal structural views showing a semiconductor element mounted state of a semiconductor device according to the present invention, wherein FIG. 1A is a perspective view and FIG.
It is BB sectional drawing.

【図２】本願発明に係る半導体装置における基板のダイ
ボンドペースト塗布位置を示す平面図である。FIG. 2 is a plan view showing a die bond paste application position on a substrate in the semiconductor device according to the present invention.

【図３】本願発明に係る実装装置の転写ピンの一例を示
す構造図で、（ａ）は正面図、（ｂ）は下面図である。3A and 3B are structural views showing an example of a transfer pin of the mounting apparatus according to the present invention, wherein FIG. 3A is a front view and FIG. 3B is a bottom view.

【図４】本願発明に係る実装方法を示す工程図である。FIG. 4 is a process chart showing a mounting method according to the present invention.

【図５】本願発明に係る半導体装置に実装する半導体素
子の一例を示す構造図である。（ａ）は斜視図、（ｂ）
は A-A断面図である。FIG. 5 is a structural view showing an example of a semiconductor element mounted on the semiconductor device according to the present invention. (A) is a perspective view, (b)
2 is an AA sectional view.

【図６】本願発明に係る実装装置の概略構成を示す斜視
図である。FIG. 6 is a perspective view showing a schematic configuration of a mounting apparatus according to the present invention.

【図７】従来の実装装置の転写ピンの一例を示す構造図
で、（ａ）は正面図、（ｂ）は下面図である。FIG. 7 is a structural view showing an example of a transfer pin of a conventional mounting apparatus, wherein (a) is a front view and (b) is a bottom view.

【図８】従来の実装方法を示す工程図である。FIG. 8 is a process chart showing a conventional mounting method.

【図９】従来の半導体装置における基板のダイボンドペ
ースト塗布位置を示す平面図である。FIG. 9 is a plan view showing a die bond paste application position on a substrate in a conventional semiconductor device.

【図１０】従来の半導体装置の半導体素子実装前後の状
態を示す断面図であり、（ａ）は実装前の状態、（ｂ）
は実装後の状態を示すものである。10A and 10B are cross-sectional views showing a state before and after mounting a semiconductor element of a conventional semiconductor device, wherein FIG. 10A is a state before mounting, and FIG.
Indicates the state after mounting.

【符号の説明】[Explanation of symbols]

１ 赤外線検出素子 ２ 半導体基板 ２ａ 空隙部 ３ 熱絶縁膜 ４ サーミスタ ５ ワイヤボンディングパッド ６ 配線 ７ 搬送ステージ ８ キャリアフィルム ９ 基板 １０ エポキシテーブル １０ａ 溝 １１ ダイボンドペースト １２ スキージ １３ ホルダー １４ 転写ピン １４ａ 台部 １４ｂ 転写部 １４ｃ 底面 １５ 実装領域 １６ 転写ピン １７ 突起 １７ａ 底面 REFERENCE SIGNS LIST 1 infrared detecting element 2 semiconductor substrate 2 a void 3 thermal insulating film 4 thermistor 5 wire bonding pad 6 wiring 7 transfer stage 8 carrier film 9 substrate 10 epoxy table 10 a groove 11 die bond paste 12 squeegee 13 holder 14 transfer pin 14 a base 14 b transfer Part 14c bottom surface 15 mounting area 16 transfer pin 17 protrusion 17a bottom surface

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 21/60 301 H01L 31/02 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/52 H01L 21/60 301 H01L 31/02

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 三次元微細加工部を有する半導体素子を
ダイボンドペーストを介して基板上に実装した半導体装
置において、前記ダイボンドペーストが前記基板上の前
記半導体素子の実装位置で前記三次元微細加工部外周に
局所的に、少なくとも前記半導体素子のワイヤボンディ
ングパッドの下方位置近傍に配置されていることを特徴
とする半導体装置。1. A semiconductor device having a semiconductor element having a three-dimensional microfabricated portion mounted on a substrate via a die-bonding paste, wherein the die-bonding paste is mounted on the substrate at the mounting position of the semiconductor element. A semiconductor device, which is locally arranged on an outer periphery at least near a position below a wire bonding pad of the semiconductor element. 【請求項２】 三次元微細加工部を有する半導体素子を
ダイボンドペーストを介して基板上に実装する半導体装
置の実装装置において、前記ダイボンドペーストを前記
基板上の前記半導体素子の実装位置で前記三次元微細加
工部外周に局所的に、少なくとも前記半導体素子のワイ
ヤボンディングパッドの下方位置近傍に供給することを
特徴とする半導体装置の実装装置。2. A device for mounting a semiconductor device having a three-dimensional microfabricated part on a substrate via a die bond paste, wherein the die bond paste is mounted on the substrate at the mounting position of the semiconductor element on the substrate. Fine processing
An apparatus for mounting a semiconductor device, wherein the semiconductor device is supplied locally at least on an outer periphery of a processed portion , at a position near a position below a wire bonding pad of the semiconductor element. 【請求項３】 三次元微細加工部を有する半導体素子を
ダイボンドペーストを介して基板上に実装する半導体装
置の実装方法において、前記ダイボンドペーストを前記
基板上の前記半導体素子の実装位置で前記三次元微細加
工部外周に局所的に、少なくとも前記半導体素子のワイ
ヤボンディングパッドの下方位置近傍に供給して実装を
行うことを特徴とする半導体装置の実装方法。3. A method for mounting a semiconductor device having a three-dimensional microfabricated part on a substrate via a die bond paste, wherein the die bond paste is mounted on the substrate at the mounting position of the semiconductor element on the substrate. Fine processing
A method of mounting a semiconductor device, wherein the semiconductor device is mounted by supplying the semiconductor device locally at least on the periphery of a processed portion at a position near a position below a wire bonding pad of the semiconductor element.
JP16160693A 1993-06-30 1993-06-30 Semiconductor device, its mounting apparatus and its mounting method Expired - Fee Related JP3149631B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP16160693A JP3149631B2 (en) 1993-06-30 1993-06-30 Semiconductor device, its mounting apparatus and its mounting method

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JPH0758134A JPH0758134A (en) 1995-03-03
JP3149631B2 true JP3149631B2 (en) 2001-03-26

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004251742A (en) 2003-02-20 2004-09-09 Denso Corp Sensor device
JP2004301740A (en) 2003-03-31 2004-10-28 Denso Corp Semiconductor sensor
JP2004301744A (en) 2003-03-31 2004-10-28 Denso Corp Infrared sensor
JP6248441B2 (en) * 2013-07-12 2017-12-20 富士通オプティカルコンポーネンツ株式会社 Optical device and optical device manufacturing method
JP6414295B2 (en) * 2017-08-02 2018-10-31 富士通オプティカルコンポーネンツ株式会社 Optical device and optical device manufacturing method

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