JP3245872B2 - Peak value detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak value detecting circuit, and more particularly, to a peak value detecting circuit suitable for use in a peak value detecting circuit for reducing the influence of a DC offset of an output buffer.

[0002]

2. Description of the Related Art As is well known, peak value detection circuits are used in various electronic equipment fields. Such a peak value detection circuit constantly monitors the magnitude of the input signal voltage, and holds the largest voltage value of the input signals so far. The configuration generally includes a voltage comparison unit, a peak voltage holding circuit, a holding voltage control circuit, a signal output circuit, and the like. In the peak value detection circuit, a signal input from the outside is applied to a comparison input terminal of a comparator constituting the voltage comparison unit, and a voltage held by the peak voltage holding circuit is applied to a comparison input terminal of the comparator. And the magnitudes of these two signals are compared. When a signal input from the outside is larger, the signal is held as a new peak value in the peak holding capacitor of the peak voltage holding circuit. Therefore, as described above, the largest one of the signals input in the past is always held in the peak voltage holding circuit.

[0003]

A signal output circuit for deriving the peak voltage held in the peak voltage holding circuit to the outside is provided for buffering with an external circuit. A buffer amplifier that performs impedance conversion is used as the circuit. However, since a DC offset may occur in the buffer amplifier, if the peak value held in the peak voltage holding circuit is output to the outside through the buffer amplifier, the positive offset or the negative offset becomes the peak value. There is a disadvantage that the signal appears as it is in the output of the detection circuit.
For this reason, the input / output characteristics of the conventional peak value detection circuit vary, and especially when the signal level to be handled is small, the DC offset has been a serious problem.

In order to solve the above-mentioned disadvantage caused by the DC offset, the applicant of the present invention has proposed to prevent a signal output circuit provided in an output stage from appearing in an external output signal even if the DC offset occurs. A possible peak value detection circuit has been proposed in Japanese Patent Application No. 2-214592. The peak value detection circuit includes a voltage comparison unit 20, a charge control unit 21, an output buffer 22, a holding capacitor 23, a discharging unit 24, and the like, as shown in the block diagram of FIG.

In general, an emitter follower is used as the charge control unit 21 in FIG. 5 as shown in the circuit diagram of FIG. 6, but using the emitter follower has the following disadvantages. That is, when the input potential is lower than the potential on the hot side of the hold capacitor 23, the hold mode is set. At this time, since the transistor P1 is turned off, the base potential of the transistor Q1 becomes lower than the emitter potential. The emitter potential of the transistor Q1 corresponds to a peak value of the input signal and, depending on the constant current source circuit form of I _1, the base potential of the transistor Q1 is G
The potential becomes higher by a certain value from ND. For example, the constant current source I ₁ is the transistor Q, as shown in the circuit diagram of FIG. 7
5 and when configured for the power source V1, the base potential of the transistor _{Q1, V1-1 · V BE + V CE} (sat)
Becomes

FIG. 8 shows the potentials of the base and the emitter of the transistor Q1. When the positive peak value of the input signal is lower than the held voltage, that is , the emitter potential of the transistor Q1, the base potential of the transistor Q1 becomes lower than the emitter potential. Therefore, depending on the operating conditions, the V _BE reverse voltage exceeds the breakdown voltage between the base and the emitter of the transistor Q1, and this phenomenon causes the following problem. That is, (1) In the hold mode, the recovery time constant is set to a predetermined value by the hold capacitor and the resistor. However, the charge of the hold capacitor 23 escapes from the emitter of the transistor Q1 to the base, and this is fixed. since thus is discharged through current source I _1, there is a problem that recovery can not set the time constant becomes faster correctly.

(2) Since the reverse breakdown voltage between the base and the emitter of the transistor Q1 is exceeded, the transistor Q1 is deteriorated. The following measures can be considered as measures to avoid these problems. In other words, to remove the constant current source I ₁ (a). (b) Set operating conditions so that V _{BE of} transistor Q1 does not exceed the reverse breakdown voltage. And so on. However, in the case of (a), there is an inconvenience that an error occurs due to leakage at the first stage. In the case (b), the input signal amplitude and the reference potential of the input signal are inevitably reduced, and the dynamic range of the peak detector circuit becomes narrow. Further, since the dynamic range is narrowed, the ratio of the error component due to ΔV _BE or the like becomes relatively large with respect to the input signal, and the accuracy is deteriorated. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to prevent a base voltage of a transistor constituting an emitter follower provided in an output stage of a charge control unit from excessively decreasing in a hold mode.

[0008]

A peak value detecting circuit according to the present invention comprises a peak voltage holding circuit for holding a peak value of an input signal voltage, a peak voltage held by the peak voltage holding circuit, and a peak voltage input from the outside. A voltage comparing unit that compares the signal voltage with the peak voltage.
It is determined that the signal voltage input from outside is higher
A charge control circuit, which is provided for controlling the charging of the peak voltage holding circuit based on the input signal voltage when the input signal voltage is high, and whose output stage is constituted by an emitter follower circuit; That limits the base voltage of the emitter follower circuit provided at the output stage of the charge control circuit so that the base voltage does not fall below a predetermined voltage when the peak voltage is smaller than the peak voltage held by the peak voltage holding circuit. Means.

[0009]

When the input signal voltage is smaller than the peak voltage held by the peak voltage holding circuit and the operation mode is the hold mode, the emitter follower provided at the output stage of the charge control circuit is used. Limit the base voltage of the transistors in the circuit so that it does not fall below a specified voltage.
You . This prevents the base potential of the transistor of the emitter follower circuit from dropping too much during the hold mode.

[0010]

FIG. 1 is a configuration diagram of a peak value detection circuit showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific configuration of the circuit of FIG. As shown in FIGS. 1 and 2, a peak value detection circuit according to the present embodiment includes a voltage comparison unit 1, a charge control unit 2,
It comprises an output buffer 3, a holding capacitor 4, a discharging means 5, a voltage clamping means 6, and the like. That is, the voltage clamp means 6 is provided in the peak value detection circuit shown in FIG. Voltage clamp means 6 is constructed by connecting the collector of transistor Q2 to power supply Vcc, connecting the emitter to the base of transistor Q1, and applying the output voltage of output buffer 3 to the base, as shown in FIG. Have been.

In the peak value detecting circuit according to the present embodiment, when the peak value of the input signal is higher than the output potential, the transistors P1 and Q1 are turned on and the transistor Q2 is turned off. The same operation as the conventional example is performed. On the other hand, when the peak value of the input signal is lower than the output potential, a hold mode is set, and the transistors P1 and Q
1 turns off and Q2 turns on. At this time, the base-emitter voltage of the transistor Q1 becomes equal to a value obtained by reversing the polarity of the base-emitter voltage of the transistor Q2, and is fixed to this value. Therefore, it is possible to completely prevent the disadvantage that the voltage value is reversed between the base and the emitter of the transistor Q1 to cause breakdown, and the problem of the conventional example can be completely solved.

Next, another embodiment of the present invention will be described with reference to FIG. As is clear from FIG. 3, in the case of the present embodiment, the voltage clamp means 6 is constituted by the transistor Q2 and the resistors R1 and R2. In this case, the transistor Q
2 is set to a potential lower than (reference potential + 2 · V _BE ). In the peak value detection circuit of FIG. 3, when the peak value of the input signal is higher than the output potential, the transistors P1 and Q1 turn on. Therefore, the base potential of the transistor Q1 becomes higher than (reference potential + 1.V _BE ), so that the transistor Q2 is turned off. The operation at this time is the same as the conventional example.

On the other hand, when the peak value of the input signal is lower than the output potential, the transistors P1 and Q1 turn off and the transistor Q2 turns on. At this time, the base potential of the transistor Q1 becomes (base potential of Q2−1 · V _BE ). In the embodiment of FIG. 3, when the amplitude of the input signal is large, the reverse voltage between the base and the emitter of the transistor Q2 may exceed the breakdown voltage. However, unlike the conventional example, the base potential of the transistor Q1 is clamped. The degree of freedom in design is much higher than in the prior art. Note that R1, R2, Q in FIG.
The circuit part 2 is a diode 1 as shown in FIG.
0 may be used. Alternatively, a zener diode 11 may be used as shown in FIG. 4B, or a diode 10 or a constant current source 12 may be used as shown in FIG. May be arbitrarily configured.

In the above embodiment, a description has been given of the peak value detection circuit of the type that performs negative feedback from the output side of the output buffer 3 to the voltage comparison unit 1. The same can be considered for a peak value detection circuit of the type that performs negative feedback to the comparison section, and the present invention can be applied.

[0015]

According to the present invention, as described above, the voltage clamp means is provided, and the input signal voltage becomes smaller than the peak voltage held by the peak voltage holding circuit, and the operation mode becomes the hold mode. The base voltage of the transistor of the emitter follower circuit provided at the output stage of the charge control circuit by the action of the voltage clamp means.
Since the voltage is limited so as not to be lower than the predetermined voltage, it is possible to prevent the base potential of the transistor of the emitter follower circuit from excessively dropping in the hold mode. Therefore, it is possible to prevent the breakdown between the base and the emitter of the emitter follower transistor of the charge control unit from occurring, so that the recovery constant can be set correctly and the deterioration due to the base-emitter breakdown of the emitter follower transistor can be prevented. Can be prevented.

When the clamp voltage is set to a constant voltage independent of the output voltage of the peak detector,
When the amplitude of the input signal is large, breakdown occurs between the base and the emitter of the emitter follower transistor of the charge control unit, so that the amplitude of the input signal is limited. Since the decrease in potential is much smaller, the degree of freedom in designing the power supply voltage, signal amplitude, and the like can be made much higher.
For this reason, the maximum signal amplitude can be set large, so that the accuracy as a peak detector can be kept good.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a peak value detection circuit showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a peak value detection circuit.

FIG. 3 is a circuit diagram of a peak value detection circuit showing an example different from FIG.

FIG. 4 is a circuit diagram showing a modification of the voltage clamping means.

FIG. 5 is a configuration diagram illustrating an example of a conventional peak value detection circuit.

6 is a circuit diagram showing a specific circuit configuration of the peak value detection circuit of FIG.

FIG. 7 is a circuit diagram illustrating an example of a constant current source.

FIG. 8 is a diagram illustrating the potential of each unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage comparison part 2 Charge control part 3 Output buffer 4 Hold capacitor 5 Discharge means 6 Voltage clamp means

Claims (1)

(57) [Claims] 1. A peak voltage holding circuit for holding a peak value of an input signal voltage, a voltage comparing unit for comparing a peak voltage held by the peak voltage holding circuit with a signal voltage input from the outside, The voltage comparator receives the external voltage higher than the peak voltage.
When it is determined that the input signal voltage is
The peak voltage holding circuit on the basis of the force the signal voltage
A charge control circuit which is provided for charge control and whose output stage is formed by an emitter follower circuit; and the magnitude of the input signal voltage is smaller than the peak voltage held by the peak voltage holding circuit. A peak value detecting circuit provided with a clamp means for limiting a base voltage of an emitter follower circuit provided at an output stage of the charge control circuit so as not to be lower than a predetermined voltage.