TWI755242B - Voltage converter and class-d amplifier - Google Patents

Voltage converter and class-d amplifier Download PDF

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TWI755242B
TWI755242B TW110100331A TW110100331A TWI755242B TW I755242 B TWI755242 B TW I755242B TW 110100331 A TW110100331 A TW 110100331A TW 110100331 A TW110100331 A TW 110100331A TW I755242 B TWI755242 B TW I755242B
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output
voltage
circuit
charging
error amplifier
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TW110100331A
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TW202228386A (en
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黃揚景
施登耀
許雅綿
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晶豪科技股份有限公司
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Abstract

A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect sn output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

Description

電壓轉換器以及D類放大器 Voltage Converters and Class D Amplifiers

本發明有關於電壓轉換器以及D類放大器，特別有關於可在不使迴路(loop)異常的情況下補償輸出電容的漏電流的電壓轉換器以及D類放大器。 The present invention relates to a voltage converter and a class D amplifier, and more particularly, to a voltage converter and a class D amplifier capable of compensating for the leakage current of the output capacitor without causing an abnormality in the loop.

習知的電壓轉換器可能會包含具有輸出電容的輸出電路(bootstrap circuit)。然而，在動作期間，輸出電容的電壓可能會因為預驅動器的消耗而變低。此種情況可能會讓輸出電路無法正常運作，例如造成迴路的異常。 A conventional voltage converter may include a bootstrap circuit with an output capacitor. However, during operation, the output capacitor voltage may drop due to pre-driver consumption. Such a situation may cause the output circuit to fail to function properly, for example, causing an abnormality in the loop.

因此，本發明一目的為提供一種在補償輸出電容的漏電流時不會造成迴路異常的電壓轉換器。 Therefore, an object of the present invention is to provide a voltage converter that does not cause loop abnormality when compensating for the leakage current of the output capacitor.

本發明另一目的為提供一種在補償輸出電容的漏電流時不會造成迴路異常的D類放大器。 Another object of the present invention is to provide a class D amplifier that does not cause loop abnormality when compensating for the leakage current of the output capacitor.

本發明一實施例揭露了一種電壓轉換器，包含一輸出電路、一誤差放大器以及一充電控制電路。輸出電路包含一輸出電容。充電控制電路包含：一偵測電路，用以偵測該輸出電容的一輸出電壓來產生一偵測訊號；以及一功率限制電路，用以依據該偵測訊號將該誤差放大器的一輸出電壓箝制在一特定範圍。充電電路用以根據該誤差放大器的該輸出電壓產生一充電訊號至該輸出 電路，以對該輸出電容充電。 An embodiment of the present invention discloses a voltage converter including an output circuit, an error amplifier and a charging control circuit. The output circuit includes an output capacitor. The charging control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier according to the detection signal within a specific range. The charging circuit is used for generating a charging signal to the output according to the output voltage of the error amplifier circuit to charge the output capacitor.

本發明一實施例揭露了一種D類放大器，包含一輸出電路、一誤差放大器以及一充電控制電路。輸出電路包含輸出電容。充電控制電路包含：一偵測電路，用以偵測該輸出電容的一輸出電壓來產生一偵測訊號；以及一功率限制電路，用以依據該偵測訊號將該誤差放大器的一輸出電壓箝制在一特定範圍。充電電路用以根據誤差放大器的輸出電壓產生一充電訊號至輸出電路，以對該輸出電容充電。 An embodiment of the present invention discloses a class D amplifier including an output circuit, an error amplifier and a charging control circuit. The output circuit contains an output capacitor. The charging control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier according to the detection signal within a specific range. The charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier to charge the output capacitor.

根據前述實施例，本發明提供的電壓轉換器可以在不直接下拉輸出電壓的情況下補償漏電流問題，從而可以在補償輸出電容的漏電流的同時避免迴路的異常。 According to the foregoing embodiments, the voltage converter provided by the present invention can compensate for the leakage current problem without directly pulling down the output voltage, so as to avoid loop abnormality while compensating for the leakage current of the output capacitor.

100:電壓轉換器 100: Voltage Converter

101:誤差放大器 101: Error Amplifier

103:充電控制電路 103: Charging control circuit

105:充電電路 105: Charging circuit

107:偵測電路 107: Detection circuit

109:功率限制電路 109: Power limiting circuit

401:邏輯電路 401: Logic Circuit

BC_1、BC_2:自舉電路 BC_1, BC_2: Bootstrap circuit

C_1:輸出電容 C_1: output capacitor

C_1a，C_2a:電容 C_1a, C_2a: Capacitors

CC_1，CC_2:轉換電路 CC_1, CC_2: Conversion circuit

CM_1，CM_2:比較器 CM_1, CM_2: Comparator

DA_1，DA_2:差動放大器 DA_1, DA_2: Difference Amplifier

R_1i，R_2i，R_1f，R_2f:電阻 R_1i, R_2i, R_1f, R_2f: Resistors

OP_1:運算放大器 OP_1: Operational Amplifier

SD:肖特基二極體 SD: Schottky Diode

Pr_1a，Pr_1b，Pr_1c，Pr_2a，Pr_2b:預驅動器 Pr_1a, Pr_1b, Pr_1c, Pr_2a, Pr_2b: Pre-drivers

SW_1，SW_2:開關 SW_1, SW_2: switch

第1圖繪示了根據本發明一實施例的電壓轉換器的方塊圖。 FIG. 1 shows a block diagram of a voltage converter according to an embodiment of the present invention.

第2圖繪示了根據本發明一實施例的，第1圖中所示的電壓轉換器的詳細結構的電路圖。 FIG. 2 is a circuit diagram illustrating a detailed structure of the voltage converter shown in FIG. 1 according to an embodiment of the present invention.

第3圖繪示了根據本發明一實施例的，第1圖和第2圖中所示的輸出電路的詳細結構的電路圖。 FIG. 3 is a circuit diagram illustrating a detailed structure of the output circuit shown in FIGS. 1 and 2 according to an embodiment of the present invention.

第4圖繪示了根據本發明一實施例的，第1圖和第2圖中所示的偵測電路的詳細結構的電路圖。 FIG. 4 is a circuit diagram illustrating a detailed structure of the detection circuit shown in FIGS. 1 and 2 according to an embodiment of the present invention.

第5圖和第6圖繪示了根據本發明一實施例的，第1圖和第2圖中所示的電路的動作示意圖。 FIGS. 5 and 6 are schematic diagrams illustrating the operation of the circuit shown in FIGS. 1 and 2 according to an embodiment of the present invention.

以下將以多個實施例來描述本發明的內容，還請留意，以下描述中的”第一”、”第二”以及類似描述僅用來定義不同的元件、參數、資料、訊號或步驟。並非用以限定其次序。 The content of the present invention will be described below with several embodiments. Please also note that the "first", "second" and similar descriptions in the following description are only used to define different elements, parameters, data, signals or steps. It is not intended to limit its order.

第1圖繪示了根據本發明一實施例的電壓轉換器的方塊圖。如第1圖所示，電壓轉換器100包含誤差放大器101，充電控制電路103，充電電路105和自舉電路BC_1，BC_2。充電控制電路103還包含偵測電路107和功率限制電路109。請注意，在以下實施例中，電壓轉換器100是差動輸入/輸出電路，因此具有兩個自舉電路BC_1，BC_2。然而，電壓轉換器100可以是單一輸入/輸出電路。在這種情況下，電壓轉換器100可以僅具有一個自舉電路，並且可以相應地改變其他電路結構。另外，在以下描述中，為了便於說明，僅繪示了電壓轉換器100的其中一路徑的動作。 FIG. 1 shows a block diagram of a voltage converter according to an embodiment of the present invention. As shown in FIG. 1, the voltage converter 100 includes an error amplifier 101, a charging control circuit 103, a charging circuit 105, and bootstrap circuits BC_1, BC_2. The charging control circuit 103 further includes a detection circuit 107 and a power limiting circuit 109 . Please note that in the following embodiments, the voltage converter 100 is a differential input/output circuit and thus has two bootstrap circuits BC_1, BC_2. However, the voltage converter 100 may be a single input/output circuit. In this case, the voltage converter 100 may have only one bootstrap circuit, and other circuit structures may be changed accordingly. In addition, in the following description, for the convenience of explanation, only the operation of one path of the voltage converter 100 is shown.

自舉電路BC_1包含一輸出電容(第1圖中未示出)。偵測電路107用以偵測輸出電容的輸出電壓V_c1以產生偵測訊號DS。功率限制電路103用以根據偵測訊號DS將誤差放大器101的輸出電壓V_e1箝制到特定範圍。在一實施例中，特定範圍是特定電壓位準。充電電路105用以根據輸出電壓V_e1產生充電訊號CS_1，來對輸出電容充電。在一實施例中，功率限制電路109將輸出電壓V_e1箝制到特定範圍，使得充電電路105增加對輸出電容充電的頻率，從而可以增加輸出電容的電壓。 The bootstrap circuit BC_1 includes an output capacitor (not shown in FIG. 1 ). The detection circuit 107 is used for detecting the output voltage V_c1 of the output capacitor to generate the detection signal DS. The power limiting circuit 103 is used for clamping the output voltage V_e1 of the error amplifier 101 to a specific range according to the detection signal DS. In one embodiment, the specific range is a specific voltage level. The charging circuit 105 is used for generating the charging signal CS_1 according to the output voltage V_e1 to charge the output capacitor. In one embodiment, the power limiting circuit 109 clamps the output voltage V_e1 to a specific range, so that the charging circuit 105 increases the frequency of charging the output capacitor, thereby increasing the voltage of the output capacitor.

在一實施例中，電壓轉換器100可以作為D類放大器。在這種情況下，引導電路BC_1可以視為一輸出電路。 In one embodiment, the voltage converter 100 may function as a class D amplifier. In this case, the steering circuit BC_1 can be regarded as an output circuit.

在以下描述中，描述了電壓轉換器100的詳細電路。還請了解，這些電路僅為舉例，並不表示限縮本發明的範圍。具有相同功能的任何電路也應落入本發明的範圍內。 In the following description, the detailed circuit of the voltage converter 100 is described. Please also understand that these circuits are only examples and are not intended to limit the scope of the present invention. Any circuit with the same function should also fall within the scope of the present invention.

第2圖繪示了根據本發明一實施例的，第1圖中所示的電壓轉換器的 詳細結構的電路圖。如第2圖所示，誤差放大器101包含電阻R_1i，R_2i，電容C_1a，C_2a和運算放大器OP_1。而且，充電電路105是包含比較器CM_1，CM_2的PWM電路，比較器CM_1，CM_2分別包含用以接收三角波訊號Tr的負輸入端和用以接收來自輸出電壓V_e1的輸出的正輸入端。另外，功率限制電路109包含差動放大器DA_1，差動放大器DA_1包含：第一輸入端，用以接收輸出電壓V_e1；第二輸入端，用以接收參考電壓RV(即上述特定電壓位準)；第一輸出端，用以根據輸出電壓V_e1和參考電壓RV產生第一功率限制訊號P_1；第二輸出端，用以根據輸出電壓V_e1和參考電壓RV產生第二功率限制訊號P_2。誤差放大器101接收第一功率限制訊號P_1和第二功率限制訊號P_2以產生輸出電壓V_e1。在一實施例中，運算放大器OP_1的負輸入端接收第二功率限制訊號P_2，運算放大器OP_1的正輸入端接收第一功率限制訊號P_1。 FIG. 2 illustrates the voltage converter shown in FIG. 1 according to an embodiment of the present invention. Circuit diagram of the detailed structure. As shown in FIG. 2, the error amplifier 101 includes resistors R_1i, R_2i, capacitors C_1a, C_2a and an operational amplifier OP_1. Moreover, the charging circuit 105 is a PWM circuit including comparators CM_1 and CM_2. The comparators CM_1 and CM_2 respectively include a negative input terminal for receiving the triangular wave signal Tr and a positive input terminal for receiving the output from the output voltage V_e1. In addition, the power limiting circuit 109 includes a differential amplifier DA_1, and the differential amplifier DA_1 includes: a first input terminal for receiving the output voltage V_e1; a second input terminal for receiving the reference voltage RV (ie, the above-mentioned specific voltage level); The first output terminal is used for generating the first power limiting signal P_1 according to the output voltage V_e1 and the reference voltage RV; the second output terminal is used for generating the second power limiting signal P_2 according to the output voltage V_e1 and the reference voltage RV. The error amplifier 101 receives the first power limit signal P_1 and the second power limit signal P_2 to generate the output voltage V_e1. In one embodiment, the negative input terminal of the operational amplifier OP_1 receives the second power limit signal P_2, and the positive input terminal of the operational amplifier OP_1 receives the first power limit signal P_1.

第3圖繪示了根據本發明一實施例的，第1圖和第2圖中所示的輸出電路的詳細結構的電路圖。另外，第4圖繪示了根據本發明一實施例的，第1圖和第2圖中所示的偵測電路的詳細結構的電路圖。為了更清楚地理解本發明的內容，請同時參照第2圖和第3圖或第4圖。 FIG. 3 is a circuit diagram illustrating a detailed structure of the output circuit shown in FIGS. 1 and 2 according to an embodiment of the present invention. In addition, FIG. 4 is a circuit diagram illustrating a detailed structure of the detection circuit shown in FIGS. 1 and 2 according to an embodiment of the present invention. For a clearer understanding of the content of the present invention, please refer to Figure 2 and Figure 3 or Figure 4 at the same time.

如第3圖所示，自舉電路BC_1包含輸出電容C_1(即上述輸出電容)，開關SW_1，SW_2，預驅動器Pr_1a，Pr_1b，Pr_1c，Pr_2a，Pr_2b和肖特基二極體SD。自舉電路BC_1操作在工作電壓V_op，並接收充電訊號CS_1，以控制開關SW_1和SW_2開啟(即，導通)或關閉(即，不導通)。開關SW_1以及預驅動器Pr_1a，Pr_1b，Pr_1c形成上橋路徑。此外，開關SW_2以及預驅動器Pr_2a，Pr_2b形成下橋路徑。如上所述，充電訊號CS_1可以是PWM訊號。因此，在第3圖的實施例中，如果充電訊號CS_1具有低邏輯值，下橋路徑被開啟(即，開關SW_2被開啟)且上橋路徑被關閉(即，開關SW_1被關閉)以對輸出電容C_1充電。相反的，如果充電訊號CS_1具有高邏輯值，則上橋路徑被開啟而下橋路徑被關閉，使得輸出 電容C_1不被充電且Vp_1被升壓。當輸出電容C_1充電時，其可能會漏電，因此其電壓可能會下降。 As shown in FIG. 3, the bootstrap circuit BC_1 includes an output capacitor C_1 (ie, the above-mentioned output capacitor), switches SW_1, SW_2, pre-drivers Pr_1a, Pr_1b, Pr_1c, Pr_2a, Pr_2b, and Schottky diodes SD. The bootstrap circuit BC_1 operates at the operating voltage V_op and receives the charging signal CS_1 to control the switches SW_1 and SW_2 to be turned on (ie, turned on) or turned off (ie, not turned on). The switch SW_1 and the pre-drivers Pr_1a, Pr_1b, and Pr_1c form an upper bridge path. In addition, the switch SW_2 and the pre-drivers Pr_2a, Pr_2b form a lower bridge path. As mentioned above, the charging signal CS_1 can be a PWM signal. Therefore, in the embodiment of FIG. 3, if the charging signal CS_1 has a low logic value, the lower path is turned on (ie, the switch SW_2 is turned on) and the upper path is turned off (ie, the switch SW_1 is turned off) to output Capacitor C_1 is charged. Conversely, if the charging signal CS_1 has a high logic value, the upper path is turned on and the lower path is turned off, so that the output Capacitor C_1 is not charged and Vp_1 is boosted. When the output capacitor C_1 is charged, it may leak, so its voltage may drop.

請參考第4圖，偵測電路107包含比較器CM_d，比較器CM_d用以比較輸出電容C_1的兩端電壓(即，第3圖中的輸出電壓V_c1和電壓V_p1)以及差異臨界值電壓V_dt。而且，偵測電路107包含邏輯電路401(例如，或閘)，其用以根據比較器CM_d的輸出來產生偵測訊號DS。更詳細來說，第4圖中的偵測電路107包含轉換電路CC_1，其用以將輸出電容C_1的兩端的電壓之間的電壓差轉換為電流。然後，電阻R_x根據電流產生電壓差。還請了解，偵測電路107不限於比較輸出電容C_1的兩端處的電壓以偵測輸出電容C_1是否有漏電。例如，偵測電路107可以將輸出電壓V_c1與標準電壓進行比較，並且當輸出電壓V_c1小於標準電壓時，判斷輸出電容C_1具有漏電。 Referring to FIG. 4 , the detection circuit 107 includes a comparator CM_d for comparing the voltage across the output capacitor C_1 (ie, the output voltage V_c1 and the voltage V_p1 in FIG. 3 ) and the difference threshold voltage V_dt. Furthermore, the detection circuit 107 includes a logic circuit 401 (eg, OR gate) for generating the detection signal DS according to the output of the comparator CM_d. In more detail, the detection circuit 107 in FIG. 4 includes a conversion circuit CC_1 for converting the voltage difference between the voltages across the output capacitor C_1 into a current. Then, the resistor R_x generates a voltage difference according to the current. Please also understand that the detection circuit 107 is not limited to comparing the voltages at both ends of the output capacitor C_1 to detect whether the output capacitor C_1 has leakage current. For example, the detection circuit 107 may compare the output voltage V_c1 with the standard voltage, and determine that the output capacitor C_1 has leakage when the output voltage V_c1 is less than the standard voltage.

第5圖和第6圖繪示了根據本發明一實施例的，第1圖和第2圖中所示的電路的動作示意圖。第5圖繪示了電容C_1兩端的電壓V_c1，充電訊號CS_1和充電電流I_c之間的關係。如第5圖所示，當電容C_1上的電壓V_c1大於臨界值電壓V_th且輸出電容C_1不被充電時，電壓轉換器100以通常模式操作。另外，為PWM訊號的充電訊號CS_1在通常模式下具有較高的佔空比(duty cycle，在這種情況下，佔空比為100%)。此外，當電容C_1兩端的電壓V_c1小於臨界值電壓V_th時，電壓轉換器100進入補償模式。在補償模式下，充電訊號CS_1具有較低的佔空比。當充電訊號CS_1具有低邏輯值時，會以充電電流I_c對輸出電容C_1充電。因此，電容C_1兩端的電壓V_c1在補償模式下會逐漸增加，直到大於臨界值電壓V_th。在一實施例中，臨界值電壓V_th被設定為0.5*V_op。 FIGS. 5 and 6 are schematic diagrams illustrating the operation of the circuit shown in FIGS. 1 and 2 according to an embodiment of the present invention. FIG. 5 shows the relationship between the voltage V_c1 across the capacitor C_1 , the charging signal CS_1 and the charging current I_c. As shown in FIG. 5 , when the voltage V_c1 on the capacitor C_1 is greater than the threshold voltage V_th and the output capacitor C_1 is not charged, the voltage converter 100 operates in the normal mode. In addition, the charging signal CS_1 which is the PWM signal has a relatively high duty cycle (in this case, the duty cycle is 100%) in the normal mode. In addition, when the voltage V_c1 across the capacitor C_1 is less than the threshold voltage V_th, the voltage converter 100 enters the compensation mode. In the compensation mode, the charging signal CS_1 has a lower duty cycle. When the charging signal CS_1 has a low logic value, the output capacitor C_1 is charged with the charging current I_c. Therefore, the voltage V_c1 across the capacitor C_1 will gradually increase in the compensation mode until it is greater than the threshold voltage V_th. In one embodiment, the threshold voltage V_th is set to 0.5*V_op.

第6圖繪示了電容C_1兩端的電壓V_c1，充電訊號CS_1，偵測訊號DS和誤差放大器101的輸出電壓V_e1之間的關係。如第6圖所示，在通常模式下，電容C_1兩端的電壓V_c1大於臨界值電壓V_th，因此充電訊號CS_1的佔空比較高， 而偵測訊號DS的邏輯值為低。而且，在通常模式下，誤差放大器101的輸出電壓V_e1未被抑制。此外，如果電容C_1兩端的電壓V_c1小於臨界值電壓V_th，則電壓轉換器100進入補償模式。在補償模式下，充電訊號CS_1具有較低的佔空比，而偵測訊號DS具有高邏輯值。而且，在補償模式下，誤差放大器101的輸出電壓V_e1被抑制到特定電壓位準V_sp，以減少充電訊號CS_1的佔空比。 FIG. 6 shows the relationship between the voltage V_c1 across the capacitor C_1 , the charging signal CS_1 , the detection signal DS and the output voltage V_e1 of the error amplifier 101 . As shown in FIG. 6, in the normal mode, the voltage V_c1 across the capacitor C_1 is greater than the threshold voltage V_th, so the duty ratio of the charging signal CS_1 is high, The logic value of the detection signal DS is low. Also, in the normal mode, the output voltage V_e1 of the error amplifier 101 is not suppressed. In addition, if the voltage V_c1 across the capacitor C_1 is less than the threshold voltage V_th, the voltage converter 100 enters the compensation mode. In the compensation mode, the charging signal CS_1 has a lower duty cycle, and the detection signal DS has a high logic value. Moreover, in the compensation mode, the output voltage V_e1 of the error amplifier 101 is suppressed to a specific voltage level V_sp to reduce the duty cycle of the charging signal CS_1.

在一實施例中，特定電壓位準V_sp由以下公式決定：

Figure 110100331-A0305-02-0008-1
In one embodiment, the specific voltage level V_sp is determined by the following formula:
Figure 110100331-A0305-02-0008-1

V_Ltri是三角波訊號Tr的底電壓(bottom voltage)，充電電路105使用該底電壓來產生PWM訊號。另外，V_Htri是三角波訊號Tr的頂電壓(upper voltage)。此外，在補償模式下，充電訊號CS的佔空比減小為小於D_max。在一實施例中，D_max為

Figure 110100331-A0305-02-0008-2
。 V_Ltri is the bottom voltage of the triangular wave signal Tr, and the charging circuit 105 uses the bottom voltage to generate the PWM signal. In addition, V_Htri is the upper voltage of the triangular wave signal Tr. In addition, in the compensation mode, the duty cycle of the charging signal CS is reduced to be smaller than D_max. In one embodiment, D_max is
Figure 110100331-A0305-02-0008-2
.

I_c是輸出電容C_1充電時輸出電容C_1的充電電流。在一實施例中，I_c等於第3圖中的肖特基二極體SD的順向電流。另外，I_d是輸出電容未充電時的放電電流。在一實施例中，I_d可以是肖特基二極體SD的漏電流，在轉換期間預驅動器Pr_1a，Pr_1b，Pr_1c的開關損耗電流或在第3圖中的節點V_p1處的接面漏電流。 I_c is the charging current of the output capacitor C_1 when the output capacitor C_1 is charged. In one embodiment, I_c is equal to the forward current of the Schottky diode SD in FIG. 3 . In addition, I_d is the discharge current when the output capacitor is not charged. In one embodiment, I_d may be the leakage current of the Schottky diode SD, the switching loss current of the pre-drivers Pr_1a, Pr_1b, Pr_1c during the transition or the junction leakage current at node V_p1 in FIG. 3 .

根據前述實施例，本發明提供的電壓轉換器可以在不直接下拉輸出電壓的情況下補償漏電流問題，從而可以在補償輸出電容的漏電流的同時避免迴路的異常。 According to the foregoing embodiments, the voltage converter provided by the present invention can compensate for the leakage current problem without directly pulling down the output voltage, so as to avoid loop abnormality while compensating for the leakage current of the output capacitor.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:電壓轉換器 100: Voltage Converter

101:誤差放大器 101: Error Amplifier

103:充電控制電路 103: Charging control circuit

105:充電電路 105: Charging circuit

107:偵測電路 107: Detection circuit

109:功率限制電路 109: Power limiting circuit

BC_1、BC_2:自舉電路 BC_1, BC_2: Bootstrap circuit

Claims (18)

一種電壓轉換器，包含：一輸出電路，包含一輸出電容；一誤差放大器：一充電控制電路，包含：一偵測電路，用以比較該輸出電容的一輸出電壓以及一差異臨界值電壓來產生一偵測訊號；以及一功率限制電路，用以接收該偵測訊號以及該誤差放大器的一輸出電壓，並依據該偵測訊號的一邏輯值改變該誤差放大器的輸入，以將該誤差放大器的該輸出電壓箝制在一特定範圍；以及一充電電路，用以根據該誤差放大器的該輸出電壓產生一充電訊號至該輸出電路，以對該輸出電容充電。 A voltage converter includes: an output circuit, including an output capacitor; an error amplifier; a charging control circuit, including: a detection circuit for comparing an output voltage of the output capacitor and a difference threshold voltage to generate a detection signal; and a power limiting circuit for receiving the detection signal and an output voltage of the error amplifier, and changing the input of the error amplifier according to a logic value of the detection signal, so as to reduce the error amplifier's output voltage The output voltage is clamped within a specific range; and a charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier to charge the output capacitor. 如請求項1所述的電壓轉換器，其中該功率限制電路將該誤差放大器的該輸出電壓箝制在該特定範圍，使得該充電電路增加對該輸出電容充電的頻率。 The voltage converter of claim 1, wherein the power limiting circuit clamps the output voltage of the error amplifier to the specific range, so that the charging circuit increases the frequency of charging the output capacitor. 如請求項1所述的電壓轉換器，其中該充電電路為PWM電路且該充電訊號為PWM訊號，其中該功率限制電路將該誤差放大器的該輸出電壓箝制在該特定範圍，使得該充電訊號的佔空比減少。 The voltage converter of claim 1, wherein the charging circuit is a PWM circuit and the charging signal is a PWM signal, wherein the power limiting circuit clamps the output voltage of the error amplifier within the specific range, so that the charging signal has a The duty cycle is reduced. 如請求項3所述的電壓轉換器，其中該佔空比被降低成少於
Figure 110100331-A0305-02-0010-3
，其中I_c為該輸出電容被充電時的充電電流，且I_d為該輸出電容未被充電時的放電電流。 The voltage converter of claim 3, wherein the duty cycle is reduced to less than
Figure 110100331-A0305-02-0010-3
, where I_c is the charging current when the output capacitor is charged, and I_d is the discharging current when the output capacitor is not charged. 如請求項3所述的電壓轉換器，其中該輸出電路包含一上橋路徑以及一下橋路徑；其中若該充電訊號具有一低邏輯值，該下橋路徑開啟以對該輸出電容充電，但該上橋路徑關閉；其中若該充電訊號具有一高邏輯值，該上橋路徑開啟但該下橋路徑關閉。 The voltage converter of claim 3, wherein the output circuit includes an upper bridge path and a lower bridge path; wherein if the charging signal has a low logic value, the lower bridge path is turned on to charge the output capacitor, but the The upper bridge path is turned off; wherein if the charging signal has a high logic value, the upper bridge path is turned on but the lower bridge path is turned off. 如請求項1所述的電壓轉換器，其中該功率限制電路包含：一差動放大器，包含：一第一輸入端，用以接收該誤差放大器的該輸出電壓；一第二輸入端，用以接收一參考電壓；一第一輸出端，用以根據該誤差放大器的該輸出電壓以及該參考電壓產生一第一功率限制訊號；一第二輸出端，用以根據該誤差放大器的該輸出電壓以及該參考電壓產生一第二功率限制訊號；其中該誤差放大器接收該第一功率限制訊號以及該第二功率限制訊號來產生該誤差放大器的該輸出電壓。 The voltage converter of claim 1, wherein the power limiting circuit comprises: a differential amplifier, comprising: a first input terminal for receiving the output voltage of the error amplifier; a second input terminal for receiving a reference voltage; a first output terminal for generating a first power limit signal according to the output voltage of the error amplifier and the reference voltage; a second output terminal for generating a first power limit signal according to the output voltage of the error amplifier and The reference voltage generates a second power limit signal; wherein the error amplifier receives the first power limit signal and the second power limit signal to generate the output voltage of the error amplifier. 如請求項6所述的電壓轉換器，其中該充電電路為包含至少一比較器的一PWM電路，其中該比較器接收該輸出電壓以及一三角波訊號來產生該充電訊號。 The voltage converter of claim 6, wherein the charging circuit is a PWM circuit including at least one comparator, wherein the comparator receives the output voltage and a triangular wave signal to generate the charging signal. 如請求項1所述的電壓轉換器，其中該偵測電路包含：一比較器，用以比較該輸出電容兩端的電壓與該差異臨界值電壓；以及 一邏輯電路，用以根據該比較器的一輸出產生該偵測訊號。 The voltage converter of claim 1, wherein the detection circuit comprises: a comparator for comparing the voltage across the output capacitor with the difference threshold voltage; and a logic circuit for generating the detection signal according to an output of the comparator. 如請求項1所述的電壓轉換器，其中該特定範圍為一特定電壓位準。 The voltage converter of claim 1, wherein the specific range is a specific voltage level. 一種D類放大器，包含：一輸出電路，包含一輸出電容；一誤差放大器：一充電控制電路，包含：一偵測電路，用以比較該輸出電容的一輸出電壓以及一差異臨界值電壓來產生一偵測訊號；以及一功率限制電路，用以接收該偵測訊號以及該誤差放大器的一輸出電壓，並依據該偵測訊號的一邏輯值改變該誤差放大器的輸入，以將該誤差放大器的該輸出電壓箝制在一特定範圍；以及一充電電路，用以根據該誤差放大器的該輸出電壓產生一充電訊號至該輸出電路，以對該輸出電容充電。 A class D amplifier, comprising: an output circuit, including an output capacitor; an error amplifier; a charge control circuit, including: a detection circuit for comparing an output voltage of the output capacitor and a difference threshold voltage to generate a detection signal; and a power limiting circuit for receiving the detection signal and an output voltage of the error amplifier, and changing the input of the error amplifier according to a logic value of the detection signal, so as to reduce the error amplifier's output voltage The output voltage is clamped within a specific range; and a charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier to charge the output capacitor. 如請求項10所述的D類放大器，其中該功率限制電路將該誤差放大器的該輸出電壓箝制在該特定範圍，使得該充電電路增加對該輸出電容充電的頻率。 The class D amplifier of claim 10, wherein the power limiting circuit clamps the output voltage of the error amplifier to the specific range, so that the charging circuit increases the frequency at which the output capacitor is charged. 如請求項10所述的D類放大器，其中該充電電路為PWM電路且該充電訊號為PWM訊號，其中該功率限制電路將該誤差放大器的該輸出電壓箝制在該特定範圍，使得該充電訊號的佔空比減少。 The class D amplifier of claim 10, wherein the charging circuit is a PWM circuit and the charging signal is a PWM signal, wherein the power limiting circuit clamps the output voltage of the error amplifier within the specific range, so that the charging signal has a The duty cycle is reduced. 如請求項12所述的D類放大器，其中該佔空比被降低成少於
Figure 110100331-A0305-02-0013-4
，其中I_c為該輸出電容被充電時的充電電流，且I_d為該輸出電容未被充電時的放電電流。 The class D amplifier of claim 12, wherein the duty cycle is reduced to less than
Figure 110100331-A0305-02-0013-4
, where I_c is the charging current when the output capacitor is charged, and I_d is the discharging current when the output capacitor is not charged. 如請求項12所述的D類放大器，其中該輸出電路包含一上橋路徑以及一下橋路徑；其中若該充電訊號具有一低邏輯值，該下橋路徑開啟以對該輸出電容充電，但該上橋路徑關閉；其中若該充電訊號具有一高邏輯值，該上橋路徑開啟但該下橋路徑關閉。 The class D amplifier of claim 12, wherein the output circuit includes an upper bridge path and a lower bridge path; wherein if the charging signal has a low logic value, the lower bridge path is turned on to charge the output capacitor, but the The upper bridge path is turned off; wherein if the charging signal has a high logic value, the upper bridge path is turned on but the lower bridge path is turned off. 如請求項10所述的D類放大器，其中該功率限制電路包含：一差動放大器，包含：一第一輸入端，用以接收該誤差放大器的該輸出電壓；一第二輸入端，用以接收一參考電壓；一第一輸出端，用以根據該誤差放大器的該輸出電壓以及該參考電壓產生一第一功率限制訊號；一第二輸出端，用以根據該誤差放大器的該輸出電壓以及該參考電壓產生一第二功率限制訊號；其中該誤差放大器接收該第一功率限制訊號以及該第二功率限制訊號來產生該誤差放大器的該輸出電壓。 The class D amplifier of claim 10, wherein the power limiting circuit comprises: a differential amplifier, comprising: a first input terminal for receiving the output voltage of the error amplifier; a second input terminal for receiving a reference voltage; a first output terminal for generating a first power limit signal according to the output voltage of the error amplifier and the reference voltage; a second output terminal for generating a first power limit signal according to the output voltage of the error amplifier and The reference voltage generates a second power limit signal; wherein the error amplifier receives the first power limit signal and the second power limit signal to generate the output voltage of the error amplifier. 如請求項15所述的D類放大器，其中該充電電路為包含至少一比較器的一PWM電路，其中該比較器接收該輸出電壓以及一三角波訊號來產生該充電訊號。 The class D amplifier of claim 15, wherein the charging circuit is a PWM circuit including at least one comparator, wherein the comparator receives the output voltage and a triangular wave signal to generate the charging signal. 如請求項10所述的D類放大器，其中該偵測電路包含：一比較器，用以比較該輸出電容兩端的電壓與該差異臨界值電壓；以及一邏輯電路，用以根據該比較器的一輸出產生該偵測訊號。 The class D amplifier of claim 10, wherein the detection circuit comprises: a comparator for comparing the voltage across the output capacitor with the difference threshold voltage; and a logic circuit for comparing the voltage across the output capacitor with the difference threshold voltage; An output generates the detection signal. 如請求項10所述的D類放大器，其中該特定範圍為一特定電壓位準。 The class D amplifier of claim 10, wherein the specific range is a specific voltage level.
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CN104485806A (en) * 2014-11-08 2015-04-01 成都芯源系统有限公司 Bootstrap voltage refresh control circuit, voltage conversion circuit and control method thereof
CN106712501A (en) * 2015-07-17 2017-05-24 三垦电气株式会社 Voltage conversion control circuit and voltage converter
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