TWI450483B - Dc-dc converter and voltage conversion method thereof - Google Patents

Description

DC to DC converter and voltage conversion method thereof

The present invention relates to a DC-to-DC converter, and more particularly to a DC-to-DC converter that can adjust the pulse width of a pulse width modulated signal.

As is known, a DC-to-DC converter converts a DC input voltage into a DC output voltage of a different magnitude. The operating voltages of the central processing unit (CPU), dynamic random access memory (DRAM), graphics chip, and chip set in the computer system are different, so many computer systems are required. The DC to DC converter is used to convert the DC input voltage (eg, 19V) provided by the power supply into the operating voltage required for each component.

In a typical DC-to-DC converter, a pulse width modulation (PWM) signal is usually used as a driving signal. Higher frequency pulse width modulation can achieve higher power density, but it will increase the loss of conversion power. Therefore, this type of driving is usually only suitable for heavy-duty applications, but it is less efficient in light-load applications because most of the power is consumed by switches in the DC-to-DC converter rather than by the load. Therefore, there is a long-felt need for a DC-to-DC converter, which is expected to be elastically adjusted as the load changes, not only in high load applications, but also in conversion efficiency in light load applications. .

The invention provides a DC-to-DC converter, which can make the load of the DC-DC converter have a good conversion efficiency when the load is light.

The invention provides a DC-to-DC converter suitable for providing an output voltage to a load, and the DC-to-DC converter comprises a control module and an output module. The control module receives the first pulse width modulation signal and the load indication signal to output a second pulse width modulation signal, wherein the first pulse width modulation signal has a first preset pulse width. When the load indication signal indicates that the load is a heavy load, the control module outputs the first pulse width modulation signal as the second pulse width modulation signal. When the load indication signal indicates that the load is a light load, the control module outputs a second pulse width modulation signal having a second preset pulse width. The output module is coupled to the control module, and provides an output voltage according to the second pulse width modulation signal, wherein the second preset pulse width is greater than the first preset pulse width.

In an embodiment of the invention, the DC-to-DC converter further includes a current detecting unit for detecting a load current of the output module to provide a load indicating signal.

In an embodiment of the invention, the control module includes a first reverse gate, a first gate, a second gate, a fixed on-time unit, and an OR gate. The input of the first reverse gate receives the load indication signal. The first and the gate inputs receive the first pulse width modulation signal and the load indication signal. The input end of the second AND gate receives the output signal of the first pulse width modulation signal and the first reverse gate. The fixed on-time unit is coupled to the output end of the second gate. When the output signal of the second gate is rising, the fixed on-time unit outputs a fixed on-time signal according to the output signal of the second gate, wherein the fixed on-time is fixed. The pulse width of the signal is equal to the second predetermined pulse width. The input end of the gate is coupled to the output end of the first gate and the on-time control unit, and outputs a second pulse width modulation signal according to the output result of the first gate and the fixed on-time signal.

In an embodiment of the invention, the fixed on-time unit includes a second reverse gate, a third reverse gate, a fourth reverse gate, a third gate, and a fifth reverse gate. The input end of the second reverse gate is coupled to the output end of the second gate. The input end of the third reverse gate is coupled to the output end of the second reverse gate. The input end of the fourth reverse gate is coupled to the output end of the third reverse gate. The input end of the third and the gate is coupled to the output end of the third reverse gate and the output end of the second gate. The input end of the fifth reverse gate is coupled to the output end of the third gate. The output of the fifth reverse gate is coupled to the input of the gate.

In an embodiment of the invention, the fixed on-time unit includes a D-type flip-flop, a sixth reverse gate, a third transistor, a current source, a capacitor, a seventh reverse gate, and an eighth reverse gate. The data input end of the D-type flip-flop is coupled to an operating voltage, the clock input end of the D-type flip-flop is coupled to the output end of the second gate, and the reset terminal R of the D-type flip-flop is coupled to the first comparison. At the output of the device, the data output end of the D-type flip-flop is coupled to the input of the gate. The input end of the sixth reverse gate is coupled to the data output end of the D-type flip-flop. The gate of the third transistor is coupled to the output of the sixth reverse gate, and the source of the third transistor is coupled to the ground voltage. The current source is coupled to the drain of the third transistor. The capacitor is coupled to the drain of the third transistor. The input end of the seventh reverse gate is coupled to the drain of the third transistor. The input end of the eighth reverse gate is coupled to the output end of the seventh reverse gate, and the output end of the eighth reverse gate is coupled to the reset end R of the D-type flip-flop.

In an embodiment of the invention, the DC-DC converter further includes a voltage dividing impedance unit and a pulse width modulation signal generating module. The voltage dividing impedance unit is coupled between the output of the DC-DC converter and the ground voltage. The pulse width modulation signal generating module is coupled to the current detecting unit, the control module and the voltage dividing impedance unit, and generates a first pulse width modulation signal according to a reference voltage, a load indicating signal and a partial voltage of the output voltage.

In an embodiment of the invention, the pulse width modulation signal generating module includes an error amplifier, a compensation unit, a ramp generator, and a second comparator. The positive and negative input terminals of the error amplifier are respectively coupled to the reference voltage and the voltage dividing impedance unit, and generate an error signal according to the voltage division of the reference voltage and the output voltage. The compensation unit is coupled to the output of the error amplifier for compensating for the error signal. The ramp generator is coupled to the current detecting unit to generate a ramp signal according to the load indicating signal and the one clock signal. The positive and negative input ends of the second comparator are respectively coupled to the output end of the error amplifier and the ramp generator, and the first pulse width modulation signal is generated according to the comparison between the error signal and the ramp signal.

The invention also proposes a voltage conversion method suitable for a DC-to-DC converter. The DC-DC converter is adapted to provide an output voltage to a load. The voltage conversion method comprises the following steps. A load current of the DC to DC converter is detected to provide a load indication signal. Receiving a first pulse width modulation signal and a load indication signal to output a second pulse width modulation signal, wherein the first pulse width modulation signal has a first predetermined pulse width. According to the load indication signal, the load of the DC-to-DC converter output is determined to be light load or heavy load. If the output of the DC-to-DC converter is lightly loaded, a pulse width modulation signal having a second predetermined pulse width is output to switch the input voltage and the ground voltage. If the output of the DC-to-DC converter is a heavy load, the first pulse width modulation signal is output as the second pulse width modulation signal. The output voltage is provided according to the second pulse width modulation signal. The second predetermined pulse width is greater than the first predetermined pulse width.

In an embodiment of the invention, the output voltage is pulled high when the pulse width modulation signal has a rising edge, and the output voltage is decreased when the second pulse width modulation signal has a falling edge.

Based on the above, the present invention outputs a second pulse width modulation signal having a predetermined pulse width when the load of the DC-DC converter is lightly loaded, so that the DC-DC converter still has a light load when its load is Can maintain good conversion efficiency.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1 is a schematic diagram of a DC-to-DC converter according to an embodiment of the invention. Referring to FIG. 1 , the DC-to-DC converter 100 includes a control module 102 and an output module 104 . The output module 104 is coupled to the control module 102 , the input voltage Vin of the DC-DC converter 100 , the ground voltage GND , and the output of the DC-DC converter 100 and the load 106 .

The control module 102 is configured to receive the first pulse width modulation signal PWM1 and the load indication signal SC1, and output a second pulse width modulation signal PWM2, wherein the first pulse width modulation signal PWM1 has a first preset pulse width. When the load indication signal SC1 indicates that the load 106 is a heavy load, the control module 102 directly outputs the first pulse width modulation signal PWM1 as the second pulse width modulation signal PWM2 to the output module 104. The output module 104 then reacts the second pulse width modulation signal PWM2 to provide an output voltage Vout to achieve a good conversion efficiency of the DC to DC converter 100.

When the load indication signal SC1 indicates that the load 106 is a light load, the control module 102 outputs a second pulse width modulation signal PWM2 having a second preset pulse width to ensure that the conversion efficiency of the DC-DC converter 100 is not lightly loaded. The second preset pulse width is greater than the first preset pulse width. Thus, by providing corresponding pulse width modulation signals (PWM1, PWM2) when the load 106 is heavily loaded and lightly loaded, the conversion efficiency of the DC-DC converter 100 can be affected by the weight of the load 106, and continues. Supply good power quality to the system circuitry of the latter stage.

2 is a schematic diagram of a DC-to-DC converter according to another embodiment of the present invention. Referring to FIG. 2, in the embodiment, the first pulse width modulation signal PWM1 of the embodiment of FIG. 1 can be generated by using the pulse width modulation signal generating module 202 and the voltage dividing impedance unit 204 shown in FIG. The pulse width modulation signal generating module 202 is coupled to the control module 102 and the voltage dividing impedance unit 204, and the voltage dividing impedance unit 204 is coupled between the output voltage Vout and the ground voltage GND.

The output module 104 includes an inductor L1, a driving unit 208, and a switching unit 210. The first end and the second end of the inductor L1 are respectively coupled to the output end of the DC-DC converter 200 and the switching unit 210. The switching unit 210 is coupled to the second end of the inductor L1, the input voltage Vin, and the ground voltage GND. The driving unit 208 is coupled to the control module 102 and the switching unit 210. The pulse width modulation signal generation module 202 generates the first pulse width modulation signal PWM1 according to the reference voltage Vref, the voltage IL on the inductor L1 and the voltage division of the output voltage Vout. The driving unit 208 outputs the first switching signal UG1 and the second switching signal LG1 to the switching unit 210 according to the second pulse width modulation signal PWM2 to control the switching unit 210 to switch the output input voltage Vin or the ground voltage GND to output a pulse signal P1. To the inductor L1, the input voltage Vin is converted into the output voltage Vout by the switching of the corresponding switching unit 210.

The difference between the embodiment of FIG. 2 and the embodiment of FIG. 1 is that the DC-to-DC converter 200 of the embodiment of FIG. 2 further includes a current detecting unit 206, in addition to the pulse width modulation signal generating module 202 and the voltage dividing impedance unit 204. The output of the switching unit 210, the pulse width modulation signal generating module 202, the driving unit 208, and the control module 102 are coupled. The current detecting unit 206 is configured to detect a load current of the DC-to-DC converter 200 to provide a load indication signal SC1. In detail, as shown in FIG. 2, the current detecting unit 206 detects the load current at the output end of the switching unit 210 (that is, the current IL on the inductor L1), and outputs according to the detected current IL of the inductor L1. The load indication signal SC1. The pulse width modulation signal generating module 202 can generate the first pulse width modulation signal PWM1 according to the load indication signal SC1, and enable the control module 102 to determine the load 106 of the output end of the DC to DC converter 200 according to the load indication signal SC1. For light load or heavy load, it is determined to output the first pulse width modulation signal PWM1 or the second pulse width modulation signal PWM2. The load 106 is a light load or a heavy load, for example, by comparing the magnitude between the current IL and a preset current value. When the current value of the current IL is less than the preset current value, it is determined that the load 106 is a light load, and when the current is When the current value of IL is greater than the preset current value, it is determined that the load 106 is a heavy load. In addition, the driving unit 208 can also control the switching state of the switching unit 210 according to the load indication signal SC1.

In detail, a further implementation circuit diagram of the DC-to-DC converter 200 of FIG. 2 can be as shown in FIG. 3 is a schematic diagram of a DC-to-DC converter according to another embodiment of the present invention. In the present embodiment, the pulse width modulation signal generation module 202 includes an error amplifier 302, a compensation unit 306, a ramp generator 308, and a comparator 304. The positive and negative input terminals of the error amplifier 302 are respectively coupled to the reference voltage Vref and the voltage dividing impedance unit 204 to generate an error signal ER1 according to the voltage division of the reference voltage Vref and the output voltage Vout. In the present embodiment, the voltage dividing impedance unit 204 includes two resistors RA and RB connected in series between the output terminal of the DC-DC converter 200 and the ground voltage GND. The error amplifier 302 is based on the reference voltage Vref and the output voltage Vout. The partial pressure produces an error signal ER1.

The compensation unit 306 is coupled to the output of the error amplifier 302. In this embodiment, the compensation unit 306 includes a resistor R1, a capacitor CA, and a capacitor CB. The resistor R1 is connected in series with the capacitor CA, and then in parallel with the capacitor CB. Limited. In addition, the positive and negative inputs of the comparator 304 are coupled to the output of the error amplifier 302 and the ramp generator 308, respectively. The compensation unit 306 is configured to compensate the error signal ER1. The ramp generator 308 generates the ramp signal ramp1 according to the clock signal CLK and the load indication signal SC1. After the compensation unit 306 completes the compensation of the error signal Vref, the comparator 304 compares the error signal ER1 with the ramp signal ramp1 provided by the ramp generator 308 to generate the first pulse width modulation signal PWM1. The waveforms of the error signal ER1, the ramp signal ramp1 and the first pulse width modulation signal PWM1 can be as shown in FIG.

In addition, in the embodiment, the control module 102 includes a first reverse gate INV1, a first AND gate AND1, a second AND gate AND2, a fixed on-time unit 310, and an OR gate OR1. The input end of the first reverse gate INV1 is coupled to the current detecting unit 206 to receive the load indicating signal SC1. The input end of the second AND gate AND2 is coupled to the output end of the first reverse gate INV1 and the output end of the comparator 304, and the output end of the second AND gate AND2 is coupled to the fixed on-time unit 310. The input end of the first AND gate AND1 is coupled to the output of the current detecting unit 206 and the comparator 304 to receive the load indicating signal SC1 and the first pulse width modulated signal PWM1, respectively. The input end of the OR gate OR1 is coupled to the output end of the first AND gate AND1 and the fixed ON time unit 310, or the output end of the gate OR1 is coupled to the driving unit 208.

In addition, the switching unit 210 is implemented by the first transistor M1 and the second transistor M2 in this embodiment. The first transistor M1 and the second transistor M2 are connected in series between the input voltage Vin of the DC-DC converter 200 and the ground voltage GND, and the gates of the first transistor M1 and the second transistor M2 are coupled to the driving unit 208. The first switching signal UG1 and the second switching signal LG1 are respectively received, and the common contact of the first transistor M1 and the second transistor M2 is coupled to the inductor L1.

The details of the operation of the DC-DC converter 200 under heavy load and light load will be described below with reference to FIGS. 3 and 4. Referring to FIG. 3 and FIG. 4 simultaneously, as shown in FIG. 4, when the current detecting unit 206 determines that the load 106 is a heavy load according to the detected current IL on the inductor L1, the current detecting unit 206 outputs high voltage logic. The load indicator of the level indicates the signal SC1. After the high voltage logic level load indication signal SC1 is inverted by the first reverse gate INV1, the output of the second AND gate AND2 is made to a low voltage logic level, thereby causing the fixed on time unit 310 to be disabled, and the control mode is disabled. The second pulse width modulation signal PWM2 output by the group 102 loses its influence.

At the same time, the load indicating signal SC1 will cause the ramp generator 308 to operate at a fixed frequency, i.e., the ramp signal ramp1 generated by the ramp generator 308 will have a fixed frequency. The first pulse width modulation signal PWM1 outputted by the comparator 304 is controlled by the ramp signal ramp1 outputted by the ramp generator 308, and the load indication signal SC1 is output to the first AND gate AND1. AND1 and OR gate OR1 are transmitted to drive unit 208. The driving unit 208 outputs the first switching signal UG1 and the second switching signal LG1 according to the first pulse width modulation signal PWM1 and the load indication signal SC1 to respectively control the conduction states of the first transistor M1 and the second transistor M2, and further The output voltage Vout of the DC-to-DC converter 200 is controlled.

The result of comparing the ramp signal ramp1 with the error signal ER1 by the comparator 304 determines the pulse width of the first pulse width modulation signal PWM1. As can be seen from FIG. 4, when the second pulse width modulation signal PWM2 is at a high voltage logic level, the driving unit sets the first switching signal UG1 to a high voltage logic level according to the second pulse width modulation signal, and The second switching signal LG1 is set to a low voltage logic level, that is, the first transistor M1 is set to an on state, and the second transistor M2 is set to a off state. In addition, when the current IL on the inductor L1 falls to a relatively low level, the driving unit 208 sets the second switching signal LG1 to a low voltage logic level according to the load indication signal SC1 to turn off the second transistor M2.

When the current detecting unit 206 determines that the load 106 is a light load according to the detected current on the inductor L1, the load indicating signal SC1 output by the current detecting unit 206 will be changed from the high voltage logic level to the low voltage logic level. . After the low voltage logic level load indicating signal SC1 is inverted by the first reverse gate INV1, the output of the second AND gate AND2 is made to be a high voltage logic level, thereby enabling the fixed on time unit 310. At the same time, the load indication signal SC1 of the low voltage logic level will cause the output of the first AND gate AND1 to be a low voltage logic level, and the first pulse width modulation signal PWM1 output by the comparator 304 is output to the control module 102. The second pulse width modulation signal PWM2 loses its influence.

As shown in FIG. 4, when the load 106 is a light load, the ramp signal ramp1 and the error signal ER1 are respectively affected by the change of the output voltage Vout and the load indication signal SC1, and the waveform is converted to the waveform shown on the right side of FIG. The frequency of the signal ramp1 and the error signal ER1 is significantly reduced. Since the output of the first AND gate AND1 is a low voltage logic level, the second pulse width modulation signal PWM2 will be completely determined by the output of the fixed on time unit 310. When the comparator 304 generates a rising edge according to the ramp signal ramp1 and the first pulse width modulation signal PWM1 outputted by the error signal ER1, the fixed on-time unit 310 outputs a fixed on-time signal Son1 according to the output signal of the second AND gate AND2. Further, it is output to the driving unit 208 as the second pulse width modulation signal PWM2 through the OR gate OR1. The pulse width of the fixed on-time signal Son1 (ie, the second pulse width modulation signal PWM2) is equal to the second predetermined pulse width described above, which is greater than the pulse width of the first pulse width modulation signal PWM1 in this embodiment.

While the second pulse width modulation signal PWM2 is maintained at the high voltage logic level, the ramp signal ramp1 will also be maintained at a specific voltage level, and the second pulse width modulation signal PWM2 is converted to the low voltage logic. After the level is lowered, it gradually drops to a lower voltage level. In addition, due to the widening of the second pulse width modulation signal PWM2, the pulse widths of the first switching signal UG1 and the second switching signal LG1 output by the driving unit 208 are also widened. When the current on the inductor L1 drops to zero, the driving unit 208 will turn off the second transistor M2 according to the load indicating signal SC1. Thus, by fixing the on-time unit 310 to convert the pulse width of the second pulse width modulation signal PWM2 to the second predetermined pulse width according to the light weight of the load 106, the DC pair can be maintained under the condition that the load 106 is lightly loaded. The conversion efficiency of the DC converter 200, in turn, supplies good power quality to the application circuit of the subsequent stage.

In detail, an embodiment of the fixed on-time unit 310 can be, for example, as shown in FIG. 5A or FIG. 5B. In FIG. 5A, the fixed on-time unit 310 includes a second reverse gate INV2, a third reverse gate INV3, a fourth reverse gate INV4, a reverse gate NAND1, and a fifth reverse gate INV5. The second reverse gate INV2~the fourth reverse gate INV4 are connected in series between the output end of the second AND gate AND2 and one input end of the reverse gate NAND1, and the other input end of the gate NAND1 is coupled to the second gate The output of AND2. In addition, the output end of the NAND gate NAND1 is coupled to the input end of the fifth reverse gate INV5, and the output end of the fifth reverse gate INV5 is coupled to the input terminal of the OR gate OR1. Thus, by utilizing the characteristic that the signal generates a time delay through the logic gate, the pulse width of the input signal of the fixed on-time unit 310 is widened, and the fixed on-time signal Son1 having the second preset width is output.

It should be noted that the number of serially connected logic gates in FIG. 5A is only an exemplary embodiment, and the actual application is not limited thereto. The fixed on-time unit 310 widens the amplitude of the pulse width of the input signal according to the actual application situation. For example, the number of reverse gates connected in series with the input terminal of the NAND1 gate can be increased to 5 or 7 to increase the fixed Turn on the pulse width of the time signal Son1.

FIG. 5B is a schematic diagram of a fixed on-time unit according to another embodiment of the present invention. Please refer to FIG. 5B. In the present embodiment, the fixed on-time unit 310 includes a D-type flip-flop 502, a sixth reverse gate INV6, a third transistor M3, a current source I1, a capacitor C1, a seventh reverse gate INV7, and an eighth reverse gate INV8. The data input terminal D of the D-type flip-flop 502 is coupled to an operating voltage VOP1, and the clock input terminal of the D-type flip-flop 502 is coupled to the output terminal of the second AND gate AND2, and the data output terminal of the D-type flip-flop 502 The Q is coupled to the input of the OR gate OR1 and the input of the sixth reverse gate INV6. The gate of the third transistor M3 is coupled to the output end of the sixth inverter INV6, and the drain and the source of the third transistor M3 are coupled to the current source I1 and the ground voltage GND, respectively. The capacitor C1 is coupled between the drain of the third transistor M3 and the ground voltage GND. The input end of the seventh reverse gate INV7 is coupled to the drain of the third transistor M3, and the output end of the seventh reverse gate INV7 is coupled to the input end of the eighth reverse gate INV8. In addition, the output end of the eighth reverse gate INV8 is coupled to the reset terminal R of the D-type flip-flop 502.

As shown in FIG. 5B, when the rising edge of the first pulse width modulation signal PWM1 occurs, the output of the second AND gate AND2 is turned into a high voltage logic potential, so that the D-type flip-flop 502 inputs its data input terminal D. The voltage is output to its data output terminal Q, and the fixed on-time signal Son1 is turned into a high-voltage logic potential (also causes the second pulse-width modulation signal PWM2 to be converted to a high-voltage logic potential). After the high-voltage logic potential fixed on-time signal Son1 is inverted by the sixth reverse gate INV6, the third transistor M3 is turned off, so that the voltage on the capacitor C1 starts to be charged by the current source I1 and gradually rises. The voltage on capacitor C1 will be transferred to reset terminal R of D-type flip-flop 502 via seventh back gate INV7 and eighth back gate INV8, and the voltage on capacitor C1 is charged to a high voltage logic level and passed to When the reset terminal R of the D-type flip-flop 502 is pulled, the data output terminal Q of the D-type flip-flop 502 is pulled to the low-voltage logic level. The self-capacitance C1 is charged until the reset terminal R of the D-type flip-flop 502 is turned to the high-voltage logic level, and the fixed on-time signal Son1 is maintained at the high-voltage logic potential, thereby making the fixed on-time signal Son1 ( The pulse width of the second pulse width modulation signal PWM2) is also widened. The user can adjust the pulse width of the second pulse width modulation signal PWM2 by changing the size of the capacitor C1 or the number of series connection of the reverse gate according to actual conditions. For example, the capacitance of the capacitor C1 can be increased or the number of serial connections of the reverse gate can be increased to increase the pulse width of the second pulse width modulation signal PWM2.

Additionally, embodiments of current detecting unit 206 may be, for example, as shown in FIG. 6A or FIG. 6B. In FIG. 6A, the current detecting unit 206 is coupled to a common contact of the first transistor M1 and the second transistor M2 and an output of the DC-to-DC converter 200. The current detecting unit 206 includes a resistor Rf1, a resistor Rf2, a capacitor Cf, and an operational amplifier 602. In addition, the resistor RL1 coupled between the inductor L1 and the output of the DC-DC converter 200 in FIG. 6A is the equivalent series resistance of the inductor L1. The resistor Rf1 is coupled between the positive input terminal of the operational amplifier 602 and a common junction of the first transistor M1 and the second transistor M2. The resistor Rf2 is coupled between the negative input terminal of the operational amplifier 602 and the output of the DC-DC converter 200. The negative input of the operational amplifier 602 is coupled to its output. The capacitor Cf is coupled between the positive input terminal of the operational amplifier 602 and the output of the DC-to-DC converter 200. The voltage across the voltage VL on the inductor L1 is as follows:

VL=(RL1+sL)IL (1)

Where L is the inductance of inductor L1, IL is the current value of inductor L1, and s is the complex frequency. In addition, the voltage across the capacitor Cf Vc can be as shown in the following equation:

Where T = L / RL1, T ₁ = Rf1 × Cf1, and if T = T ₁ , then Vc = RL1 × IL. That is, if Rf1×Cf1=L/RL1 is properly selected, the voltage across the capacitor Cf Vc will be proportional to the current IL on the inductor L1, and the current flowing through the resistor Rf2 is also proportional to the current IL on the inductor L1. . Therefore, as long as the current flowing through the resistor Rf2 is detected, the change of the current IL on the inductor L1 can be known, and the weight of the load 106 can be known, and the load indication signal SC1 can be output accordingly.

FIG. 6B is a schematic diagram of a current detecting unit according to another embodiment of the present invention. Please refer to FIG. 6B. In this embodiment, the current detecting unit 206 includes a resistor Rf3 and an operational amplifier 604. The resistor Rf3 is coupled between the common junction N1 of the first transistor M1 and the second transistor M2 and the negative input terminal of the operational amplifier 604. The positive input terminal of the operational amplifier 604 is coupled to the ground voltage GND, and the negative input terminal of the amplifier 604 is coupled to its output terminal.

When the first transistor M1 is turned on and the second transistor M2 is turned off, the current IL on the inductor L1 flows from the contact point N1 to the load 106, and at this time, the voltage on the contact point N1 is a positive voltage. Conversely, when the first transistor M1 is turned off and the second transistor M2 is turned on, since the current IL portion on the inductor L1 changes immediately, the current IL still flows from the contact point N1 to the load 106, but at this time, The voltage at point N1 is a negative voltage. It should be noted that during the period when the second transistor M2 is turned on, the current IL on the inductor L1 can be detected by detecting the current flowing through the resistor Rf3, wherein the current flowing through the resistor Rf3 is proportional to the inductor L1. Current IL on. Since the positive input of the operational amplifier 604 is coupled to the ground voltage GND and its negative input is coupled to its output, the voltage on the negative input of the operational amplifier 604 will also be equal to the ground voltage GND. Since the voltage on the contact N1 is a negative voltage at this time and the voltage on the negative input terminal of the operational amplifier 604 will also be equal to the ground voltage GND, the current on the resistor Rf3 will flow from the negative input terminal of the operational amplifier 604 to the contact N1. And the current on the resistor Rf3 is proportional to the current IL on the inductor L1. In this way, it is only necessary to detect the magnitude of the current flowing through the resistor Rf3 to know the change of the current IL on the inductor L1, and then to know the light weight of the load 106, and accordingly output the load indication signal SC1.

FIG. 7 is a flow chart of a voltage conversion method of a DC-DC converter according to an embodiment of the invention. Referring to FIG. 7, in summary, the voltage conversion method steps of the DC-DC converter 200 can be summarized as follows. First, the load current of the DC-to-DC converter is detected to provide a load indication signal (step S702). Then, the first pulse width modulation signal and the load indication signal are received to output a second pulse width modulation signal (step S704), wherein the first pulse width modulation signal has a first preset pulse width. Then, the load of the DC-to-DC converter output is determined to be light load or heavy load according to the load indication signal (step S706). If the output of the DC-to-DC converter is lightly loaded, outputting a second pulse width modulation signal having a second preset pulse width (step S708), and then providing an output voltage according to the second pulse width modulation signal (step S712). If the output of the DC-to-DC converter is a heavy load, the first pulse width modulation signal is output as the second pulse width modulation signal (step S710), and then the output voltage is provided according to the second pulse width modulation signal ( Step S712), wherein the second preset pulse width is greater than the first preset pulse width. In addition, when the current drop on the inductor is zero or the pulse width modulation signal has a falling edge, the output voltage of the DC-to-DC converter will be lowered. When the rising edge of the second pulse width modulation signal occurs, the output voltage of the DC to DC converter will be pulled high.

In summary, in the embodiment of the present invention, when the load of the DC-DC converter is a heavy load and a light load, respectively, a pulse width modulation signal corresponding thereto is provided, so that the conversion efficiency of the DC-DC converter is not affected by the load. influences. When the load of the DC-DC converter is a heavy load, outputting a second pulse width modulation signal having a first preset pulse width, and at a light load, outputting a second pulse width modulation having a second preset pulse width a signal, wherein the second predetermined pulse width is greater than the first predetermined pulse width. This will continue to supply good power quality to the application circuit of the latter stage.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200. . . DC to DC converter

102. . . Control module

104. . . Output module

106. . . load

202. . . Pulse width modulation signal generation module

204. . . Voltage divider impedance unit

206. . . Current detection unit

208. . . Drive unit

210. . . Switching unit

302. . . Error amplifier

304. . . Comparators

306. . . Compensation unit

308. . . Ramp generator

310. . . Fixed on time unit

502. . . D-type flip-flop

602, 604. . . Operational amplifier

S702~S708. . . Steps of the voltage conversion method

Vin. . . Input voltage

GND. . . Ground voltage

M1, M2, M3. . . Transistor

PWM1, PWM2. . . Pulse width modulation signal

Vout. . . The output voltage

UG1, LG1. . . Switching signal

L1. . . inductance

IL. . . Current on inductor L1

SC1. . . Load indication signal

P1. . . Pulse signal

Vref. . . Reference voltage

ER1. . . Error signal

RA, RB, R1, Rf1~Rf3, RL1. . . resistance

CA, CB, C1, Cf. . . capacitance

Ramp1. . . Oblique wave signal

I1. . . Battery

Vc. . . Cross-voltage on capacitor Cf

VL. . . Cross-over on inductor L1

CLK. . . Clock signal

INV1~INV8. . . Reverse gate

AND1~AND2. . . Gate

NAND1. . . Reverse gate

OR1. . . Gate

VOP1. . . Operating voltage

Son1. . . Fixed on time signal

N1. . . contact

FIG. 1 is a schematic diagram of a DC-to-DC converter according to an embodiment of the invention.

2 is a schematic diagram of a DC-to-DC converter according to another embodiment of the present invention.

3 is a schematic diagram of a DC-to-DC converter according to another embodiment of the present invention.

4 is a waveform diagram of a plurality of signals in a DC-to-DC converter of the embodiment of FIG. 3.

5A and 5B are schematic diagrams showing a fixed on-time unit according to an embodiment of the present invention.

6A and 6B are schematic diagrams showing a current detecting unit according to an embodiment of the present invention.

FIG. 7 is a flow chart of a voltage conversion method of a DC-DC converter according to an embodiment of the invention.

100. . . DC to DC converter

102. . . Control module

104. . . Output module

106. . . load

Vin. . . Input voltage

GND. . . Ground voltage

PWM1, PWM2. . . Pulse width modulation signal

Vout. . . The output voltage

SC1. . . Load indication signal

Claims (9)

A DC-to-DC converter is adapted to provide an output voltage to a load. The DC-to-DC converter includes: a control module that receives a first pulse width modulation signal and a load indication signal to output a second a pulse width modulation signal, the first pulse width modulation signal has a first predetermined pulse width; when the load indication signal indicates that the load is a heavy load, the control module uses the first pulse width modulation signal as the a second pulse width modulation signal output; when the load indication signal indicates that the load is a light load, the control module outputs the second pulse width modulation signal having a second predetermined pulse width; and an output module The output module is coupled to the control module, and the output module provides the output voltage according to the second pulse width modulation signal, wherein the second predetermined pulse width is greater than the first predetermined pulse width. The DC-to-DC converter of claim 1, further comprising: a current detecting unit for detecting a load current of the output module to provide the load indicating signal. The DC-DC converter of claim 2, wherein the control module comprises: a first reverse gate, wherein the input end receives the load indication signal; a first AND gate, the input end receives the first a pulse width modulation signal and the load indication signal; a second gate, the input end receiving the first pulse width modulation signal and the output signal of the first back gate; a fixed on time unit coupled to the first And at the output end of the second gate, when the output signal of the second gate has a rising edge, the fixed on-time unit outputs a fixed on-time signal according to the output signal of the second gate, wherein the fixed-on time signal pulse The width is equal to the second predetermined pulse width; and the input terminal is coupled to the output end of the first gate and the on-time control unit, according to the output result of the first gate and the fixed on-time signal The second pulse width modulation signal is output. The DC-to-DC converter of claim 3, wherein the fixed on-time unit comprises: a second reverse gate, the input end of which is coupled to the output end of the second gate; and a third reverse gate, The input end is coupled to the output end of the second reverse gate; a fourth reverse gate, the input end of which is coupled to the output end of the third reverse gate; and a third gate, the input end of which is coupled to the third reverse gate And an output terminal of the second gate; and a fifth reverse gate, the input end of which is coupled to the output end of the third gate, and the output of the fifth gate is coupled to the input of the gate . The DC-to-DC converter according to claim 3, wherein the fixed on-time unit comprises: a D-type flip-flop, wherein the data input end is coupled to an operating voltage, and the clock of the D-type flip-flop The input end is coupled to the output end of the second gate, the reset end of the D-type flip-flop is coupled to the output end of the first comparator, and the data output end of the D-type flip-flop is coupled to the gate An input end; a sixth reverse gate, the input end of which is coupled to the data output end of the D-type flip-flop; a third transistor whose gate is coupled to the output end of the sixth reverse gate, the third transistor The source is coupled to the ground voltage; a current source coupled to the drain of the third transistor; a capacitor coupled to the drain of the third transistor; and a seventh reverse gate coupled to the input terminal a drain of the third transistor; and an eighth back gate, the input end of which is coupled to the output end of the seventh reverse gate, and the output end of the eighth reverse gate is coupled to the reset end of the D-type flip-flop. The DC-to-DC converter according to claim 1, further comprising: a voltage dividing impedance unit coupled between the output end of the DC-DC converter and a ground voltage; and a pulse width modulation The signal generating module is coupled to a current detecting unit, the control module and the voltage dividing impedance unit, and generates the first pulse width modulation signal according to a reference voltage, the load indicating signal and a partial voltage of the output voltage. The DC-to-DC converter according to claim 6, wherein the pulse width modulation signal generating module comprises: an error amplifier, wherein the positive and negative input terminals are respectively coupled to the reference voltage and the voltage dividing impedance unit And generating an error signal according to the reference voltage and the voltage division of the output voltage; a compensation unit coupled to the output end of the error amplifier to compensate the error signal; a ramp generator coupled to the current detection unit, The load indicating signal and the one pulse signal generate a ramp signal; and a second comparator, wherein the positive and negative input ends are respectively coupled to the output end of the error amplifier and the ramp generator, according to the error signal and the oblique The comparison result of the wave signal produces the first pulse width modulation signal. A voltage conversion method is applicable to a DC-to-DC converter, wherein the DC-to-DC converter is adapted to provide an output voltage to a load, the voltage conversion method comprising: detecting a load current of the DC-DC converter, Providing a load indication signal; receiving a first pulse width modulation signal and the load indication signal to output a second pulse width modulation signal, wherein the first pulse width modulation signal has a first preset pulse width; The load indication signal determines that the load of the DC-to-DC converter output is a light load or a heavy load; if the output of the DC-to-DC converter is a light load, the output has the second preset pulse width of the second a pulse width modulation signal; and if the output of the DC to DC converter is a heavy load, the first pulse width modulation signal is used as the second pulse width modulation signal output; and the second pulse width modulation signal is used according to the second pulse width modulation signal The output voltage is provided, wherein the second predetermined pulse width is greater than the first predetermined pulse width. The voltage conversion method of claim 8, wherein the output voltage is raised when a rising edge of the pulse width modulation signal occurs, and decreased when a falling edge of the second pulse width modulation signal occurs.