CN114825906A - Voltage converter and class-D amplifier - Google Patents

Voltage converter and class-D amplifier Download PDF

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Publication number
CN114825906A
CN114825906A CN202110060626.1A CN202110060626A CN114825906A CN 114825906 A CN114825906 A CN 114825906A CN 202110060626 A CN202110060626 A CN 202110060626A CN 114825906 A CN114825906 A CN 114825906A
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China
Prior art keywords
output
circuit
voltage
charging
signal
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CN202110060626.1A
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Chinese (zh)
Inventor
黄扬景
施登耀
许雅绵
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Elite Semiconductor Memory Technology Inc
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Elite Semiconductor Memory Technology Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A voltage converter and a class D amplifier. The voltage converter comprises an output circuit, an error amplifier and a charging control circuit. The output circuit includes an output capacitor. The charge control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier within a specific range according to the detection signal. The charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier so as to charge the output capacitor.

Description

Voltage converter and class-D amplifier
Technical Field
The present invention relates to a voltage converter and a class D amplifier, and more particularly, to a voltage converter and a class D amplifier capable of compensating for a leakage current of an output capacitor without causing an abnormality in a loop (loop).
Background
The known voltage converter may comprise an output circuit (bootstrap circuit) with an output capacitance. However, during operation, the voltage of the output capacitor may become low due to consumption of the pre-driver. This situation may cause the output circuit to fail to operate properly, for example, causing an abnormal loop.
Disclosure of Invention
Therefore, an object of the present invention is to provide a voltage converter that does not cause loop abnormality when compensating for leakage current of an output capacitor.
Another objective of the present invention is to provide a class D amplifier that does not cause loop anomaly when compensating for leakage current of an output capacitor.
An embodiment of the invention discloses a voltage converter, which comprises an output circuit, an error amplifier and a charging control circuit. The output circuit includes an output capacitor. The charge control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier within a specific range according to the detection signal. The charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier so as to charge the output capacitor.
An embodiment of the invention discloses a class-D amplifier, which comprises an output circuit, an error amplifier and a charging control circuit. The output circuit includes an output capacitor. The charge control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier within a specific range according to the detection signal. The charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier so as to charge the output capacitor.
According to the embodiment, the voltage converter provided by the invention can compensate the leakage current problem under the condition of not directly pulling down the output voltage, thereby avoiding the abnormity of a loop while compensating the leakage current of the output capacitor.
Drawings
Fig. 1 is a block diagram of a voltage converter according to an embodiment of the invention.
Fig. 2 is a circuit diagram illustrating a detailed structure of the voltage converter shown in fig. 1 according to an embodiment of the invention.
Fig. 3 is a circuit diagram illustrating a detailed structure of the output circuit shown in fig. 1 and 2 according to an embodiment of the present invention.
Fig. 4 is a circuit diagram illustrating a detailed structure of the detection circuit shown in fig. 1 and 2 according to an embodiment of the present invention.
Fig. 5 and 6 are schematic diagrams illustrating the operation of the circuits shown in fig. 1 and 2 according to an embodiment of the invention.
[ notation ] to show
100 voltage converter
101 error amplifier
103 charging control circuit
105 charging circuit
107 detection circuit
109 power limiting circuit
401 logic circuit
BC _1, BC _2 bootstrap circuit
C _1 output capacitor
C _1a, C _2a capacitance
CC _1, CC _2 conversion circuit
CM _1, CM _2 comparator
DA _1, DA _2 differential amplifier
R _1i, R _2i, R _1f, R _2f resistors
OP _1 operational amplifier
SD Schottky diode
Pr _1a, Pr _1b, Pr _1c, Pr _2a, Pr _2b predriver
SW _1, SW _2 switch
Detailed Description
The present invention will be described in terms of several embodiments, it should also be noted that the terms "first," "second," and the like in the following description are only used for defining different elements, parameters, data, signals or steps. And are not intended to be limiting.
Fig. 1 is a block diagram of a voltage converter according to an embodiment of the invention. As shown in fig. 1, the voltage converter 100 includes an error amplifier 101, a charge control circuit 103, a charge circuit 105, and bootstrap circuits BC _1 and BC _ 2. The charge control circuit 103 further includes a detection circuit 107 and a power limiting circuit 109. Please note that in the following embodiments, the voltage converter 100 is a differential input/output circuit, and thus has two bootstrap circuits BC _1 and BC _ 2. However, the voltage converter 100 may be a single input/output circuit. In this case, the voltage converter 100 may have only one bootstrap circuit, and the other circuit configuration may be changed accordingly. In addition, in the following description, for convenience of illustration, only one path of the voltage converter 100 is shown.
The bootstrap circuit BC _1 includes an output capacitor (not shown in fig. 1). The detection circuit 107 is used for detecting the output voltage V _ c1 of the output capacitor to generate the detection signal DS. The power limiting circuit 103 is used for clamping the output voltage V _ e1 of the error amplifier 101 to a specific range according to the detection signal DS. In one embodiment, the particular range is a particular voltage level. The charging circuit 105 is used for generating a charging signal CS _1 according to the output voltage V _ e1 to charge the output capacitor. In one embodiment, the power limiting circuit 109 clamps the output voltage V _ e1 to a specific range, so that the charging circuit 105 increases the frequency of charging the output capacitor, thereby increasing the voltage of the output capacitor.
In one embodiment, the voltage converter 100 may operate as a class D amplifier. In this case, the pilot circuit BC _1 can be regarded as an output circuit.
In the following description, a detailed circuit of the voltage converter 100 is described. It should also be understood that these circuits are exemplary only, and are not meant to limit the scope of the present invention. Any circuit having the same function should also fall within the scope of the present invention.
Fig. 2 is a circuit diagram illustrating a detailed structure of the voltage converter shown in fig. 1 according to an embodiment of the invention. As shown in fig. 2, the error amplifier 101 includes resistors R _1i and R _2i, capacitors C _1a and C _2a, and an operational amplifier OP _ 1. Also, the charging circuit 105 is a PWM circuit including comparators CM _1, CM _2, the comparators CM _1, CM _2 respectively including a negative input terminal for receiving the triangular wave signal Tr and a positive input terminal for receiving an output from the output voltage V _ e 1. The power limiting circuit 109 includes a differential amplifier DA _1, and the differential amplifier DA _1 includes: a first input terminal for receiving an output voltage V _ e 1; a second input terminal for receiving a reference voltage RV (i.e. the specific voltage level); a first output terminal for generating a first power limiting signal P _1 according to the output voltage V _ e1 and a reference voltage RV; a second output terminal for generating a second power limiting signal P _2 according to the output voltage V _ e1 and the reference voltage RV. The error amplifier 101 receives the first power limiting signal P _1 and the second power limiting signal P _2 to generate the output voltage V _ e 1. In one embodiment, the negative input terminal of the operational amplifier OP _1 receives the second power limiting signal P _2, and the positive input terminal of the operational amplifier OP _1 receives the first power limiting signal P _ 1.
Fig. 3 is a circuit diagram illustrating a detailed structure of the output circuit shown in fig. 1 and 2 according to an embodiment of the present invention. In addition, fig. 4 is a circuit diagram illustrating a detailed structure of the detection circuit shown in fig. 1 and 2 according to an embodiment of the present invention. For a clearer understanding of the contents of the present invention, please refer to fig. 2 and fig. 3 or fig. 4 at the same time.
As shown in fig. 3, the bootstrap circuit BC _1 includes an output capacitor C _1 (i.e., the output capacitor), switches SW _1 and SW _2, pre-drivers Pr _1a, Pr _1b, Pr _1C, Pr _2a and Pr _2b, and a schottky diode SD. The bootstrap circuit BC _1 operates at the operating voltage V _ op and receives the charging signal CS _1 to control the switches SW _1 and SW _2 to be turned on (i.e., conductive) or turned off (i.e., non-conductive). The switch SW _1 and the pre-drivers Pr _1a, Pr _1b, Pr _1c form an upper bridge path. In addition, the switch SW _2 and the pre-drivers Pr _2a, Pr _2b form a lower bridge path. As described above, the charging signal CS _1 may be a PWM signal. Therefore, in the embodiment of fig. 3, if the charging signal CS _1 has a low logic value, the lower bridge path is turned on (i.e., the switch SW _2 is turned on) and the upper bridge path is turned off (i.e., the switch SW _1 is turned off) to charge the output capacitor C _ 1. Conversely, if the charging signal CS _1 has a high logic value, the upper bridge path is turned on and the lower bridge path is turned off, so that the output capacitor C _1 is not charged and Vp _1 is boosted. When the output capacitor C _1 is charged, it may leak current, and thus its voltage may drop.
Referring to fig. 4, the detection circuit 107 includes a comparator CM _ d for comparing the voltages at the two ends of the output capacitor C _1 (i.e., the output voltage V _ C1 and the voltage V _ p1 in fig. 3) and the difference threshold voltage V _ dt. Also, the detection circuit 107 includes a logic circuit 401 (e.g., an or gate) to generate the detection signal DS according to the output of the comparator CM _ d. In more detail, the detection circuit 107 in fig. 4 includes a conversion circuit CC _1 for converting a voltage difference between voltages at two ends of the output capacitor C _1 into a current. Then, the resistor R _ x generates a voltage difference according to the current. It should also be understood that the detection circuit 107 is not limited to comparing the voltages at the two ends of the output capacitor C _1 to detect whether the output capacitor C _1 has leakage. For example, the detection circuit 107 may compare the output voltage V _ C1 with a standard voltage and determine that the output capacitor C _1 has leakage when the output voltage V _ C1 is less than the standard voltage.
Fig. 5 and 6 are schematic diagrams illustrating the operation of the circuits shown in fig. 1 and 2 according to an embodiment of the invention. Fig. 5 shows the relationship between the voltage V _ C1 across the capacitor C _1, the charging signal CS _1 and the charging current I _ C. As shown in fig. 5, when the voltage V _ C1 on the capacitor C _1 is greater than the threshold voltage V _ th and the output capacitor C _1 is not charged, the voltage converter 100 operates in the normal mode. In addition, the charging signal CS _1, which is a PWM signal, has a high duty cycle (in this case, the duty cycle is 100%) in the normal mode. In addition, when the voltage V _ C1 across the capacitor C _1 is smaller than the threshold voltage V _ th, the voltage converter 100 enters the compensation mode. In the compensation mode, the charging signal CS _1 has a low duty ratio. When the charging signal CS _1 has a low logic value, the output capacitor C _1 is charged with the charging current I _ C. Therefore, the voltage V _ C1 across the capacitor C _1 gradually increases in the compensation mode until it is greater than the threshold voltage V _ th. In one embodiment, the threshold voltage V _ th is set to 0.5 × V _ op.
Fig. 6 shows the relationship between the voltage V _ C1 across the capacitor C _1, the charging signal CS _1, the detection signal DS, and the output voltage V _ e1 of the error amplifier 101. As shown in fig. 6, in the normal mode, the voltage V _ C1 across the capacitor C _1 is greater than the threshold voltage V _ th, so the duty ratio of the charging signal CS _1 is high, and the logic value of the detection signal DS is low. Also, in the normal mode, the output voltage V _ e1 of the error amplifier 101 is not suppressed. In addition, if the voltage V _ C1 across the capacitor C _1 is less than the threshold voltage V _ th, the voltage converter 100 enters the compensation mode. In the compensation mode, the charging signal CS _1 has a low duty ratio, and the detection signal DS has a high logic value. Also, in the compensation mode, the output voltage V _ e1 of the error amplifier 101 is suppressed to a certain voltage level V _ sp to reduce the duty ratio of the charging signal CS _ 1.
In one embodiment, the specific voltage level V _ sp is determined by the following formula:
Figure BDA0002902408260000051
v _ Ltri is a bottom voltage (bottom voltage) of the triangular wave signal Tr, which is used by the charging circuit 105 to generate the PWM signal. In addition, V _ Htri is the top voltage (upper voltage) of the triangular wave signal Tr. Further, in the compensation mode, the duty ratio of the charging signal CS is reduced to be less than D _ max.
In one embodiment, D _ max is
Figure BDA0002902408260000052
I _ C is the charging current of the output capacitor C _1 when the output capacitor C _1 is charged. In one embodiment, I _ c is equal to the forward current of the schottky diode SD in fig. 3. In addition, I _ d is a discharge current when the output capacitor is not charged. In one embodiment, I _ d may be the leakage current of the schottky diode SD, the switching loss current of the pre-drivers Pr _1a, Pr _1b, Pr _1c during the transition period, or the junction leakage current at the node V _ p1 in fig. 3.
According to the embodiment, the voltage converter provided by the invention can compensate the leakage current problem under the condition of not directly pulling down the output voltage, thereby avoiding the abnormity of a loop while compensating the leakage current of the output capacitor.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims (18)

1. A voltage converter, comprising:
an output circuit including an output capacitor;
an error amplifier:
a charge control circuit, comprising:
the detection circuit is used for detecting the output voltage of the output capacitor to generate a detection signal; and
a power limiting circuit for clamping the output voltage of the error amplifier within a specific range according to the detection signal; and
the charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier so as to charge the output capacitor.
2. The voltage converter of claim 1, wherein the power limiting circuit clamps the output voltage of the error amplifier within the specific range such that the charging circuit increases the frequency of charging the output capacitor.
3. The voltage converter of claim 1, wherein the charging circuit is a PWM circuit and the charging signal is a PWM signal, wherein the power limiting circuit clamps the output voltage of the error amplifier in the specific range such that the duty cycle of the charging signal is reduced.
4. The voltage converter of claim 3, wherein the duty cycle is reduced to less than
Figure FDA0002902408250000011
Wherein I _ c is a charging current when the output capacitor is charged, and I _ d is a discharging current when the output capacitor is not charged.
5. The voltage converter of claim 3, wherein the first and second voltage sources are connected in series,
wherein the output circuit comprises an upper bridge path and a lower bridge path;
wherein if the charging signal has a low logic value, the lower bridge path is turned on to charge the output capacitor, but the upper bridge path is turned off;
wherein if the charging signal has a high logic value, the upper bridge path is turned on but the lower bridge path is turned off.
6. The voltage converter of claim 1, wherein the power limiting circuit comprises:
a differential amplifier, comprising:
a first input terminal for receiving the output voltage;
a second input terminal for receiving a reference voltage;
a first output terminal for generating a first power limiting signal according to the output voltage and the reference voltage;
a second output terminal for generating a second power limiting signal according to the output voltage and the reference voltage;
wherein the error amplifier receives the first power limiting signal and the second power limiting signal to generate the output voltage.
7. The voltage converter of claim 6, wherein the charging circuit is a PWM circuit comprising at least one comparator, wherein the comparator receives the output voltage and a triangular wave signal to generate the charging signal.
8. The voltage converter of claim 1, wherein the detection circuit comprises:
a comparator for comparing the voltage at both ends of the output voltage with a differential threshold voltage; and
the logic circuit is used for generating the detection signal according to the output of the comparator.
9. The voltage converter of claim 1, wherein the specific range is a specific voltage level.
10. A class D amplifier, comprising:
an output circuit including an output capacitor;
an error amplifier:
a charge control circuit, comprising:
the detection circuit is used for detecting the output voltage of the output capacitor to generate a detection signal; and
a power limiting circuit for clamping the output voltage of the error amplifier within a specific range according to the detection signal; and
the charging circuit is used for generating a charging signal to the output circuit according to the output voltage of the error amplifier so as to charge the output capacitor.
11. The class-D amplifier of claim 10, wherein the power limiting circuit clamps the output voltage of the error amplifier within the specified range such that the charging circuit increases the frequency of charging the output capacitor.
12. The class-D amplifier of claim 10, wherein the charging circuit is a PWM circuit and the charging signal is a PWM signal, wherein the power limiting circuit clamps the output voltage of the error amplifier in the specific range such that the duty cycle of the charging signal is reduced.
13. A class D amplifier circuit as claimed in claim 12 wherein the duty cycle is reduced to less than
Figure FDA0002902408250000021
Wherein I _ c is a charging current when the output capacitor is charged, and I _ d is a discharging current when the output capacitor is not charged.
14. The class-D amplifier of claim 12,
wherein the output circuit comprises an upper bridge path and a lower bridge path;
wherein if the charging signal has a low logic value, the lower bridge path is turned on to charge the output capacitor, but the upper bridge path is turned off;
wherein if the charging signal has a high logic value, the upper bridge path is turned on but the lower bridge path is turned off.
15. The class D amplifier of claim 10, wherein the power limiting circuit comprises:
a differential amplifier, comprising:
a first input terminal for receiving the output voltage;
a second input terminal for receiving a reference voltage;
a first output terminal for generating a first power limiting signal according to the output voltage and the reference voltage;
a second output terminal for generating a second power limiting signal according to the output voltage and the reference voltage;
wherein the error amplifier receives the first power limiting signal and the second power limiting signal to generate the output voltage.
16. The class D amplifier of claim 15, wherein the charging circuit is a PWM circuit comprising at least one comparator, wherein the comparator receives the output voltage and a triangular wave signal to generate the charging signal.
17. The class D amplifier of claim 10, wherein the detection circuit comprises:
a comparator for comparing the voltage at both ends of the output voltage with a differential threshold voltage; and
the logic circuit is used for generating the detection signal according to the output of the comparator.
18. The class D amplifier of claim 10, wherein the specific range is a specific voltage level.
CN202110060626.1A 2021-01-18 2021-01-18 Voltage converter and class-D amplifier Pending CN114825906A (en)

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Publication Number Publication Date
CN114825906A true CN114825906A (en) 2022-07-29

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