JP2858164B2 - Power supply - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device which is particularly suitable for small and medium power and outputs a stable high voltage to a load.

[Conventional technology]

As a power supply device that outputs a stable high voltage to a load, a switching power supply device is conventionally known. This device controls the switching of the primary side of the output transformer, rectifies the high voltage induced in the secondary side of the transformer, and supplies it to the load. The switching element on the primary side is fed back with a PWM (pulse width modulation) signal. By controlling, a stable output can be obtained.

[Problems to be solved by the invention]

However, since the conventional power supply as described above uses a transformer, it is heavier than the other components of the system, so that the system cannot be weighed. Because of the shield, there is a problem in that design restrictions are large.

The present invention has been made in view of such a problem, and an object of the present invention is to obtain a power supply device that can be weighed and has few design restrictions.

[Means for solving the problem]

The power supply device of the present invention is configured as follows.

(1) A plurality of capacitors, a first switch group for connecting the plurality of capacitors in parallel, a second switch group for connecting the plurality of capacitors in series, and a third switch for short-circuiting each of the plurality of capacitors. Switches and
A first switch control circuit for controlling the first switch group and the second switch group to perform switching between parallel connection and series connection, and a second switch control circuit for controlling the third switch group A DC power supply for charging a plurality of capacitors connected in parallel; a detection circuit for detecting a voltage supplied to the load from the plurality of charged capacitors switched to the series connection; And a PWM circuit for outputting a PWM signal having the duty to the switch control circuit. The first switch control circuit variably controls a parallel connection time of the plurality of capacitors according to a duty of the PWM signal. In addition, the series connection time is fixed, and the second switch control circuit determines that the pulse width of the PWM signal is equal to or greater than a first predetermined value. Was to control the third switch group in accordance with the detection of that falls below a second predetermined value.

(2) The first and second switch control circuits are constituted by one-chip inductively separated ICs.

(3) The second switch control circuit includes the PW
Under the condition that the pulse width of the M signal does not become equal to or more than the first predetermined value or equal to or less than the second predetermined value, the control is performed such that the number of ONs of the switch group is minimized.

[Action]

In the power supply device of the present invention, a plurality of capacitors are connected in parallel by the first switch group, and in this state, each capacitor is charged by the DC power supply. Then, the charged capacitors are connected in series by the second switch group, and the high voltage of the sum of these capacitors is output to the load. At this time, connection switching of each capacitor is controlled by a switch control circuit, and a stable output is obtained by controlling this by a PWM signal. Also,
The response speed can be increased by controlling the third switch group that shorts each capacitor.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
In _{FIG, C 1, C 2, ......} C n capacitors of the plurality of (n in this _{case), S 10, S 11,} ...... S 1n, S 21, S 22 ...... S 2n and S _30, S
_31, ...... S _3n on switches provided for each capacitor, respectively, switches _{S 10, S 11, ...... S} n and the switch S _30, S ₃₁ ...
... S _3n each capacitor C _1, C _2, first paralleling the ...... C _n
Constitute switch group, switches _{S 21, S 22, ...... S} 2n each capacitor C _1, C _2, form a second group of switches to be connected in series with ...... C _n. S ₄₁ , S ₄₂ , …… S _4n is each capacitor C ₁ ,
A switch for short-circuiting C ₂ ,..., C _n constitutes a third switch group. V ₁ is each capacitor connected in parallel
C ₁ , C ₂ ,..., C _n are current power supplies for charging C _n , P ₁ , P ₂ are a high voltage output terminal and a high voltage reference terminal (ground terminal) to the load 1, and the load 1 has a charged capacitor C _1. , C ₂ ,..., C _n are connected in series. Di ₁ is a diode, C ₀₁ , C ₀₂ and R ₀₁ are capacitors and resistors constituting a filter circuit, and a direct current is applied to the load 1 through the diode Di ₁ and the filter circuit. 2 is load 1
Voltage detection circuit for detecting the output voltage (load voltage) to the
Is an operation amplifier for comparing the detected value with a reference value from the voltage source V _2, and a detection signal from the voltage detection circuit 2 is input to a minus input terminal through a signal line 4. Reference numeral 5 denotes a PWM circuit that generates a PWM signal based on the output of the operation amplifier 3 input through the signal line 6, and 7 denotes capacitors C ₁ and C ₂ by the above switch groups based on the PWM signal input through the signal line 8. , a switch control circuit that performs parallel connection and switching of the series connection of ...... C _n, from the output bus 7a switches
S ₁₀ , S ₁₁ , S _1n control signal, switch from output bus 7b
S _21, S _22, ...... S control signal _2n, the output switch S _30, S ₃₁ from the bus 7c, the control signal ...... S _3n are output.

Reference numeral 10 denotes a switch for controlling the switches S ₄₁ , S ₄₂ ,..., S _4n of the third switch group for short-circuiting the capacitors C ₁ , C ₂ ,..., C _n according to the detection result of the variable width of the PWM signal. 2 is a switch control circuit, 11 is a comparator, one plus input terminal is connected to the signal line 4, and the other minus input terminal is D /
An analog output terminal of the A (digital / analog) converter 12 is connected via a signal line 13, and an output terminal is connected via a signal line 14 to a control signal input terminal of the switch control circuit 10. The switch control circuit 10 has output buses 10a and 10b for two kinds of signals, and the CPU 15 receives a signal line 16 from one of the output buses 10a.
In accordance with the information output above, a signal for holding an open state of any of the switches S ₃₀ , S ₃₁ ,... S _3n and the switches S ₁₀ , S _{11 ,.} The CPU 15 turns on or off any of the switches S ₄₁ , S ₄₂ ,... S _4n from the other output bus 10 b in accordance with information output from the CPU 15 onto the signal line 16 via the signal line 16. Is output. The switches S ₄₁ , S ₄₂ ,...
... S _4n are connected capacitors C _1, C _2, in parallel with ...... C _n. Further, the digital data of the D / A converter 12 is transmitted from the CPU 15 through the signal bus line 17 to the D / A converter.
Serves as may set configuration and the 12 digital signal input terminal of the ground lines of the D / A converter 12 (reference power supply line) is connected to a high voltage reference terminal P _2.

The high-voltage output terminal P ₁ is, n-th呑opposite terminal and the diode Di ₁ and the connection end of the switch S _2n capacitors C _n
Of being connected to the anode side, high-voltage reference terminal P ₂ is connected to the negative terminal side of the terminal and the voltage source V ₁ of the side opposite to the connection end of the first switch S ₁₀ of the capacitor C _1. Then, the positive terminal of the voltage source V ₂ is connected to the positive input terminal of the differential amplifier 3.

 Next, the operation will be described.

When the circuit is operating in a steady state, a PWM signal having a waveform as shown in FIG.
Each capacitor depends on the timing of the duty of the WM signal.
C _1, C _2, switching of connection of ...... C _n is controlled. That is,
The timing (period) at which the H (high) level signal of the control pulse is output is A, the timing at which the L (low) level signal is output is B, and the A + B period is one cycle of the pulse. The time of timing B is fixed for simplicity, the time of timing A is variable, and
If the voltage V ₀ is H level output, the increased time T _A that is the output shall be reduced if the L level. Then, first, when the timing of the signal on the signal line 8 is A, then the output bus 7a and outputs the H-level control signal on 7c, first the switch S ₁₀ of switch group, S ₁₁ of the switching control circuit 7 , S _1n and S ₃₀ , S ₃₁ , …… S _3n all ON
To At the same time, outputs an L level output control signal on the bus 7b, a second of the switches S ₂₁ of switch group, S _22, ...... S
Turn _2n off. Thereby, each capacitor C ₁ ,
C ₂ ,..., C _n are connected in parallel with each other. FIG. 3 shows an equivalent circuit at the time of this parallel connection. Here, the switches are all an ideal switch assuming that can be expressed as the sum of the on time of the on-resistance equivalent circuit, each capacitor C _1, C _2, ...... respectively on resistance to C _n R ₁₁ , R ₂₁ , …… R
_n1 is the base of the series connection. Then, through the resistors R ₁₁ , R ₂₁ ,..., R _n1 shown in FIG. 3, each time constant (C ₁ R
₁₁ , C ₂ R ₂₁ ,..., C _n R _n1 ) and each capacitor C ₁ , C ₂ ,.
C _n is charged by the DC power supply V _1.

Next, when the T _A period of the timing A ends and the pulse state at the timing B transits, the control signals of the output buses 7a and 7c of the switch control circuit 7 change from H level to L level, and at the same time, the output bus 7b Changes from the L level to the H level. Thus, the switches S ₁₀ , S ₁₁ ,... S _1n and S ₃₀ , S _{31 ,.}
Are turned off, and the switches S ₂₁ , S ₂₂ ,..., S _{2n of} the second switch group are turned on, and the capacitors C ₁ , C ₂ ,
...... a state in which C _n are connected in series with each other. FIG. 4 shows an equivalent circuit of this series connection. In the figure, R ₁₂ , R ₂₂ , …… R _n2
Are the on-resistances of the switches S ₂₁ , S ₂₂ ,..., S _2n . In this state, the capacitors C _1, C _2, a high voltage of the sum by electric charge charged in ...... C _n is supplied to the load 1 through the diode Di ₁ and the aforementioned filter circuit. At that time, only V _f fraction in a diode Di ₁ voltage drops.

The DC voltage supplied to the load 1
_{C 1, C 2, ...... C} n, C 01, C 02 and resistor R _01, R _{12, 22,} is adjusted by the CR time constant of the ...... R _n2, increases the time T _A timing A is long, Decreases when shorter. The voltage across the load 1 is detected by the voltage detection circuit 2, and a detection signal is output on a signal line 4. Then, the H signal from the differential amplifier 3 output voltage on the signal line 6 if Kere lower than the reference voltage of the voltage source V ₂ on signal line 4 is output, is higher than the reference voltage L signal is outputted The output of the PWM circuit 5 is controlled by the HL signal. That is, a PWM signal based on the level of the output voltage to the load 1 is output to the switch control circuit 7, and negative feedback control is applied to the whole system, so that the voltage across the load 1 is maintained at a constant voltage. You. At that time, the voltage across the load 1 is to decrease the charge of the capacitor C _01, C ₀₂ as in the third view in the period T _A of the timing A is discharged to the resistor R ₀₁ and the load 1, the period of time T _B The capacitors C ₀₁ and C ₀₂ with the maximum capacitors C ₁ and
C _2, the voltage level -Di ₁ that occurs when the ...... C _n are connected in series
Up to the level of V _F operates to charge.

As described above, since the DC high voltage can be supplied to the load 1 without using a transformer, the measurement can be achieved, and there is no switching noise or magnetic shield, and there are few design restrictions.

The time range of the timing A of the PWM signal from the PWM circuit 5 normally has a maximum value when the PWM circuit 5 is created by an actual IC or the like, and requires a time width of the timing A that is equal to or longer than the maximum width. Control at high voltage becomes impossible. Conversely, there is a minimum width of the time range of the timing A in an IC or the like, and control at a low voltage ₍ under high-voltage control ₎ that requires a time width equal to or less than the minimum width becomes impossible.

The present embodiment is configured to solve these inconveniences, and operates as follows. Now, D / A conversion of digital data corresponding to the detected voltage value of the high voltage voltage detection circuit 2 corresponding to the maximum value of the output pulse width of the PWM circuit 5 or slightly lower voltage from the CPU 15 through the signal bus line 17 is performed. vessel
Set to 12 digital signal input terminals. And
When the potential of the positive input terminal of the comparator 11 exceeds the potential indicated by the digital data of the D / A converter 12, the output of the comparator 11 changes from “0” to “1”, and the signal is controlled by the switch control circuit 10. It is input to the signal input terminal. When detecting the signal, the switch control circuit 10 determines whether the signal output on the signal line 14 is the maximum value or the minimum value of the timing A according to the instruction of the signal on the signal line 16. When the maximum value is determined, the switch control circuit 10 performs the following operation so that the maximum value detection signal is not detected. That is, when the switch _S4n is on, the switches _S1n and _S3n are always open, and when the switch _S4n is off, the switches _S1n and _S3n always perform the above-described operation. When the switch S _4n is turned on, “n” is changed in order from the maximum value to the minimum value, and when the switch S _4n is turned off, the reverse control is performed to obtain the maximum value. Control is performed such that the number of ON of the switch _S4n is minimized under the condition that the detection signal is not detected.

Next, the operation when the minimum value of the time width of the timing A of the PWM signal is detected will be described. At this time, the CPU 15 detects a high voltage corresponding to the minimum value of the output pulse width of the PWM circuit 5 formed by the time width of the timing A to the digital signal input terminal of the D / A converter 12 through the signal bus line 17. Digital data corresponding to or slightly higher than the detected voltage value of the circuit 2 is set to the digital signal input terminal of the D / A converter 12 through the signal bus line 17. When the potential of the plus input terminal of the comparator 11 falls below the potential indicated by the digital data of the D / A converter 12, the output of the comparator 11 changes from "1" to "0", Input to control signal input terminal. When detecting the signal, the switch control circuit 10 determines that the signal output on the signal line 14 is the minimum value of the timing A according to the instruction of the signal on the signal line 16, and determines the minimum value detection signal. The following operation is performed so that is not detected. That is, when the switch _S4n is on, the switches _S1n and _S3n are always open, and when the switch _S4n is off, the switches _S1n and _S3n always perform the same operation as the embodiment of FIG. When the switch S _4n is turned on, “n” is changed in order from the minimum value toward the maximum value, and when the switch S _4n is turned off, the reverse control is performed, thereby detecting the minimum value. Control is performed such that the number of ON of the switch _S4n is minimized under the condition that no signal is detected.

In the above embodiment, at least the switch control circuit is constituted by a one-chip dielectric isolation type IC, and the switch is not only a mercury switch and a reed switch but also a semiconductor switch which has been conventionally difficult in terms of its structure and breakdown voltage. Can also be used by dielectric isolation technology,
A compact circuit capable of high-speed switching control can be configured. This also has the advantage that an inexpensive transformerless high-voltage power supply can be easily configured. This is especially effective when a supercapacitor or the like is used for each capacitor, where the charging speed of one capacitor is slow and the response speed of control is delayed, and the response speed is increased by controlling the number of capacitors connected in series. There are benefits that can be achieved.

In addition, in the conventional IC, a well was formed by a PN junction. Therefore, it was necessary to always reverse bias between the well and the substrate. However, according to the above-described dielectric isolation method, the limitation is eliminated and the capacitor can be easily manufactured. It is possible to superimpose a voltage between the two.

〔The invention's effect〕

As described above, according to the present invention, a plurality of capacitors are connected in parallel and charged, and the charged capacitors are connected in series to supply a high voltage based on the sum to a load. There is an effect that a transformer is unnecessary, measurement can be achieved, switching noise and a magnetic shield are eliminated, and design restrictions are reduced.

Further, even if a request is made such that the pulse width of the PWM signal exceeds the maximum width or the minimum width, it is possible to prevent uncontrollability by selectively shorting a plurality of capacitors.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram of a PWM signal output from the PWM circuit of FIG.
FIG. 4 is an equivalent circuit diagram when the capacitors in FIG. 1 are connected in parallel, and FIG. 4 is an equivalent circuit diagram when the capacitors in FIG. 1 are connected in series. C ₁ ~C _n ...... capacitor S ₁₀ ~S _1n ...... switch (first switch group) S ₃₀ ~S _3n ...... switch (first switch group) S ₂₁ ~S _2n ...... switch (second Switch group) S _{41 to} S _4n ...... Switch (third switch group) V ₁ , V ₂ … DC power supply 1… Load 2… Voltage detection circuit 5… PWM circuit 7, 10… Switch control circuit

Claims (3)

(57) [Claims] A plurality of capacitors; a first switch group for connecting the plurality of capacitors in parallel; a second switch group for connecting the plurality of capacitors in series; and a second switch group for short-circuiting each of the plurality of capacitors. A third switch group; a first switch control circuit for controlling the first switch group and the second switch group to switch between parallel connection and series connection; and controlling the third switch group. A second switch control circuit; a DC power supply for charging a plurality of capacitors connected in parallel; a detection circuit for detecting a voltage supplied to the load from the plurality of charged capacitors switched to the series connection; And a PWM circuit that outputs a PWM signal having a duty corresponding to the output level of the circuit to the switch control circuit. Switch control circuit, the above
The parallel connection time of the plurality of capacitors is variably controlled and the serial connection time is fixed according to the duty of the PWM signal, and the second switch control circuit is configured such that the pulse width of the PWM signal is equal to or greater than a first predetermined value. Alternatively, the power supply device controls the third switch group in response to detection that the voltage has become equal to or less than a second predetermined value. 2. The power supply device according to claim 1, wherein said first and second switch control circuits are constituted by one-chip inductively-separated type ICs. 3. The second switch control circuit according to claim 2,
Under the condition that the pulse width of the PWM signal does not become equal to or more than the first predetermined value or equal to or less than the second predetermined value, control is performed such that the number of ON of the switch group is minimized. The power supply device according to claim 1.