JP3245444B2 - Wafer inspection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer inspection method .

[0002]

2. Description of the Related Art In a skip monitor function of a skip function of a conventional IC test system, as shown in FIG. 4, three continuous ICs are monitored from a wafer measurement start point of a fourth wafer and thereafter to guarantee the skip function. Was.

[0003]

The skip monitor function of the conventional test system described above has started monitoring three consecutive ICs immediately from the start point of measurement of the fourth and subsequent wafers.

[0004] In other words, for the test items, Orazu only continuous IC is a part that biased the wafer is measured
There is a problem that variations in the wafer surface are not monitored .

[0005] An object of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide an erased wafer inspection method .

[0006]

In order to achieve the above object, a wafer inspection method according to the present invention performs a test of all items from a first wafer of a lot start to a predetermined number of wafers to determine a skip condition. A skip condition determination is made as to whether or not the condition is satisfied. If the skip condition is satisfied, discontinuity at a plurality of predetermined points among a plurality of ICs in a plane of a wafer next to the predetermined number of wafers is determined. The above-described all item test is performed on a plurality of ICs to be monitored.

[0007]

In the skip monitor process, an arbitrary number of ICs are monitored.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a controller for controlling the entire test apparatus, skip control, and all other controls related to the test.

Reference numeral 102 denotes a timing generator which controls the timing of voltage and current applied to a device under test (hereinafter, referred to as a DUT).

Reference numeral 103 denotes a pattern generator which generates an expected value of input / output of the DUT. Format controller 104
Controls the voltage and current waveform applied to the DUT through the test head and the waveform output from the DUT. DC
Unit 105 tests the DC parameters of the DUT through the test head at the DC unit.

A DPS 106 supplies a bias voltage and a current to the DUT.

A level 107 supplies a level of a pulse driver built in the test head for applying a pulse to the DUT and a determination level of a pulse output of the DUT. 108
Is a test head, which serves as an interface between the DUT and the test equipment.

FIG. 2 is a flowchart showing the flow of the present invention. First, a lot is started in step 10 of FIG. In step 20, skip condition setting (test item, test circuit, reference yield value) and condition setting are performed. If the skip condition is determined in step 30 and the condition is satisfied, step 4
0 skippable test item, if unsatisfied, step 5
The skip start of step 60 is started as a 0 non-skippable test item.

When the skip is performed and the head IC of the next wafer in step 70 is reached, the temporary skip in step 80 is canceled. In step 90, skip monitor conditions are set (the number of monitor ICs and the position of the monitor IC), and in step 100, skip monitor is started.

The judgment is made based on the monitor test item in step 110. If Pass, the skip continuation item is used as it is. If Fail, the skip elimination test item in step 120 is added.
At 40, the in-wafer test is continued.

When the wafer is finished, the data is fed back to the leading IC of the next wafer in step 70. However, the skip of the test that failed on the monitor remains released.

Next, a series of flows in FIG. 2 will be described with reference to FIGS. First, in both the prior art (FIG. 4) and the present invention (FIG. 3), skip condition determination is performed from the start of the lot until the middle of the third wafer (in this example, the skip condition is satisfied in the middle of the third wafer). All items are tested to perform

Then, skipping is started in the remaining ICs of the third wafer. After the third wafer is completed,
The skip is temporarily canceled for the fourth wafer, and monitoring is started.

In the prior art, as shown in FIG. 4, three continuous ICs (the number can be set arbitrarily, but in this example, three ICs) are monitored from the start point of measurement of the fourth and subsequent wafers. I have.

On the other hand, according to the present invention, the number of ICs to be monitored is set to any three points in the wafer surface, so that variations in the wafer surface can be monitored, and a more reliable test can be performed.

The monitored IC performs a test of all test items, and if the three test items that have become skippable test items in the skip condition determination described above are Pass,
Continue to skip one item out of three ICs
If it becomes 1, the test item is a skip release test item, and the test item is not skipped until the end of the lot.

When the wafer is updated, three ICs are monitored again and the above operation is repeated. However, in this example, the number of monitors is set to three.

[0024]

As described above , according to the present invention, the skip monitor function can be executed by an arbitrary number of arbitrary ICs, so that the quality variation in the wafer surface can be accurately determined, and the skip function can be performed. By feeding back the data, the reliability of the skip function can be improved. Sa
In addition, when the skip condition is satisfied, a predetermined number of w
ICs to be monitored that are not adjacent in the plane of the wafer following EHA
Can be selected and measured to improve the bias, more reliable
High-quality inspection can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing the operation of the present invention.

FIG. 4 is a schematic diagram showing the operation of a conventional example.

[Explanation of symbols]

 Reference Signs List 101 Controller 102 Timing generator 103 Pattern generator 104 Format controller 105 DC unit 106 DPS 107 Level 108 Test head

Claims (1)

(57) [Claims] 1. A skip condition determination as to whether or not a skip condition is satisfied is performed by performing all item tests from a first wafer of a lot start to a predetermined number of wafers, and when the skip condition is satisfied, A wafer inspection method comprising: performing the all-item test on a plurality of discontinuous monitoring ICs at a plurality of predetermined points among a plurality of ICs in a plane of a wafer next to the predetermined number of wafers. .