JP2001343429A - Apparatus and method for testing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus and method for testing semiconductor devices, capable of testing an output waveform having small pulse width and of reducing the cost required in the test apparatus. SOLUTION: Test signal generating parts (14, 15, 16, 18) for generating a prescribed test signal and a comparison judging part (11, 17) for continuously comparing the value of the output signal from the semiconductor device device- under-test(DUT) 2 with a prescribed set value for a constant period to judge the quality of the DUT are provided to the DUT 2. In the comparison judging part (11, 17), the output signal during the constant period is compared with the set value, and when the value of the output signal does not exceed the set value through a fixed period, for example, the DUT 2 is judged to be poor. When there is a value of the output signal exceeding the set value during the fixed period, the DUT 2 is judged to be satisfactory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus and a test method for a semiconductor device, and more particularly, to a test apparatus and a test method for a semiconductor device for determining whether a product is good or defective in an AC characteristic test or a function test of an LSI. .

[0002]

2. Description of the Related Art Semiconductor devices (LSI: Large Scale Integer)
grated Circuit) test is performed by inputting a test signal or the like to the LSI under test, and comparing the output value from the LSI with an expected value or a threshold value to determine whether the function of the LSI is good or not, input / output signals, and power supply. For example, it measures an analog value such as voltage or current of a portion.

The test items basically include a function test, an alternating current (AC) characteristic test, and a direct current (DC) characteristic test. The outline of each test will be described below.

The function test checks the logical operation function of the LSI. The AC characteristic test checks the operation performance of the LSI, and includes a maximum operation clock frequency (operation performance of an internal logic block), a clock input duty (a ratio of 1 or 0 input period to one cycle), and input / output. Propagation delay time (time from the input of certain data until the data at the output pin changes), setup period (time for which certain signals should be determined before other signals for normal operation), hold time (The time when a certain signal should be held with respect to another signal for normal operation), and the transition time of the output waveform. In an ordinary LSI tester, an AC characteristic specification can be described as timing information in a function test. Therefore, an AC characteristic test is usually performed simultaneously in a function test. The DC characteristics test measures the static characteristics such as high-level and low-level input voltage of each input pin, the input current, the output voltage of each output pin, the output current, and the DC characteristics of the device such as the operating current consumption and the quiescent current. This is a test for measurement.

Hereinafter, an LSI tester that performs, for example, a function test including an AC test will be described. FIG. 1 is a configuration diagram of an LSI tester. In FIG. 1, an LSI tester 1 includes a CPU 11 and an input / output device 1.
2, a storage device 13, a pattern generator 14, a timing generator 15, a format controller 16,
Pattern comparator 17 and pin interface unit 18
And a programmable power supply 19.

Usually, there is a device under test 2 having n inputs and m outputs, and a DUT (Device Under T
est). Normally, response output data from the DUT 2 with respect to a test pattern for testing the DUT 2 is obtained in advance as an expected value or a threshold value by logic simulation or the like, and the LSI tester 1 includes a test pattern and a test pattern for measuring the DUT 2. The expected value of the response output from the DUT 2 or the threshold value is stored in the storage device 13.

The operation of the above LSI tester will be described. The pattern signal 14Sa generated from the pattern generator 14 by the signal from the CPU 11
The waveform is shaped by the format controller 16 according to the timing signal 15Sa generated from Step 5 and becomes a test pattern. This test pattern is applied to a predetermined input pin of the DUT 2 with a voltage level determined by a driver (not shown) of the pin interface unit 18. DUT2
Is compared with, for example, a threshold (signal) 14Sb generated from the pattern generator 14 by the pattern comparator 17 via the pin interface unit 18. The time point (sampling) at which the comparison is performed is specified by the strobe signal 15Sb from the timing generator 15. As a result of the pattern comparison, if the output pattern from the DUT 2 exceeds the predetermined threshold 14Sb, it is determined to be a pass, for example, and if it does not exceed the predetermined threshold 14Sb, it is determined to be a fail, for example.

Although not shown, a wafer prober used in connection with the LSI tester 1 is required to test the LSI in a wafer state. In the wafer prober, a signal is input from the test apparatus 1 and power is supplied through a probe that is brought into contact with a bonding pad on the surface of the LSI chip, and the probe is sequentially moved to test the LSI on the wafer one after another.

As described above, conventionally, in order to determine whether or not the DUT 2 is non-defective in an LSI tester, a test pattern is given to the input terminal of the DUT 2 from the tester, the output waveform from the DUT 2 is sampled for a certain period, and the voltage level is measured. Is compared to determine the quality of the DUT2.

FIG. 4 shows a measurement example of an LSI having a high-frequency output waveform. FIG. 4A shows the output pattern 30 from the DUT 2 and the threshold value 14Sb. This test is to check the operation performance of LSI
One of the characteristic tests is, for example, the maximum operation clock frequency (the operation performance of the internal logic block), the clock input duty (the ratio of 1 or 0 input period to one cycle), and the input / output propagation delay time (some It measures the transition time of the output waveform after inputting the data until the data at the output pin changes). For example, in the present test, for example, whether or not the output pattern 30 from the DUT 2 has a predetermined threshold value 14Sb is tested, and the output pattern 30 is detected within a predetermined period, and FIG. As shown in ()), it is necessary to determine an LSI having an output pattern 30 exceeding a predetermined threshold value 14Sb as a non-defective product.

[0011]

However, FIG.
As shown in FIG. 4A, for example, when a high-frequency output waveform 30 is measured, a strobe signal 15Sb having a frequency as shown in FIG. ) Is compared with the threshold value 14Sb.
In some cases, the SI tester cannot determine that the DUT 2 that outputs the output waveform shown in FIG. Such an output waveform from the DUT 2 has a high frequency exceeding the upper limit of the frequency of the strobe signal 15Sb of the LSI tester, or an output waveform whose frequency is within the sampling capability but whose duty is extremely thin. If the pulse width of the output waveform is very small, such as when measuring, use a tester that is more expensive, has higher performance, and has a higher frequency of the strobe signal 15Sb, or uses a separate component to replace the high frequency with the low frequency. Needed.

The present invention has been made in view of the above problems, and therefore, the present invention can test an output waveform having a small pulse width and can reduce the cost of a test apparatus. An object of the present invention is to provide a test device and a test method for a semiconductor device.

[0013]

In order to achieve the above object, a semiconductor device test apparatus according to the present invention is a semiconductor device test apparatus for determining whether a semiconductor device is defective or defective according to an output signal from the semiconductor device. And comparing the output signal with a predetermined set value continuously for a certain period of time, and when the value of the output signal does not exceed the set value throughout the certain period, is good or bad for the semiconductor device. A comparative determination for performing a first determination of a defect and performing a second determination different from the first determination on the semiconductor device when there is a value of the output signal exceeding the set value during the fixed period; Having a part.

Preferably, a test signal for outputting the output signal is generated and output to the semiconductor device, and a value of the output signal from the semiconductor device is continuously changed to a predetermined set value for a predetermined period. A test signal generation unit that generates a comparison signal to be compared and outputs the comparison signal to the comparison determination unit,
The comparison determination unit compares the value of the output signal with the set value based on the comparison signal.

For example, the test signal generator includes a pattern generator for generating a pattern signal indicating the type of waveform of the test signal, and a timing for generating a timing signal for determining timings of rising and falling of the test signal. A generator for generating the test signal from the pattern signal and the timing signal;

According to the above-described test apparatus for a semiconductor device of the present invention, for example, a predetermined test signal is input to the semiconductor device by the test signal generator, and the output signal output from the semiconductor device in response to the test signal is received. Is input to the comparison determination unit. For example, when it is desired to select a signal whose output signal value from the semiconductor device exceeds a predetermined set value as a non-defective product (second judgment) and a signal not exceeding a predetermined set value as a defective product (first judgment). In the comparison and determination unit, the output signal is continuously compared with a predetermined set value for a certain period, and if the value of the output signal does not exceed the predetermined set value during the certain period, the semiconductor It is determined that the semiconductor device is defective, and when there is an output signal value exceeding a set value during a certain period, it is determined that the semiconductor device is non-defective. The above function can be applied even when the pulse width of the output signal is very small because it is determined whether or not the output signal may exceed a predetermined set value during a certain period.

In order to achieve the above object, a method for testing a semiconductor device according to the present invention comprises the steps of: inputting a predetermined test signal to a semiconductor device; and outputting a test signal from the semiconductor device output in response to the input of the test signal. The value of the output signal is continuously compared with a predetermined set value for a certain period, and when the value of the output signal does not exceed the set value throughout the certain period, whether the semiconductor device is good or bad Make a first decision,
When there is a value of the output signal exceeding the set value during the certain period, a second determination different from the first determination is performed on the semiconductor device.

According to the method for testing a semiconductor device of the present invention, a predetermined test signal is input to the semiconductor device, and the value of an output signal output from the semiconductor device in response to the test signal is changed for a predetermined period. It is continuously compared with a predetermined set value. For example, if the value of the output signal from the semiconductor device exceeds a predetermined set value as a non-defective product, and if the value of the output signal does not exceed the predetermined set value as a defective product, the output signal and the output signal are continuously output for a certain period of time. A comparison with a predetermined set value is performed,
If the value of the output signal does not exceed a predetermined set value during the certain period, a determination is made that the semiconductor device is defective (first determination), and the output signal exceeding the set value during the certain period is determined. Is determined, the semiconductor device is determined to be non-defective (second determination). The above-described method is applied even in the case where the pulse width of the output signal is very small, because it is determined whether the output signal from the semiconductor device may exceed a predetermined set value during a certain period. Can be.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a test apparatus and a test method for a semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a test apparatus for a semiconductor device according to the present embodiment. Test apparatus 1 for semiconductor device of the present invention
Are a CPU 11, an input / output device 12, and a storage device 13.
, A pattern generator 14, a timing generator 15,
Format controller 16 and pattern comparator 17
And a pin interface section 18 and a programmable power supply 19.

The central processing unit (CPU) 11, for example,
It is composed of a general-purpose or dedicated minicomputer, etc., and manages software such as test programs, edits test programs, controls test execution, manages peripheral devices, and processes data of test results.

The input / output device 12 is composed of, for example, a printer or a display device, and performs input of control commands, input / output of test programs, output of test results, and the like.

The storage device 13 includes, for example, a magnetic disk device, a magnetic tape device, a flexible disk device, and the like, and stores system software of the test device 1, a test program, data of test results, and the like.

A pattern generator (Pattern Generator) 14
Is a pattern signal 14Sa serving as a source of a predetermined test pattern to the semiconductor device under test (device under test: DUT) 2.
Is generated and output to the format controller 16. For example, there is a sequential pattern generator for generating a logic LSI pattern. Also,
The pattern generator 14 outputs a threshold (signal) 14Sb for the test pattern for measuring the DUT 2 to the pattern comparator 17. The threshold value 14Sb is created in advance by logical simulation or the like, and stored in the storage device 13.

The timing generator 15 is a timing (time) of the rising and falling edges of the test pattern.
Pulse (timing signal) 15Sa that determines
Occurs. Further, the timing generator 15 sends a window strobe signal (Window Strob signal) to the pattern comparator 17.
e signal) 15Sb is output. The window strobe signal 15Sb is a signal that causes the pattern comparator 17 to compare with the threshold value 14Sb continuously for a certain fixed width in the test cycle.
The width of 5Sb (determination period) and the time lag from the input pattern are created by logic simulation using semiconductor process variations and temperature variations as parameters in advance.

A format controller (Format Contr)
The oller 16 shapes the pattern signal 14Sa output from the pattern generator 14 into a test pattern of a predetermined waveform mode according to the timing edge of the clock pulse 15Sa output from the timing generator 15.

Pattern comparator 1
7 compares the output pattern from the DUT 2 with the threshold value 14Sb. The comparison is performed continuously during the period of the window strobe signal based on the timing of the window strobe signal 15Sb.

The pin interface unit 18 is provided for the DUT 2
, For example, a driver that supplies a signal to the DUT 2, supplies a signal from the format controller 16 to each designated pin of the DUT 2, and compares a voltage appearing at an output pin of the DUT 2 with a pattern comparator. 17 is output. The level setting of the test pattern in the driver is performed by a DA converter (not shown).

[0029] Programmable power
supply) 19, when testing DUT2, DUT2
This is a DC power supply for applying an operating voltage to the power supply. The power on / off and the connection of the power supply to the pins of the DUT 2 can be controlled by a program, and the control values of the voltage and the current can be programmed.

Although not shown, a wafer prober used in connection with the test apparatus 1 is required to test the LSI in a wafer state. The wafer prober inputs a signal from the test apparatus 1 and supplies power through a probe that is in contact with a bonding pad on the surface of the LSI chip, and sequentially moves the probe to test the LSI on the wafer one after another. Since the position of the probe on the LSI differs depending on the type of LSI,
Printed circuit board with probe attached (probe card: prob
e card) for each type of LSI.

The operation of the semiconductor device test apparatus 1 will be described. A pattern signal 14Sa generated from the pattern generator 14 by a signal from the CPU 11 is a clock pulse 15Sa generated from the timing generator 15.
The waveform is shaped by the format controller 16 to become a test pattern. The voltage of the test pattern is determined by a driver (not shown) of the pin interface unit 18 and applied to the input pin of the DUT 2. D
The output signal from the UT 2 is output to the pin interface unit 18
Is compared with a threshold (signal) 14Sb generated from the pattern generator 14 by the pattern comparator 17. The period for performing the comparison is specified by the window strobe signal 15Sb from the timing generator 15. As a result of the pattern comparison, if the output pattern from the DUT exceeds a predetermined threshold, it is determined to be a pass, for example, and if it does not exceed the predetermined threshold, it is determined to be a fail, for example.

A method of testing a semiconductor device according to the present invention using the above-described semiconductor device test apparatus 1 will be described.
The test according to the present embodiment is one of AC characteristic tests for checking the operation performance of an LSI, and includes, for example, a maximum operation clock frequency (operation performance of an internal logic block), a clock input duty (1 in one cycle). Or a ratio of 0 input period), input / output propagation delay time (time from input of certain data until data of output pin changes), transition time of output waveform, and the like.

FIG. 2 is a diagram for explaining the test method of the present invention using the test apparatus 1. FIG. 2A shows a DUT
2 and output pattern 20 and threshold value 14Sb
2B shows the window strobe signal 15Sb output from the timing generator 15 to the pattern comparator 17.

The window strobe function, which is a function of a commercially available LSI tester, will be described. As shown in FIG. 2, the window strobe function continuously compares the output pattern 20 with the threshold value 14Sb during the window strobe signal 15Sb (determination period).

The above-mentioned window strobe function, for example, as shown in FIG. 2A, outputs an LSI having a large output pulse width such that all output patterns are detected within the determination period as follows. It is usually used for testing. For example, when the expected value of the output pattern is set to high in the comparison with the threshold value 14Sb, the output pattern 20 is output in all of the determination period.
When the value of the output pattern 20 exceeds the threshold value 14Sb, it is determined as a pass (Pass), and the value of the output pattern 20 is set to the threshold value 1
If it is lower than 4Sb, it is determined as Fail. Conversely, the expected value of the output pattern is set to low (Lo).
When set to w), the pass is determined when the value of the output pattern 20 is lower than the threshold 14Sb in all of the determination periods, and when the value of the output pattern 20 is higher than the threshold 14Sb at any one point. Is a function for determining a failure. In the case of an LSI test in which the pulse width is large and all the output patterns are detected within the window strobe signal period, whether the pulse exceeds a predetermined threshold is maintained. This is effective for testing whether (the expected value is set to high) or whether the state below the predetermined threshold is maintained (the expected value is set to low).

However, when testing an LSI in which the pulse width of the output pattern is very small, usually, in order to detect the output pattern, the width of the window strobe or the like must be reduced to some extent in consideration of variations in the semiconductor process. In order to provide a margin, it is only necessary to be able to determine whether or not a predetermined threshold value is exceeded when an output pattern is detected during the window strobe period.

Therefore, in the present invention, the setting is made so that the following judgment can be made. That is, in the present invention, when testing an LSI having a small output pattern pulse width, for example, an LSI whose output pattern exceeds a predetermined threshold is regarded as a non-defective product, and an LSI whose output pattern does not exceed a predetermined threshold is determined as non-defective. When it is determined that the product is good, the setting is made as follows. That is, in comparison with the threshold value 14Sb, the expected value of the output pattern is set to high (Hig).
h), when the value of the output pattern 20 exceeds the threshold value 14Sb even at one location during the determination period, the pass (P
ass) and the output pattern 20 throughout the determination period.
Is smaller than the threshold value 14Sb, a failure (Fa)
il).

Conversely, for example, when it is desired to determine an LSI whose output pattern is lower than the predetermined threshold 14Sb as a non-defective product and to determine an LSI whose output pattern is not lower than the predetermined threshold 14Sb as a defective product, the following process is performed. Set to That is, in the comparison with the threshold value 14Sb, when the expected value of the output pattern is set to low, if at least one of the values of the output pattern 20 is lower than the threshold value 14Sb during the determination period, it is determined to be a pass. If the value of the output pattern 20 exceeds the threshold value 14Sb throughout the determination period, it is set so as to determine a failure. In the present invention, the above-described function is performed by the pattern comparator 17 and the CPU
11 is executed.

FIG. 3 shows an example of a test method using the test apparatus 1 for a semiconductor device. In FIG.
3A to 3D show, for example, different DUTs 2 respectively.
, The same test pattern is input to the DUT 2 and response output patterns (20a, 20b, 20c, 20
d) and the threshold value 14Sb.
(E) shows the waveform of the window strobe signal 15Sb.

As described above, the width of the window strobe signal 15Sb (determination period) and the deviation from the input pattern are created in advance by a logical simulation, and are output to a test pattern for measuring the DUT 2. The threshold value 14Sb of the pattern is also created in advance by a logic simulation or the like.

For example, in this test, a product whose output pattern from the DUT 2 exceeds a predetermined threshold value 14Sb is determined as a non-defective product. Therefore, DUs having output patterns (20a, 20b) as shown in FIGS.
At T2, the output pattern (20a, 20b) is detected within the window strobe range (within the determination period) and exceeds the predetermined threshold value 14Sb, which means that the output pattern is good. In addition, the DUT 2 having the output pattern 20c as shown in FIG. 3C is defective because the output pattern 20c is detected within the determination period but does not exceed the threshold value 14Sb. FIG. 3 (d)
DUT2 having an output pattern 20d as shown in FIG.
Although the output pattern 20d exceeds the threshold value 14Sb,
Since the input / output propagation delay time is long and is not detected within the determination period, it is a defective product.

The above-mentioned determination of good or bad of the DUT 2 is performed as follows. That is, in comparison with the threshold value 14Sb, the expected value of the output pattern is set to High. When testing with the expected value set to high, (a)
(B) is a threshold value 14S within the window strobe width.
b, there is a portion that goes high, so that the path is determined. On the other hand, in (c) and (d), the portion that goes high beyond the threshold value 14Sb within the window strobe 15Sb range. Since it does not exist, it is determined to be failed. Thus, (a) and (b) can be determined as non-defective products, and (c) and (d) can be determined as defective products.

According to the test apparatus and the test method for a semiconductor device of the embodiment of the present invention, when the pulse width of the output pattern from the semiconductor device under test (DUT) is very small, the output pattern from the DUT is May not be determined to be a predetermined threshold value, or an output pattern may not be detected within a predetermined window strobe period. Further, even when the pulse width of the output pattern is very small, the output pattern is detected within the window strobe period and the output pattern exceeds the predetermined threshold value.
The UT can be determined as good. Therefore, even when the pulse width of an output pattern such as an output waveform with a high frequency or a narrow duty is very small, the test can be reliably performed, so that defective products can be prevented from being shipped, and the cost required for it can be reduced. Can be reduced.

Embodiments of the semiconductor device test apparatus and test method of the present invention are not limited to the above description. For example, the semiconductor device that can be tested in the present invention is applicable to both digital ICs and analog ICs. In addition, various changes can be made without departing from the gist of the present invention.

[0045]

According to the test apparatus and test method for a semiconductor device of the present invention, an output waveform having a small pulse width can be reliably tested, and the cost of the test apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device test apparatus according to an embodiment.

FIG. 2 is a diagram for explaining a test method of the present invention.

FIG. 3 shows an example of a test method using the semiconductor device test apparatus of the present invention.

FIG. 4 is a diagram for explaining a problem in a test of an LSI having a high-frequency output waveform according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Test apparatus, 11 ... CPU, 12 ... I / O device, 13
... Storage device, 14 ... Pattern generator, 14Sa ... Pattern signal, 14Sb ... Threshold (signal), 15 ... Timing generator, 15Sa ... Clock pulse, 15Sb ... Window strobe signal, strobe signal, 16 ... Format controller, 17 ... Pattern Comparator, 18 pin interface section, 19 programmable power supply, 20,
20a, 20b, 20c, 20d, 30 ... output patterns.

Claims (4)

[Claims] An apparatus for testing a semiconductor device for determining whether or not the semiconductor device is defective according to an output signal from the semiconductor device, comprising: comparing the output signal with a predetermined set value continuously for a certain period of time; If the value of the output signal does not exceed the set value throughout the fixed period, a first determination of good or bad is made to the semiconductor device, and the output signal exceeds the set value during the fixed period. A test device for a semiconductor device having a comparison / determination unit that makes a second determination different from the first determination on the semiconductor device when there is a value of? 2. A test signal for outputting the output signal is generated and output to the semiconductor device, and the value of the output signal from the semiconductor device is continuously compared with a predetermined value for the predetermined period. A test signal generation unit that generates a comparison signal and outputs the comparison signal to the comparison determination unit, wherein the comparison determination unit compares the value of the output signal with the set value based on the comparison signal. 2. The test device for a semiconductor device according to claim 1. 3. The test signal generator includes: a pattern generator that generates a pattern signal indicating the type of waveform of the test signal; and a timing that generates a timing signal that determines the rising and falling timings of the test signal. 3. The test apparatus for a semiconductor device according to claim 2, further comprising: a generating unit; and a format unit that generates the test signal from the pattern signal and the timing signal. 4. A predetermined test signal is input to a semiconductor device, and a value of an output signal from the semiconductor device output in response to the input of the test signal is continuously compared with a predetermined set value for a predetermined period. Then, when the value of the output signal does not exceed the set value throughout the fixed period, a first determination of good or bad is performed for the semiconductor device, and the semiconductor device exceeds the set value during the fixed period. If there is an output signal value,
A method of testing a semiconductor device, wherein a second determination different from the first determination is performed on the semiconductor device.