JP3243581B2 - Active matrix liquid crystal light valve - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an active device.
active matrix liquid crystal light valve (AMLC) that switches the liquid crystal cell by element
V), a liquid crystal display (LCD) having the light valve, and an image information processing apparatus having the LCD.

[0002]

2. Description of the Related Art Conventionally, an AM having an active element is provided.
A liquid crystal display element LCD as an LCV is widely used when a twisted nematic (TN) liquid crystal is used,
It has been commercialized as a flat panel display or as a projection television. The above-mentioned active element represented by a thin film transistor (TFT), a diode element, a MIM (metal insulator metal) element, etc., has a switching characteristic.
By maintaining a voltage applied state for a TN liquid crystal having a relatively slow response longer than a substantial line selection cycle, the response of the liquid crystal to an optical switch is assisted. In addition, for a liquid crystal having no memory property (self-holding property) such as a TN liquid crystal, the above-described voltage application state holding causes a unit cell to have a substantial memory state for one frame. The LCD can provide good display characteristics without crosstalk between lines and pixels in principle.

In recent years, development of a ferroelectric liquid crystal (FLC), which has a several-digit response speed faster than that of a TN liquid crystal, has been advanced, and a display panel, a light valve, and the like using the same have been announced. Here, by driving the FLC with the active matrix element, a better display element may be obtained. Examples of the combination of the FLC and the TFT include U.S. Pat. No. 4,840,462 and Proceeding of the SDD, Vol.
89, "Ferroelectric Liquid-Crystal
Video Display "(Proceeding of
theSID, vol. 30, 1989, "Ferr
olive Liquid-Crystal
Video Display ”).

FIG . 11 shows a circuit of a conventional liquid crystal display device.

[0005] A circuit shown in FIG . 11 includes a liquid crystal cell 701 in which a liquid crystal material is sealed between a common electrode COM and each pixel electrode CE.
A signal line 703 for transmitting a video signal, a line buffer 704, a shift pulse switch 708, a horizontal shift register 705, a gate line 711 for transmitting a gate signal, and a vertical shift register 706. The video signal is 70
7 is sequentially transferred to each pixel or each line at a shifted timing from the signal input end of the pixel 7.

FIG. 12 shows the drive pulse timing of the conventional active matrix liquid crystal display device shown in FIG. The drawing shows a line sequential driving method. That is, the video signal S _V to be recorded on the liquid crystal is transferred to the buffer unit via the shift pulse switch 708 driven by the horizontal shift register 705 indicating an output synchronized with the frequency of the video signal, and the video signal for one line is stored in the buffer unit. Be recorded. After the video signals of all the pixels in a certain line are recorded in the line buffer unit 704, the video signals are recorded in each liquid crystal cell through the output switch of the line buffer unit 704 and the pixel switch turned on by the vertical shift register 706. Signal transfer to each liquid crystal cell is generally during the blanking period of the horizontal run period, signal transfer is performed collectively by the pulse phi _T for a horizontal line. At the above timing, the video signal is sequentially transferred to each line.

With respect to the signal voltage thus transferred,
As the liquid crystal molecules constituting the cell move, the transmittance of the liquid crystal cell changes depending on the direction of a polarizing plate separately provided in relation to a cross polarizer. This is shown in FIG.

The meaning of the signal voltage value shown on the horizontal axis in FIG. 13 differs depending on the liquid crystal used. For example, when a TN liquid crystal is used, the value is defined as an effective voltage value (V _rms ). A qualitative description of this value will be given with reference to FIG. In order to prevent a DC component from being applied to the liquid crystal for a long time, there is a method of applying a signal by changing the polarity of the signal voltage for each frame. In this case, the liquid crystal itself operates according to the AC voltage component indicated by the hatched portion in the figure. Therefore, _assuming that the effective voltage V _rms is t _{F for} a time corresponding to two frames and V _LC (t) is a signal voltage transferred to the liquid crystal.

[0009]

(Equation 1) Is represented by On the other hand, the FLC liquid crystal is generally driven by a DC voltage. For example, FLCs having a bistable state (such liquid crystals are preferably chiral smectic liquid crystals and chiral smectic C
Phase (SmC *) or H phase (SmH *) and SmI *,
Chiral smectic liquid crystals such as SmF * and SmG * are suitable. ), The driving waveform is as shown in FIG. That is, the signal voltage before writing the signal, once reset by the reset voltage V _R to one of the state of the bistable states, then the write voltage signal (V
_M ). The signal voltage that contributes to the transmittance in FIG. 13 is also indicated by hatching. Unlike TN liquid crystal,
The DC component of the write voltage becomes the signal voltage as it is.

When the driving method shown in FIG. 12 is used, the voltage of the pixel electrode changes depending on the signal voltage, but is always positive with respect to the potential of the common electrode of the liquid crystal, and the state where the DC voltage component is always applied to the liquid crystal cell. Is the same as In particular, T
When an N-type liquid crystal is used, this direct current component causes burn-in of liquid crystal molecules.

One method of removing the DC voltage component is a one-frame inversion driving method of a signal voltage as shown in FIG. The N-th signal voltage is applied so as to be in the positive direction with respect to the potential of the common electrode, and the (N + 1) -th signal voltage is applied so as to be in the negative direction. By inverting the polarity of the signal voltage with respect to the common electrode potential for each frame as described above, the DC voltage component applied to the liquid crystal cell is cancelled, and the burn-in of the liquid crystal molecules can be prevented.

With the same operation and effect, there are an inversion driving method for each 1H period, an inversion driving method for each pixel, and the like. However, such a conventional inversion driving method has a new technical problem to be solved as follows.

Assuming that the maximum value of the signal voltage is V _MAX , in the case of inversion driving, the shift register section must have the ability to transfer a signal having an amplitude twice V _MAX , regardless of the method described above. Can be Naturally, the shift register section is required to have a higher ON-state breakdown voltage.

As one of means for relaxing the withstand voltage condition,
Although it is conceivable to lower the maximum amplitude of the signal voltage, in the case where high definition is required such as a high-vision display which is expected to spread rapidly in the future, the same means as shown in FIG. Is difficult, which is not desirable.

[0015]

As another means for alleviating the withstand voltage condition, a transistor constituting a shift register is provided with an LDD (lightly doped drain).
n) It is conceivable to use a MOS transistor having a high withstand voltage structure such as a structure as a switch. However, these high withstand voltage type MOS transistors which have been devised at present are added in series to a source and a drain in exchange for improvement of withstand voltage. However, there is a problem that the transconductance gm decreases due to an increase in resistance. As mentioned earlier, in the future LCV
As in the case of high-vision displays, high-speed driving is increasingly required, and a larger gm is also required for a TFT as an active element. Further, the MOS transistor having the high withstand voltage structure as described above requires a complicated process, and lowers the yield in forming a shift register, resulting in a relatively high manufacturing cost.

On the other hand, apart from the above-mentioned problem of the withstand voltage, it is required to improve the driving speed in order to display a good image. In particular, when performing the line sequential driving, it is required to increase the writing speed to the line buffer. To this end, it is conceivable to increase the frequency of the shift pulse, but this is naturally limited by the circuit shown in FIG. 11 and the driving method shown in FIG.

In particular, as the amount of information increases, this problem increases the load on software, and also increases the amount of memory in peripheral devices and the load on hardware such as a microprocessor (MPU).

[0018]

SUMMARY OF THE INVENTION It is a first object of the present invention to solve the above-mentioned technical problem relating to the withstand voltage by improving a driving circuit.

A second object of the present invention is to solve the technical problem relating to the signal processing speed independent of the above-mentioned problem relating to the withstand voltage by improving the driving circuit and the driving timing.

A third object of the present invention is to suppress an increase in the scale of a peripheral device or an increase in software complexity.

[0021]

SUMMARY OF THE INVENTION The first and third objects described above are for transferring a signal to be applied to a cell in an active matrix light valve having a plurality of cells each having a liquid crystal and an active element. the circuit for driving the switch have a boosting means for boosting the output of the shift register and the shift register, said boosting means comprises first
MOS transistor, first capacitor and second MOS
And a first MOS transistor.
Gate and source connected to first output of shift register
And the first electrode of the capacitor is connected to the second electrode of the shift register.
Output and the gate of the second MOS transistor
Connected to the third output of the
The first MOS transistor connected to the reset power supply line
A drain of the transistor and a second electrode of the first capacitor.
The drains of the second MOS transistors are connected to each other.
Or the step-up means comprises a fourth MOS
Transistor, fifth MOS transistor and sixth MO
A fourth MO having an S transistor and a second capacitor;
The source of the S transistor is connected to the power supply line, and the gate is
The fourth MO is connected to the first output terminal of the shift register.
Drain of S transistor and fifth MOS transistor
Of the second capacitor and the first electrode of the second capacitor.
Connected. The second electrode of the second capacitor is
6th MOS connected to the second output terminal of the
The source of the transistor is connected to the reset power line,
Port is connected to the third output terminal of the shift register,
Fifth, drains of the sixth MOS transistors are connected to each other
This is achieved by a light valve characterized in that:

The first and third objects have liquid crystal display means in which a plurality of cells each having a liquid crystal and an active element are arranged two-dimensionally, and a drive circuit for driving the display means. The drive circuit includes a switch for transferring a signal applied to the plurality of cells, a shift register that generates a shift pulse, and a booster circuit that boosts a voltage of the shift pulse of the shift register. Driving the switch by inputting an output of a booster circuit to the switch , wherein the booster circuit includes a first MOS transistor
And the first capacitor and the second MOS transistor
And the gate and source of the first MOS transistor are
Connected to the first output of the shift register and to the first output of the capacitor.
One electrode is connected to the second output of the shift register,
The gate of the MOS transistor is connected to the third
Output, and the source is an independent reset
Connected to the source line, the drain of the first MOS transistor
And a second electrode of the first capacitor and a second MOS transistor.
The drains of the transistors are connected to each other,
The booster circuit includes a fourth MOS transistor and a fifth MOS transistor.
MOS transistor, sixth MOS transistor and
And the fourth MOS transistor
Source is connected to the power supply line, and the gate is
1 output terminal and connected to the fourth MOS transistor.
Rain and source and gate of fifth MOS transistor
And the first electrodes of the second capacitor are connected to each other.
You. The second electrode of the second capacitor is connected to the
2 output terminal and connected to the source of the sixth MOS transistor.
Source is connected to the reset power supply line, and the gate is
The fifth and sixth MOS transistors are connected to the third output terminal of the
The invention is achieved by a liquid crystal display element characterized in that drains of transistors are connected to each other , and an image information processing apparatus having the element.

On the other hand, the second and third objects described above include a liquid crystal display means in which a plurality of cells each having a liquid crystal and an active element are two-dimensionally arranged, and a drive circuit for driving the display means. In the liquid crystal display device, the driving circuit includes a switch array for transferring image signals applied to the plurality of cells, and a pulse generation circuit for generating a time-series pulse for sequentially driving the switch array. , the signal is a signal line is provided with a plurality of for input to the switch array, said time chronologically is at least partially overlaps the sequence pulses inputted to the switch array, the pulse generating circuit Emits a shift pulse
Shift register and boost pulse voltage
And a booster circuit for forming the time-series pulse.
And the booster circuit includes a first MOS transistor and a first MOS transistor.
And a second MOS transistor,
The gate and source of the first MOS transistor are shifted
A first electrode of a capacitor connected to a first output of the transistor;
Is connected to the second output of the shift register, and the second MOS
The gate of the transistor is connected to the third output of the shift register.
Connect the source to the independently provided reset power line.
Connected to the drain of the first MOS transistor and the first
The second electrode of the capacitor and the second MOS transistor
The drains are connected to each other, or
The booster circuit includes a fourth MOS transistor and a fifth MOS transistor.
Transistor, a sixth MOS transistor and a second capacitor.
And the source of the fourth MOS transistor is
Connected to the source line, and the gate is connected to the first output terminal of the shift register.
And the drain of the fourth MOS transistor
A source and a gate of the fifth MOS transistor;
The first electrodes of the capacitor are connected to each other. Second
The second electrode of the capacitor is the second output terminal of the shift register
And the source of the sixth MOS transistor is reset.
And the gate is connected to the third shift register.
Fifth and sixth MOS transistors connected to the output terminal
Are connected to each other, and a liquid crystal display element and an image information processing apparatus having the element.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a first embodiment of the present invention, a drive signal pulse input to a switch for transferring a signal to be applied to a liquid crystal cell is boosted by the above-described specific booster circuit. Accordingly, it is possible to omit a complicated structure for improving the withstand voltage of a transistor or the like included in the shift register. This makes it possible to manufacture a high-performance element (device) without lowering the production yield.

On the other hand, in a second embodiment of the present invention, a drive signal pulse for driving a switch corresponding to a plurality of lines by setting a plurality of lines of the signal to be input to a switch array for transferring a signal to be applied to a liquid crystal cell. Are supplied in a time-series manner, and the processing speed of an image (video) signal can be improved by this configuration.

This also makes it possible to manufacture a high-performance device without lowering the production yield. In addition, it is possible to suppress an increase in the scale of software and hardware of the peripheral device.

The present invention is used for a liquid crystal printer, a light valve for a liquid crystal display element, and an image information processing apparatus equipped with the same.

The active element, the transfer switch, the shift register, and the booster used in the present invention are desirably integrally formed on the same substrate as a semiconductor integrated circuit. As such a base, a base having a semiconductor region on an insulating film is preferable. This is because such a base can easily form a light transmission type liquid crystal light valve having a built-in peripheral circuit.

The step-up means in the first embodiment is formed using a transistor, a capacitor element.

On the other hand, a plurality of lines in the second embodiment are supplied with a plurality of element signals constituting a video signal. The component signals are combined into one video signal. In particular, if a color separation signal such as a red signal, a green signal, and a blue signal is used as an element signal, it becomes easy to increase the signal processing speed for forming a complex color image.

More preferably, by adopting the line sequential driving, writing to the line buffer becomes faster, and extra time for performing other time-series signal processing in parallel can be created.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, each embodiment of the present invention will be described specifically and in detail. However, the present invention is not limited to these embodiments, and a design within a range in which the object of the present invention is achieved. This includes changes and replacement of elements.

(Embodiment 1) FIG. 1 shows a drive circuit of an active matrix element based on this embodiment. In FIG. 1, 1
Reference numeral 01 denotes a shift register, and P1 to P7 are output terminals of the shift register 101. 102 is the first MO
It is an S transistor, and its gate and source are connected to the first output terminal P1 of the shift register 101.
Reference numeral 103 denotes a first capacitor, and a first electrode of the capacitor 103 is connected to a second output terminal P2 of the shift register 101. A second MOS transistor 104 has a gate connected to a third output terminal P3 of the shift register 101, and a source connected to a reset power supply line 1 connected to a reference power supply _VRS for providing a reset reference electrode.
05. First MOS transistor 10
2 and the second electrode of the first capacitor 103 and the drain of the second MOS transistor are connected to each other;
It becomes the first output terminal 01. Subsequently, the third output terminal P3, the fourth output terminal P4, and the fifth output terminal P5 of the shift register
A MOS transistor and a capacitor are connected to the same configuration as above, and a second output terminal 02 is provided. Hereinafter, the connection is sequentially shifted by two terminals. Reference numeral 106 denotes a switching transistor controlled by a signal of the shift register.

FIG. 2 shows the operation timing for explaining the specific operation. Each output of the shift register 101 is sequentially output from each terminal without temporally overlapping each other as shown by P1 to P7 in FIG. First, the potential of the output terminal 01 is boosted by the signal of P1 to a voltage lower than the output voltage of P1 by the threshold voltage of the first MOS transistor 102. Subsequently, in response to the signal of P2, the voltage is boosted by the voltage obtained by multiplying the signal voltage of P2 by the capacitor 103 and the gate capacitance of the transistor 106 via the capacitor 103. Here, for example, the output amplitude of P1 to P7 is 7 V, the threshold voltage of first MOS transistor 102 is 1 V, capacitor 10
3 and the gate capacitance of the transistor 106 are set to 0.9, the switching transistor 106
The voltage applied to the gate of
12.3 with respect to the operating voltage 7V of the shift register 101
It is boosted to 1.76 times V.

Output terminal voltage = (7-1) + 7 × 0.9 = 12.3 V With this circuit, the power supply voltage applied to the shift register 101 and each transistor in the circuit remains as low as 7 V. , 12.3 V, and can handle signals with 11 V amplitude.

FIG. 3 is a timing chart when a PMOS is used as the switching transistor 106. Similar effects can be obtained in the case of a PMOS.

(Embodiment 2) FIG. 4 shows a circuit diagram of a second embodiment. In this embodiment, after the circuit of the present invention is connected to the first output terminal P1, the second output terminal P2, and the third output terminal P3 of the shift register, the second output terminal P2, the third output terminal P3, the fourth output terminal The output terminal P4 is sequentially connected to the output terminal P4 while being shifted by one terminal. FIG. 5 shows an operation timing chart of this circuit. As can be seen from the figure, in the case of this circuit, the outputs are output in an overlapping manner for a certain period. However, as shown in FIG. 4, when there are a plurality of signal lines connected by the switching transistor 106, for example, the color panel In the case where there is a signal line for each of R, G, B and each color,
By making the outputs overlap in timing, a higher-speed operation can be realized as compared with the first embodiment.

(Embodiment 3) FIG. 6 is a circuit diagram of a third embodiment. In the present embodiment, the period during which the desired high voltage output can be maintained is limited to the period during which the P2 signal is output in the first embodiment, whereas the period between the output of the P2 signal and the first electrode of the first capacitor and the position of the P2 output terminal of the shift register. A third MOS transistor 601 is interposed therebetween, the source and the gate of this MOS transistor are connected to the P2 output terminal, and the drain is connected to the first electrode of the first capacitor. As described above, even after the output of the P2 signal is completed, the potential on the first electrode side of the capacitor is maintained, and the potential on the second electrode side is also changed to the next P level.
The desired high voltage output can be maintained until three signals are applied. Thus, the period during which the switching transistor can transfer a signal can be extended.

A reset transistor 602 is connected to the first electrode of the first capacitor, and resets the potential of the first electrode when the P3 signal is applied.

(Embodiment 4) FIG. 8 shows a circuit diagram of a fourth embodiment. This embodiment is an embodiment in which a booster circuit is configured using a charge pumping circuit. The fourth MOS transistor 801, the fifth MOS transistor 802, and the sixth
MOS transistor 803 and second capacitor 804
The source of the fourth MOS transistor 801 is connected to the power supply line VDD 805, the gate is connected to the P1 output terminal of the shift register, the drain of the fourth MOS transistor 801 and the source and gate of the fifth MOS transistor 802 And the first of the second capacitors 804
The electrodes are connected to each other. Second capacitor 804
Is connected to the P2 output terminal, the source of the sixth MOS transistor 803 is connected to the power supply line VSS806, the gate is connected to the P3 output terminal of the shift register, the fifth MOS transistor 802 and the sixth MO
The drains of the S transistors 803 are connected to each other and serve as output terminals. FIG. 9 shows an operation timing chart. First, P
The potential of the drain terminal of the fourth MOS transistor 801 is boosted by one signal. Next, the voltage is further boosted by the P2 signal via the capacitor 804 and output. Next, P3
Reset by signal. In this circuit configuration, the same effect as in the above embodiment can be obtained.

When the line-sequential driving method is employed, the output (video signal) of the switching transistor 106 in the first to fourth embodiments described above is used for the line buffer 7 shown in FIG.
04 is supplied to the signal line 70 3 through. Separately, when the pixels are sequentially driven in time series for each pixel, the output is directly sent to the signal line 7 without passing through the line buffer 704.
0 supplied to the 3.

The circuits of the first to fourth embodiments described above are formed on a semiconductor substrate.

FIG. 10 is a schematic diagram showing an image information processing apparatus using an AMLCD according to the present invention.

Reference numeral 1 denotes an AMLCD, in which a display unit 5 is provided at the center of a base 6. FIG. 10 schematically shows the pixel portion as 4 and 4 ′ in an enlarged manner. A drive circuit including a shift register is arranged around the display unit 5. The horizontal drive circuits 3 and 3 ′ connected to signal lines and supplying video signals are arranged above and below the display unit, and the drive circuits 2 and 2 ′ connected to gate lines and generating line selection signals are arranged on the left and right sides of the display unit 5. ing.

The AMLCD 1 is connected to a drive control circuit 10 mounted on another board for controlling these drive circuits. This circuit 10 includes a circuit for separating one video signal into a plurality of element signals (for example, S _VR , S _VG , S _VB ) when designed for the second to fourth embodiments.

The drive control circuit 1 includes a light source 12 and a lighting control circuit including an inverter for controlling lighting of the light source.
0 is connected to the central control circuit 14.

Further, the image information processing apparatus has an optical system 22 including a lens for inputting image information, an image sensor 21 including a photoelectric conversion element, and a drive circuit 20 for driving the image sensor.

In addition, the image information by the image sensor 21 and / or the displayed image information is recorded on a recording medium by a recording control circuit 30 including a recording head 31.

The active matrix liquid crystal display element 1 of the embodiment described above uses a semiconductor substrate having a single-crystal Si layer manufactured by the following method.
A liquid crystal element, a liquid crystal driving circuit, and other peripheral driving circuits can be simultaneously formed on the same substrate. Hereinafter, the method will be described.

The single crystal Si layer of the semiconductor substrate is formed by using a porous Si substrate obtained by making the single crystal Si substrate porous.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 ° are formed in the porous Si substrate, and the density thereof is less than half that of single crystal Si. Nevertheless, its single crystallinity is maintained, and a single crystal Si layer can be epitaxially grown on the porous layer. However, if the temperature is higher than 1000 ° C., rearrangement of the internal holes occurs, and the characteristics of the accelerated etching are impaired. For this reason, the epitaxial growth of the Si layer includes the molecular beam epitaxial growth method and the plasma CV method.
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid crystal growth method, etc. is preferable.

Here, a method for epitaxially growing a single crystal layer after making P-type Si porous will be described.

First, a Si single crystal substrate was prepared, and
It is made porous by an anodizing method using an F solution. The density of single crystal Si is 2.33 g / cm ³ , but the density of the porous Si substrate is changed to 0.6 to 1.1 g / cm ³ by changing the HF solution concentration to 20 to 50% by weight. Can be done. This porous layer is made of P for the following reason.
It is easy to form on the Si substrate.

Porous Si was discovered in the course of research on the electropolishing of semiconductors, and was
In the dissolution reaction of the above, holes are necessary for the anodic reaction of Si in the HF solution, and the reaction is shown as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂
+ 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λ
e ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the number of holes required for dissolving the Si1 atom, and it is assumed that porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, it can be seen that P-type Si containing holes exists.
Can be said to be easily made porous.

On the other hand, it has been reported that high-concentration N-type Si can also be made porous. Therefore, it is possible to make the porous body regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, the density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
The chemical etching rate is significantly increased compared to the etching rate of a normal single crystal layer.

The conditions for making single-crystal Si porous by anodizing are shown below. The starting material of the porous Si formed by anodization is not limited to single crystal Si, but may be Si having another crystal structure.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) Si is epitaxially grown on the porous Si substrate thus formed, and a single-crystal Si thin film is formed. To form
The thickness of the single crystal Si thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, after oxidizing the surface of the single-crystal Si thin film, a base that will eventually constitute a substrate is prepared.
The oxide film on the surface of the single-crystal Si is bonded to the substrate. Alternatively, the surface of a newly prepared single crystal Si substrate is oxidized and then bonded to the single crystal Si layer on the porous Si substrate. The reason why this oxide film is provided between the substrate and the single-crystal Si layer is that, for example, when glass is used as the substrate, the interface level generated by the underlying interface of the Si active layer is higher at the oxide film interface than at the glass interface. This is because the lower the level, the more significantly the characteristics of the electronic device can be improved. Further, only a single crystal Si thin film obtained by etching and removing a porous Si substrate by selective etching described later may be bonded to a new substrate. The lamination is performed so that the respective surfaces can be simply brought into contact with each other at room temperature after washing, so that they cannot be easily peeled off by van der Waals force, but they are further adhered to each other at 200 to 900 ° C., preferably 600 to 900 ° C. Heat treatment under a nitrogen atmosphere at a temperature of 5 ° C. to completely bond.

Further, an Si ₃ N ₄ layer is deposited as an etching prevention film on the whole of the two bonded substrates, and only the Si ₃ N ₄ layer on the surface of the porous Si substrate is removed.
Apiezon wax may be used instead of the Si ₃ N ₄ layer. Thereafter, the entirety of the porous Si substrate is removed by means such as etching to obtain a semiconductor substrate having a thin-film single-crystal Si layer.

A selective etching method for electrolessly wet etching only the porous Si substrate will be described.

As an etching solution having no etching action on crystalline Si and capable of selectively etching only porous Si, a buffered solution such as hydrofluoric acid, ammonium fluoride (NH ₄ F) or hydrogen fluoride (HF) may be used. A mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which hydrofluoric acid or hydrogen peroxide solution is added, a mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which alcohol is added, or a hydrofluoric acid or buffer to which hydrogen peroxide water and an alcohol are added A mixture of difluoric acid is preferably used. The substrate bonded to these solutions is wetted and etched. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding the hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case without addition. Further, by changing the ratio of the hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. In addition, by adding alcohol, bubbles of the reaction gas generated by the etching can be instantaneously removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, and still more preferably 1 to 70% by weight with respect to the etching solution. The NH ₄ F concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, and still more preferably 5 to 80% by weight based on the etching solution.

The HF concentration is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, and still more preferably 5 to 80% by weight, based on the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably set to 1 to 95% by weight, more preferably 5 to 90% by weight, and still more preferably 10 to 80% by weight, and is set within a range in which the above-mentioned hydrogen peroxide solution is exerted.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight with respect to the etching solution.
Hereinafter, it is more preferably 40% by weight or less, and is set within a range in which the effect of the alcohol is exerted.

The temperature is set in the range of preferably 0 to 100 ° C., more preferably 5 to 80 ° C., and still more preferably 5 to 60 ° C.

The alcohol used in this step is not limited to ethyl alcohol, and may be isopropyl alcohol or any other alcohol that can be used in the production process and the like, and can further exhibit the above-mentioned alcohol addition effect.

In the semiconductor substrate obtained in this manner, a single-crystal Si layer equivalent to that of a normal Si wafer is flattened and uniformly thinned, and formed over a large area over the entire substrate.

The single crystal Si layer of the semiconductor substrate is separated by a partial oxidation method or by etching in an island shape, and is doped with impurities to form a p or n channel transistor.

(Embodiment 5) FIGS. 16 and 17 are charts showing a drive circuit of a liquid crystal light valve according to the present invention and its timing.

This embodiment is a partial improvement of the above-described fourth embodiment, and the other configuration except for the improved point is almost the same as that of the fourth embodiment.

In terms of the circuit, by connecting the shift register terminal one stage later, such as connecting the gate of the MOS transistor 803 to the terminal P4, as shown in FIG. ON) and the set timing (OFF) of the next one terminal are temporally reversed, and overlapping periods _T01 and _T02 are sequentially provided. Then, a register operating at a high frequency is employed as the shift register 101. Thus, the processing speed of a signal written to the output side of the switch 106 can be increased.

In this embodiment, the boosting circuit and the overlap driving are combined as in the second and third embodiments. However, in the present invention, the boosting circuit is not provided and only the shift pulse of the shift register is overlapped and no boosting is performed. May be supplied.

[0077]

According to the present invention, it is possible to omit a complicated structure for improving the breakdown voltage of a transistor or the like constituting a shift register, and to manufacture a high-performance element without lowering the manufacturing yield. It becomes possible.

Further, according to the present invention, the processing speed of an image (video) signal can be improved, and a high-performance device can be manufactured without lowering the production yield. In addition, it is possible to suppress an increase in the scale of software and hardware of the peripheral device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a drive circuit of an active matrix liquid crystal light valve according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the drive circuit according to the first embodiment.

FIG. 3 is a timing chart when a PMOS transistor is partially used in the drive circuit according to the first embodiment;

FIG. 4 is a diagram illustrating a drive circuit of an active matrix liquid crystal light valve according to a second embodiment of the present invention.

FIG. 5 is an operation timing chart of the drive circuit according to the second embodiment.

FIG. 6 is a diagram showing a drive circuit of an active matrix liquid crystal light valve according to a third embodiment of the present invention.

FIG. 7 is an operation timing chart of the drive circuit according to the third embodiment.

FIG. 8 is a diagram showing a drive circuit of an active matrix liquid crystal light valve according to a fourth embodiment of the present invention.

FIG. 9 is an operation timing chart of the drive circuit according to the fourth embodiment.

FIG. 10 is a schematic diagram showing the structure of an image information processing apparatus using a liquid crystal light valve according to the present invention.

FIG. 11 is a circuit diagram of a conventional liquid crystal display device.

FIG. 12 is a diagram showing drive pulse timing of an active matrix liquid crystal display element.

FIG. 13 is a diagram showing a correlation between a transmittance of a TN liquid crystal cell and a signal voltage.

FIG. 14 is a diagram showing a driving waveform of an active matrix liquid crystal display device using a TN liquid crystal.

FIG. 15 is a diagram showing driving waveforms of an active matrix liquid crystal display device using a ferroelectric liquid crystal.

FIG. 16 is a diagram showing a drive circuit of an active matrix liquid crystal light valve according to Embodiment 5 of the present invention.

FIG. 17 is an operation timing chart of the drive circuit according to the fifth embodiment.

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/133 550 G02F 1/1368 G09G 3/36 H02M 3/07

Claims (15)

(57) [Claims] 1. An active matrix liquid crystal light valve including a plurality of cells each having a liquid crystal and an active element, wherein a circuit for driving a switch for transferring a signal applied to each cell includes a shift register and a shift register of the shift register. A booster for boosting an output, wherein the booster includes a first MOS transistor and a first key.
A first MOS transistor and a first MOS transistor.
The gate and source of the MOS transistor are shifted
The first electrode of the capacitor is connected to the first output of the
Connected to the second output of the
The gate of the transistor is connected to the third output of the shift register
The source is connected to an independently provided reset power line.
And the drain of the first MOS transistor and the first capacitor.
Drain of the second electrode of the capacitor and the second MOS transistor
The active matrix liquid crystal light valves are connected to each other . 2. An active matrix liquid crystal light valve including a plurality of cells each having a liquid crystal and an active element, wherein a circuit for driving a switch for transferring a signal applied to each of the cells includes a shift register and a shift register of the shift register. A booster for boosting an output, wherein the booster includes a fourth MOS transistor and a fifth M transistor.
The OS transistor, the sixth MOS transistor, and the second
With a capacitor, the source of the fourth MOS transistor
Is connected to the power supply line, and the gate is the first output of the shift register.
And the drain of the fourth MOS transistor
And the source and gate of the fifth MOS transistor,
The first electrodes of the two capacitors are connected to each other. No.
The second electrode of the second capacitor is the second output of the shift register
Terminal of the sixth MOS transistor
Connected to the reset power supply line and the gate is
The fifth and sixth MOS transistors are connected to the third output terminal.
The drains of the transistors are connected to each other.
Active matrix liquid crystal light valve that. 3. A liquid crystal display device comprising: liquid crystal display means in which a plurality of cells each having a liquid crystal and an active element are two-dimensionally arranged; and a drive circuit for driving the display means. A switch for transferring a signal to be applied to the plurality of cells, a shift register for generating a shift pulse, and a booster circuit for boosting a voltage of the shift pulse of the shift register; and an output of the booster circuit. A drive circuit that drives the switch by inputting to the switch
The booster circuit includes a first MOS transistor and a first key.
A first MOS transistor and a first MOS transistor.
The gate and source of the MOS transistor are shifted
The first electrode of the capacitor is connected to the first output of the
Connected to the second output of the
The gate of the transistor is connected to the third output of the shift register
The source is connected to an independently provided reset power line.
And the drain of the first MOS transistor and the first capacitor.
Drain of the second electrode of the capacitor and the second MOS transistor
The liquid crystal display elements are connected to each other . 4. A liquid crystal display device comprising: liquid crystal display means in which a plurality of cells each having a liquid crystal and an active element are two-dimensionally arranged; and a drive circuit for driving the display means. A switch for transferring a signal to be applied to the plurality of cells, a shift register for generating a shift pulse, and a booster circuit for boosting a voltage of the shift pulse of the shift register; and an output of the booster circuit. A drive circuit that drives the switch by inputting to the switch
The booster circuit includes a fourth MOS transistor and a fifth M transistor.
The OS transistor, the sixth MOS transistor, and the second
With a capacitor, the source of the fourth MOS transistor
Is connected to the power supply line, and the gate is the first output of the shift register.
And the drain of the fourth MOS transistor
And the source and gate of the fifth MOS transistor,
The first electrodes of the two capacitors are connected to each other. No.
The second electrode of the second capacitor is the second output of the shift register
Terminal of the sixth MOS transistor
Connected to the reset power supply line and the gate is
The fifth and sixth MOS transistors are connected to the third output terminal.
The drains of the transistors are connected to each other.
The liquid crystal display element that. 5. A liquid crystal display device in which a plurality of cells each having a liquid crystal and an active element are arranged two-dimensionally, and a drive circuit for driving the display device, wherein the drive circuit includes the plurality of cells. Including a switch for transferring an image signal to be applied to the shift register, a shift register for generating a shift pulse, and a booster circuit for boosting the voltage of the shift pulse of the shift register. The output of the booster circuit is input to the switch. The liquid crystal display means for driving the switch, and a separate image signal supply means for supplying the image signal to be input to the liquid crystal display means , wherein the booster circuit includes a first MOS transistor and a second MOS transistor. 1 key
A first MOS transistor and a first MOS transistor.
The gate and source of the MOS transistor are shifted
The first electrode of the capacitor is connected to the first output of the
Connected to the second output of the
The gate of the transistor is connected to the third output of the shift register
The source is connected to an independently provided reset power line.
And the drain of the first MOS transistor and the first capacitor.
Drain of the second electrode of the capacitor and the second MOS transistor
The image information processing apparatuses are connected to each other . 6. A liquid crystal display device in which a plurality of cells each having a liquid crystal and an active element are two-dimensionally arranged, and a drive circuit for driving the display device, wherein the drive circuit includes the plurality of cells. Including a switch for transferring an image signal to be applied to the shift register, a shift register for generating a shift pulse, and a booster circuit for boosting the voltage of the shift pulse of the shift register. The output of the booster circuit is input to the switch. a liquid crystal display means for driving said switch by, anda separate the image signal supply means for supplying the image signal to be input to the liquid crystal display unit, the booster circuit includes a fourth MOS transistor first M of 5
The OS transistor, the sixth MOS transistor, and the second
With a capacitor, the source of the fourth MOS transistor
Is connected to the power supply line, and the gate is the first output of the shift register.
And the drain of the fourth MOS transistor
And the source and gate of the fifth MOS transistor,
The first electrodes of the two capacitors are connected to each other. No.
The second electrode of the second capacitor is the second output of the shift register
Terminal of the sixth MOS transistor
Connected to the reset power supply line and the gate is
The fifth and sixth MOS transistors are connected to the third output terminal.
The drains of the transistors are connected to each other .
That image information processing apparatus. 7. The image information processing apparatus according to claim 5, wherein the image information processing apparatus further includes an image sensor that generates information based on the image signal. 8. The image information processing apparatus according to claim 5, further comprising a recording unit that records information corresponding to the image signal on a recording medium.
An image information processing apparatus according to any one of the preceding claims. 9. A liquid crystal display device comprising: liquid crystal display means in which a plurality of cells each having a liquid crystal and an active element are two-dimensionally arranged; and a drive circuit for driving the display means. A drive circuit including a switch array for transferring image signals to be applied to the plurality of cells, and a pulse generation circuit for generating a time-series pulse for sequentially driving the switch array , wherein the pulse generation circuit is Shift, generate shift pulse
The voltage of the register and the shift pulse are boosted, and the time series
A booster circuit for forming a pulse, wherein the booster circuit includes:
A first MOS transistor, a first capacitor, and a second
A first MOS transistor
The gate and source of the star are connected to the first output of the shift register.
And the first electrode of the capacitor is the
2 and the gate of the second MOS transistor
Is connected to the third output of the shift register and the source is independent
Connected to the reset power supply line provided in the first MOS
The drain of the transistor and the second capacitor of the first capacitor
The pole and the drain of the second MOS transistor are connected to each other
And a plurality of signal lines for inputting the signals to the switch array, wherein the time-series pulses are input to the switch array at least partially overlapped in a time-series manner. Display element. 10. A liquid crystal display device comprising: a liquid crystal display means in which a plurality of cells each having a liquid crystal and an active element are two-dimensionally arranged; and a drive circuit for driving the display means. A drive circuit including a switch array for transferring image signals to be applied to the plurality of cells, and a pulse generation circuit for generating a time-series pulse for sequentially driving the switch array , wherein the pulse generation circuit is Shift, generate shift pulse
The voltage of the register and the shift pulse are boosted, and the time series
And a booster circuit for forming a pulse.
Fourth MOS transistor and fifth MOS transistor
Having a sixth MOS transistor and a second capacitor,
The source of the fourth MOS transistor is connected to the power supply line.
And the gate is connected to the first output terminal of the shift register.
And the drain of the fourth MOS transistor and the fifth MO
A source and a gate of the S transistor, and a second capacitor
Are connected to each other. Second capacitor
Of the shift register is connected to the second output terminal of the shift register.
The source of the sixth MOS transistor is a reset power supply.
Line, the gate is the third output terminal of the shift register
And drains of the fifth and sixth MOS transistors
Are connected to each other and provided with a plurality of signal lines for inputting the signals to the switch array, and inputting the time-series pulses to the switch array at least partially overlapping in time series. Characteristic liquid crystal display element. 11. The liquid crystal display device according to claim 9, wherein the signal is a plurality of color separation signals. 12. A liquid crystal display device in which a plurality of cells each having a liquid crystal and an active element are arranged two-dimensionally, and a drive circuit for driving the display device, wherein the drive circuit comprises:
A switch array for transferring the image signal to be applied to the plurality of cells, when for sequentially driving the switch array
A pulse generating circuit for generating a series pulse , wherein a plurality of signal lines for inputting the signal to the switch array are provided, and the switch is configured to at least partially overlap the time series pulse in a time series. Liquid crystal display means for inputting to the array, and separate image signal supply means for supplying the image signal to be input to the liquid crystal display means , wherein the pulse generation circuit generates a shift pulse.
The voltage of the register and the shift pulse are boosted, and the time series
A booster circuit for forming a pulse, wherein the booster circuit includes:
A first MOS transistor, a first capacitor, and a second
It consists of a MOS transistor data, the first MOS transients
The gate and source of the star are connected to the first output of the shift register.
And the first electrode of the capacitor is the
2 and the gate of the second MOS transistor
Is connected to the third output of the shift register and the source is independent
Connected to the reset power supply line provided in the first MOS
The drain of the transistor and the second capacitor of the first capacitor
The pole and the drain of the second MOS transistor are connected to each other
An image information processing apparatus, comprising: 13. A liquid crystal display device in which a plurality of cells each having a liquid crystal and an active element are arranged two-dimensionally, and a drive circuit for driving the display device, wherein the drive circuit comprises:
A switch array for transferring the image signal to be applied to the plurality of cells, when for sequentially driving the switch array
A pulse generation circuit that generates a series pulse, and a plurality of signal lines for inputting the signal to the switch array are provided. Liquid crystal display means for inputting to the array, and separate image signal supply means for supplying the image signal to be input to the liquid crystal display means , wherein the pulse generation circuit generates a shift pulse.
The voltage of the register and the shift pulse are boosted, and the time series
A booster circuit for forming a pulse, wherein the booster circuit includes:
Fourth MOS transistor and fifth MOS transistor
And a sixth MOS transistor and a second capacitor.
The source of the fourth MOS transistor is connected to the power supply line
And the gate is connected to the first output terminal of the shift register.
And the drain of the fourth MOS transistor and the fifth MO
A source and a gate of the S transistor, and a second capacitor
Are connected to each other. Second capacitor
Is connected to the second output terminal of the shift register.
The source of the sixth MOS transistor is a reset power supply.
Line, the gate is the third output terminal of the shift register
And the drains of the fifth and sixth MOS transistors
The image information processing apparatuses are connected to each other . 14. The image information processing apparatus according to claim 12 or 13, characterized in that it has an image sensor for generating the image information processing apparatus is further based on the image signal information. 15. The image processing apparatus according to claim 12, wherein the image information processing apparatus further includes a recording unit that records information corresponding to the image signal on a recording medium.
The image information processing apparatus according to claim 1.