JP3241622B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL having an active filter as a low-pass filter.
(Locked loop) circuit.

[0002]

2. Description of the Related Art In recent years, an active filter has been
LL circuits are increasingly configured. Hereinafter, a conventional PLL circuit of this type will be described. FIG. 2 shows a circuit diagram of a conventional PLL circuit. In FIG. 2, 1 is an operation
Amplifier (hereinafter referred to as an operational amplifier ) , 2 is a phase comparator (PD), 3 is a voltage controlled oscillator (VCO), 4, 5, 7
Is a resistor, 6 is a capacitor, and Vi is an external input signal serving as a reference signal to be locked.

[0003] Here, the voltage controlled oscillator 3 oscillates at a frequency corresponding to the control input voltage. The phase comparator 2 compares the phase of the output signal of the voltage controlled oscillator 3 with the phase of the external input signal Vi, and outputs a signal corresponding to the phase difference between the two signals.
An active filter 8 is composed of the operational amplifier 1, the resistors 4, 5, 7, and the capacitor 6. The low-pass component of the output signal of the phase comparator 2 is extracted and supplied to the voltage controlled oscillator 3 as a control input voltage. The PLL circuit directly outputs the output signal of the voltage controlled oscillator 3 to the phase comparator 2 as shown in FIG.
In some cases, the output signal of the voltage controlled oscillator 3 is once divided by a frequency divider and then applied to the phase comparator 2.

The operation of the PLL circuit configured as described above will be described with reference to FIGS. 3 and 4. FIG. 3 shows the output voltage of the phase comparator 2 until the PLL circuit is locked when there is no offset voltage at the input to the active filter 8, and the input voltage of the voltage controlled oscillator 3 until the PLL circuit is locked. Is shown in FIG.

When the PLL operation starts, the oscillation frequency of the voltage controlled oscillator 3 and the frequency of the external input signal Vi do not match at first, so that the output signal of the phase comparator 2 is a swell of the frequency difference between the two input signals. As a component. Here, it is assumed that the voltage-controlled oscillator 3 sets the output frequency to be higher when the control input voltage is higher, and further assumes that the frequency of the external input signal Vi is higher than the oscillation frequency of the voltage-controlled oscillator 3 in the initial state.

In this case, the output signal of the phase comparator 2 is inverted through the active filter 8 and becomes the input signal of the voltage controlled oscillator 3, so that the output signal voltage of the phase comparator 2 in FIG. When it is lower than 0, the control input voltage of the voltage controlled oscillator 3 increases and the output signal frequency of the voltage controlled oscillator 3 also increases, so that the frequency difference between the two input signals of the phase comparator 2 decreases and the phase comparison The output signal period of the device 2 becomes longer. Conversely, when the output signal voltage of the phase comparator 2 is higher than the predetermined DC voltage 0, the oscillation frequency of the voltage controlled oscillator 3 becomes lower, so that the input signal difference of the phase comparator 2 becomes larger and the phase comparator 2 has a shorter output signal period.

When the output signal of the phase comparator 2 is passed through the active filter 8, the time required for the capacitor 6 to be charged with positive charge on the voltage-controlled oscillator 3 side is longer than the time required for discharging the positive charge. Positive charges accumulate on the voltage-controlled oscillator 3 side of the capacitor 6, the control input voltage of the voltage-controlled oscillator 3 increases, and the oscillation frequency of the voltage-controlled oscillator 3 increases. When the external input signal Vi and the oscillation frequency of the voltage controlled oscillator 3 match, the external input signal Vi and the output signal of the voltage controlled oscillator 3 are fixed at a fixed angle and are locked.

However, the lock voltage in the figure is a control input voltage to the voltage controlled oscillator 3 for outputting the same frequency as the frequency of the external input signal Vi to the voltage controlled oscillator 3,
The lock point is a point in time when the output voltage of the phase comparator 2 and the control input voltage of the voltage controlled oscillator 3 become flat due to the locked state.

[0009]

However, the conventional configuration described above has a drawback that the PLL circuit may not lock when the input to the active filter 8 has an offset voltage. This point will be described with reference to FIGS. FIG. 5 shows the output voltage of the phase comparator 2 until the PLL circuit is locked when the offset voltage is present at the input to the active filter 8, and the input voltage of the voltage controlled oscillator 3 until the PLL circuit is locked. Is shown in FIG.

That is, when there is an offset voltage, for example, when the output voltage of the phase comparator 2 shifts to a higher voltage as shown in FIG.
The time for discharging is longer than the time for charging the positive charge to the side. As a result, there is a possibility that the control input voltage of the voltage-controlled oscillator 3 does not change or shifts in the opposite direction as shown in FIG.

An object of the present invention is to provide a PLL circuit which can be locked even when an input to an active filter has an offset voltage.

[0012]

The PLL circuit of the present invention comprises:
A series circuit of a resistor and a capacitor is connected between the output terminal of the operational amplifier and the non-inverting input terminal so that the active filter is in an oscillation state until the active filter is locked. At this time, the positive feedback loop gain by the series circuit of the resistor and the capacitor is set to be smaller than the negative feedback loop gain by the series circuit of the resistor and the capacitor between the output terminal and the inverting input terminal of the operational amplifier. With this configuration, even if the input voltage to the active filter has an offset voltage, P
The LL circuit can be locked.

[0013]

PLL circuit of the embodiment of the Invention The present invention includes a voltage controlled oscillator, the phase and out of the output signal of the voltage controlled oscillator
A phase comparator for comparing the phase of an external input signal supplied from the section , and an active filter for extracting a low-frequency component of the output signal of the phase comparator and supplying the low-frequency component to a voltage-controlled oscillator as a control input voltage. Then, the active filter, the negative feedback series circuit of a first resistor and a first capacitor connected is between the inverting input terminal and the output terminal of the operational amplifier
Is, positive feedback series circuit of a second resistor and a second capacitor connected is between the output terminal and the non-inverting input of the operational amplifier
Have been. In this case, larger than the first resistor and the first positive feedback loop gain by the positive feedback series circuit of the negative feedback negative feedback loop gain by the series circuit <br/> second resistor and a second capacitor of the capacitor Is done .

According to this configuration, in the unlocked state, the output voltage of the active filter is in the oscillating state, and the output voltage of the active filter passes through a point that matches the voltage to be locked in the PLL circuit, and enters the locked state. At this time, the negative feedback loop is activated, and the locked state can be maintained. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a PLL according to an embodiment of the present invention.
FIG. 2 shows a circuit diagram of a circuit. In FIG. 1, 11 is
An operational amplifier (hereinafter referred to as an operational amplifier ) , 12 is a phase comparator (PD), 13 is a voltage controlled oscillator (VCO), 1
4, 15, 17, and 18 are resistors, 16 and 19 are capacitors, and Vi is an external input signal serving as a reference signal to be locked. Here, the voltage controlled oscillator 13 oscillates at a frequency corresponding to the control input voltage. The phase comparator 12 compares the phase of the output signal of the voltage controlled oscillator 13 with the phase of the external input signal Vi, and outputs a signal corresponding to the phase difference between the two signals.
An active filter 20 is composed of the operational amplifier 11, the resistors 14, 15, 17, 18 and the capacitors 16, 19, and extracts a low-frequency component of the output signal of the phase comparator 12 and supplies the control input voltage to the voltage-controlled oscillator 13. Give as.

When the active filter 20 is configured as described above, the negative feedback does not work when unlocked, the output voltage of the active filter 20 is oscillated by the positive feedback, and the output voltage of the active filter 20 locks the PLL circuit. The lock state is entered when passing through a point that matches the voltage. At the same time as locking, a negative feedback loop gain larger than the positive feedback loop gain is generated, and the locked state is maintained.

The PLL circuit is not limited to the case where the output signal of the voltage controlled oscillator 13 is directly applied to the phase comparator 12 as shown in FIG. After that, it may be added to the phase comparator 12. The operation of the PLL circuit of this embodiment configured as described above will be described in detail.

First, a general active filter is shown in FIG.
Shown in 8, 21 and 22 resistors, 23 a capacitor, 24 is an operational amplifier (hereinafter, op gutter
) , Vin is the input voltage of the active filter, Vou
t is the output voltage of the active filter. This circuit is composed of the operational amplifier 11 and the resistor 1 in the PLL circuit of FIG.
4, 15 and the capacitor 16 and the transfer function Vout / Vin is

[0019]

(1) − (sR22 · C23 + 1) / (sR21 · C23) Here, s is the Laplace operator, R21 is the resistance value of the resistor 21, R22 is the resistance value of the resistor 22, and C23 is the capacitance of the capacitor 23. Here, the circuit of FIG.
FIG. 9 shows a circuit diagram of FIG. Since the output signal of the phase comparator 12 when not locked is not output with respect to the frequency component of the external input signal Vi that is originally subjected to phase detection, the output side (point b) of the phase comparator 12 is considered to be grounded. . Also, when there is no external input signal Vi, the output side (point b) of the phase comparator 12 can be considered to be ground.

Here, the operation of the phase comparator 12 will be supplemented. First, since the output signal of the phase comparator 12 in the unlocked state is not output with respect to the frequency component of the external input signal Vi, the output side (point b) of the phase comparator 12 can be considered as ground. The points will be described. That is, when not locked, the frequency of the voltage controlled oscillator 13 changes arbitrarily and is not constant.
The output of the voltage controlled oscillator 13 and the external input signal Vi are input to the phase comparator 12, and the phase difference is input as a voltage. Here, while the external input signal Vi has a constant frequency, the frequency of the output of the voltage controlled oscillator 13 is arbitrarily changed, so that the output of the voltage controlled oscillator 13 with respect to the frequency component of the external input signal Vi is changed. Since there is no phase difference and the output of the phase comparator 12 is not output for the frequency component of the external input signal Vi, it can be considered as ground (immobile).

Next, the point that the output side (point b) of the phase comparator 12 can be considered to be ground even when there is no external input signal Vi will be described. That is, the phase comparator 12
Converts the phase difference between two input signals into a voltage and outputs the voltage. When there is no external input signal Vi, the output of the phase comparator 12 is not output, so that the output is grounded (immobile).
It can be thought that.

When not locked, point b is in the ground state, and a positive feedback loop gain (gain between point a and GND when signal Vin is input) is applied by adding resistors 17 and 18 and capacitor 19. Then, an oscillation state can be set. By setting the oscillation state, the output of the active filter 20 passes through the lock voltage,
As a result, a locked state is set. When the locked state is established, a negative feedback loop gain is applied, and the locked state can be maintained by setting a constant such that the gain is larger than the positive feedback loop gain.

The active filter 20 is provided with a positive feedback loop only when the external input signal Vi is not input or when the signal is not locked.
This is to make the output of the device oscillate. FIG. 7 shows the input voltage of the voltage controlled oscillator 13 until the PLL circuit enters the locked state when the input to the active filter 8 has an offset voltage. In the case of this embodiment, the output of the phase comparator 12 does not come out when there is no external input signal Vi or when it is not locked.

As described above, according to the PLL circuit of this embodiment, a configuration is adopted in which the series circuit of the resistor 18 and the capacitor 19 is connected between the output terminal of the operational amplifier 11 and the non-inverting input terminal. By oscillating the output of the active filter 20 until the lock, the output voltage of the active filter 20 passes through a voltage that matches the lock voltage. , And that state can be maintained.

[0025]

According to the PLL circuit of the present invention, the second resistor and the second resistor are connected between the output terminal of the operational amplifier and the non-inverting input terminal .
By connecting the positive feedback series circuit of the capacitor No. 2 and setting the positive feedback loop gain smaller than the negative feedback loop gain, the active filter is oscillated until locking, and the negative feedback is performed when the locking operation is started. By activating the loop and releasing the oscillation state, it is possible to lock the input of the active filter even if there is an offset voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

FIG. 2 shows a conventional PLL using an active filter.
FIG. 3 is a circuit diagram illustrating a configuration of a circuit.

FIG. 3 is a time chart showing a change in an output voltage of a phase comparator when there is no offset voltage in a conventional PLL circuit.

FIG. 4 is a time chart showing a change in an input voltage of a voltage controlled oscillator when there is no offset voltage in a conventional PLL circuit.

FIG. 5 is a time chart showing a change in output voltage of a phase comparator when there is an offset voltage in a conventional PLL circuit.

FIG. 6 is a time chart showing a change in an input voltage of a voltage controlled oscillator when there is an offset voltage in a conventional PLL circuit.

FIG. 7 is a time chart showing a change in the input voltage of the voltage controlled oscillator when there is an offset voltage in the PLL circuit of the present invention.

FIG. 8 is a circuit illustrating a configuration of a general active filter.

FIG. 9 is a circuit diagram for obtaining an open loop gain in the PLL circuit of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 operational amplifier 2 phase comparator 3 voltage controlled oscillator 4 resistor 5 resistor 6 capacitor 7 resistor 11 op amp 12 phase comparator 13 voltage controlled oscillator 14 resistor 15 resistor 16 capacitor 17 resistor 18 resistor 19 capacitor 21 resistor 22 resistor 23 capacitor 24 op amp

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Makoto Nakamura 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-63-5561 (JP, A) JP-A-7- 162301 (JP, A) JP-A-53-104147 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/093 H03H 11/04

Claims (1)

(57) [Claims] 1. A voltage controlled oscillator, a phase comparator for comparing a phase of an output signal of the voltage controlled oscillator with a phase of an externally applied external signal, and a low frequency component of the output signal of the phase comparator. An active filter for extracting and providing the voltage-controlled oscillator as a control input voltage to the voltage-controlled oscillator
An L-circuit, wherein the active filter has a first resistor and a negative capacitor connected between an output terminal of the operational amplifier and an inverting input terminal.
A feedback series circuit is connected , a positive feedback series circuit of a second resistor and a second capacitor is connected between an output terminal of the operational amplifier and a non-inverting input terminal, and a loop of the negative feedback series circuit is connected.
Loop gain is larger than the loop gain of the positive feedback series circuit.
A PLL circuit characterized by being set .