JP3240970B2 - Transistor drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor driving device, and more particularly, to a driving device for an upper arm power transistor provided in an H-bridge type DC-AC inverter.

[0002]

2. Description of the Related Art In recent years, opportunities to use OA equipment and the like in automobiles have been increasing. For this purpose, various AC power supplies have been proposed for securing a drive power supply for OA equipment. Generally, this type of AC power supply converts a 12-volt DC power supply of a battery provided in an automobile into an AC power supply with an effective value of 100 volts.

An AC power supply is composed of a DC-DC converter and a D-DC converter.
It has a C-AC inverter. The DC-DC converter intermittently applies the DC voltage to a primary winding of a step-up transformer by using a transistor to generate a high-voltage AC voltage in a secondary winding of the transformer, and outputs the high-voltage AC. The voltage is rectified by a rectifier circuit and converted to a DC voltage. That is, the DC-DC converter boosts the DC power supply voltage of 12 volts of the battery to a DC voltage Vh of 100 to 144 volts, and outputs it to the DC-AC inverter of the next stage.

[0004] The DC-AC inverter converts the boosted DC voltage Vh from the DC-DC converter into an AC voltage having an effective value of 100 volts, and supplies drive power to OA equipment as a load. FIG. 2 shows an electrical configuration of the DC-AC inverter. DC-AC inverter is below made of two-ene <br/> upper arm transistor SW1 consisting Han performs instruction type N-channel MOS transistor, SW3 and two Enha <br/> emissions performs instruction type N-channel MOS transistor An H-bridge circuit including side arm transistors SW2 and SW4 is provided. The H-bridge circuit includes a pair of one upper arm and lower arm transistors SW1 and SW4 and the other upper arm and lower arm transistor SW
By turning on and off the set of 3, SW2 alternately,
An AC voltage is output to an output terminal to supply drive power to a load 10 such as an OA device.

[0005]

By the way, this kind of D
In the H-bridge type circuit of the C-AC inverter, the lower arm transistors SW2 and SW4 are grounded.
The upper arm transistors SW1, SW3 are not grounded and are in a floating state. Therefore, a power supply for driving the upper arm transistors SW1 and SW3 is obtained by converting a DC power supply into an AC power in a power supply circuit 31 composed of a semiconductor integrated circuit device (IC) and supplying the AC power to the transformer T. The rectified DC voltage (isolated power supply voltage) is used. That is, the power supply circuit 31 includes the upper arm transistors SW1, SW
3 is isolated via a transformer T.

A control signal SG1 for driving a transistor for applying the isolated power supply voltage to the gates of the upper arm transistors SW1 and SW3.
1, a switching control circuit 33 for generating SG12 is also isolated via a photocoupler.

As a result, the circuit configuration of the DC-AC inverter becomes large and the cost increases.
As a result, the size and cost of the AC power supply device have been increased.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems. An object of the present invention is to make it possible to drive a transistor in a floating state without using a transformer or a photocoupler by isolating it, and to reduce the cost and size. It is an object of the present invention to provide a transistor driving device capable of achieving high performance.

[0009]

According to a first aspect of the present invention, there are provided first and second upper arm transistors each having one end to which a DC power supply voltage is applied, and first and second upper transistors each having one end grounded.
The other ends of the first upper and first lower arm transistors are both connected to one output terminal, and the other ends of the second upper and second lower arm transistors are both other ends. An H-bridge circuit connected to an output terminal, and a first output to a control terminal of each of the first and second lower arm transistors for alternately turning on and off the first and second lower arm transistors.
And a switching control circuit for generating and outputting a second control signal, and when the first and second control signals turn on the first and second lower arm transistors, respectively, by the first and second control signals. the driving power source at the same first and second control signal generating respective control terminals of said first and second upper arms preparative <br/> transistor causes respectively grounded,
When said first and second control signal turns off the first and second lower arm transistors of the first and second upper arm transistor <br/> data based on the first and second control signals A drive circuit for disconnecting the control terminals from the ground and applying the drive power, respectively.

According to a second aspect of the present invention, in the transistor driving device according to the first aspect, the driving circuit has one end connected to the control terminals of the first and second lower arm transistors and the other end connected to the control terminals of the first and second lower arm transistors. A grounding transistor that is grounded and is turned on / off based on the first and second control signals, a capacitor that charges the first and second control signals as a drive power source, and (2) a backflow prevention diode for supplying a control signal; and a drive power supply for the capacitor so as to turn on the first and second upper arm transistors after the first and second lower arm transistors are turned off. Consists of resistance.

According to a third aspect of the present invention, in the transistor driving device according to the second aspect, the driving circuit includes the first and second lower arm transistors in the first and second upper arm transistors. And a discharge circuit for turning off each of them before turning on.

According to the first aspect of the present invention, when the switching control circuit outputs the first and second control signals for turning on the first and second lower arm transistors, the drive circuit outputs the first and second control signals. The control terminals of the first and second upper transistors are grounded by a control signal, and a drive power supply is generated by the first and second control signals. When the drive circuit outputs first and second control signals for turning off the first and second lower arm switching elements, the drive circuit controls the first and second upper transistors based on the first and second control signals. The terminals are respectively disconnected from the ground, and the first and second upper arm transistors for applying the driving power are turned on.

Therefore, when the first and second lower arm transistors are turned on, the first and second upper arm transistors are grounded, and the driving power of the first and second upper arm transistors is changed to the first and second upper arm transistors. Generated based on the second control signal. When the first and second lower arm transistors are off, the driving power supply is switched to the first
And turn on the second upper arm transistor. As a result, it is possible to drive the first and second upper arm transistors without isolating the first and second upper arm transistors in a floating state by a transformer, a photocoupler, or the like. Can be achieved.

According to the second aspect of the present invention, the grounding transistor is turned on in response to the first and second control signals for turning on the first and second lower arm transistors, respectively, and the first and second upper arm transistors are turned on. The control terminals of the arm transistors are grounded. At this time, the first and second control signals are charged to the capacitor by the backflow prevention diode and the resistor, respectively, as a drive power supply. The grounding transistor is turned off in response to the first and second control signals for turning off the first and second lower arm transistors, and cuts off the control terminals of the first and second upper arm transistors from the ground state, respectively. At this time, the driving power charged in the capacitor is supplied to the control terminals of the first and second upper arm transistors, respectively.

Accordingly, the first and second upper arm transistors can be driven without isolating the first and second upper arm transistors in the floating state by a transformer, a photocoupler, or the like. The size can be reduced.

According to the third aspect of the present invention, the discharging circuit includes the first and second lower arm transistors in the first and second lower arm transistors.
Each of them is turned off before the upper arm transistor is turned on. Therefore, when the first and second upper arm transistors are turned on, no arm short circuit occurs in the H-bridge circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an electrical configuration of the DC-AC inverter. In FIG.
The DC-AC inverter includes an H-bridge circuit 11, a switching control circuit 12 that generates a control signal for driving a transistor included in the H-bridge circuit 11,
Drive circuits 13 and 14 for driving the transistors based on the first and second control signals SG3 and SG4 from the switching control circuit 12 are provided.

[0018] H-bridge circuit 11 comprises two Enhan scan <br/> first and second upper arm transistor consisting instrument type N-channel MOS transistor SWa1, SWa2 and 2
First and second lower arm transistor SWb consisting number of Enhan performs instruction type N-channel MOS transistor
1 and SWb2.

The drain of the first upper arm transistor SWa1 is connected to an input terminal c to which a positive DC voltage Vh is applied. First upper arm transistor S
The source of Wa1 is connected to one output terminal a and to the drain of the second lower arm transistor SWb2. Second lower arm transistor SW
The source of b2 is grounded.

The drain of the second upper arm transistor SWa2 is connected to the input terminal c. The source of the second upper arm transistor SWa2 is connected to the other output terminal b.
And is connected to the drain of the first lower arm transistor SWb1. The source of the first lower arm transistor SWb1 is grounded.

A set of first upper and first lower arm transistors SWa1 and SWb1 and a set of second upper and second lower arm transistors SWa2 and SWb2 are alternately turned on.
By turning off, an AC power supply having an effective value of 100 volts is supplied to the load 15 connected to the output terminals a and b.

Therefore, when the set of the first upper and first lower arm transistors SWa1 and SWb1 is turned on (the second upper and second lower arm transistors SWa2 and SWb1).
The set of b2 is off), plus input terminal c → first upper arm transistor SWa1 → output terminal a → load 15
→ Output terminal b → First lower arm transistor SWb1 →
Current flows through the ground path.

When the pair of the second upper and second lower arm transistors SWa2 and SWb2 is turned on (the first upper and first lower arm transistors SWa1 and SWb1).
Is turned off), and a current flows through the path of the plus input terminal c → the second upper arm transistor SWa2 → the output terminal b → the load 15 → the output terminal a → the second lower arm transistor SWb2 → the ground.

The switching control circuit 12 is composed of a semiconductor integrated circuit device (IC), and receives a power supply induced from a secondary winding of a transformer provided in a DC-DC converter for inputting a DC power supply of a battery. Created 12
A volt DC power supply voltage Vb is input as an operation power supply.
The control circuit 11 has an externally connected capacitor C10 and absorbs fluctuations in the load of the DC power supply voltage Vb of 12 volts. In addition, the switching control circuit 11 includes an oscillation resistor R11 and an oscillation capacitor C11 for determining the on / off cycle of each set of transistors that are turned on / off alternately.
11 is attached externally.

The switching control circuit 12 includes a first control transistor Q1 for controlling the first upper arm transistor SWa1 and the second lower arm transistor SWb2.
And a second control transistor Q2 for controlling the second upper arm transistor SWa2 and the first lower arm transistor SWb1. The first and second control transistors Q1 and Q2 are both bipolar transistors, and both collector terminals are supplied with a DC power supply voltage Vb of 12 volts. The emitters of the first and second control transistors Q1, Q2 are connected to corresponding first and second drive circuits 13, 14, respectively.

First and second control transistors Q1, Q2
Drive signals SG1 and SG2 generated based on the values of the oscillation resistor R11 and the oscillation capacitor C11 in the control circuit 12. The drive signals SG1 and SG2 generated by the control circuit 12 are signals having a constant period and a phase shifted by half a period from each other. In the present embodiment, based on a detection signal from a load current detection device (not shown) that detects a load current flowing through the load 15, the switching control circuit 12 changes the drive signals SG1 and SG2 so that the effective value becomes 100 volts. The duty ratio is changed in the range of 0% to 50%.

When the first and second control transistors Q1 and Q2 are turned on / off by the drive signals SG1 and SG2,
First and second control signals SG3 and SG4 are output to the first and second drive circuits 13 and 14, respectively, based on the first and second control transistors Q1 and Q2. By the way, when the drive signals SG1 and SG2 are at H level and the first and second control transistors Q1 and Q2 are turned on, the first and second control signals SG3 and SG4 are at H level of 12 volts. or,
When the drive signals SG1 and SG2 are at L level and the first and second control transistors Q1 and Q2 are turned off, the first and second control transistors Q1 and Q2 are turned off.
The control signals SG3 and SG4 are at the L level of 0 volt.

Next, the first and second driving circuits 13 and 14 will be described. Note that the first drive circuit 13 and the second drive circuit 14 control the input control signals SG3 and SG4 and the drive control target (the first upper and second lower arm transistors SW).
a1 and SWb2 and the second upper and first lower arm transistors SWa2 and SWb1) are different from each other only in that the circuit configuration is the same. The same parts are denoted by the same reference numerals, and description thereof is omitted.

The first drive transistor Q3 has a base terminal connected to the emitter terminal of the first control transistor Q1 of the switching control circuit 12, and a collector terminal grounded. The base of the first driving transistor Q3
A first resistor R12 is connected between the collector terminals, and a first diode D1 is connected between the base and emitter terminals such that the anode terminal is connected to the base terminal and the cathode terminal is connected to the emitter terminal. The cathode terminal of the first diode D1 is connected to the second resistor R13 and the third
The second lower arm transistor SWb via the resistor R14
2 gate terminals. The second resistor R13 is connected in parallel with a second diode D2 constituting a discharge circuit. A capacitor C13 is connected between the gate and source terminals of the second lower arm transistor SWb2. In the present embodiment, the resistance of the second resistor R13 is 62 kΩ and the resistance of the third resistor R14 is 10 ohm.

Therefore, when the first control transistor Q1 is turned on, the H-level control signal SG3 is supplied to the first diode D
1, applied to the gate terminal of the second lower arm transistor SWb2 via the second and third resistors R13 and R14,
The second lower arm transistor SWb2 is turned on. On the contrary, when the first control transistor Q1 is turned off,
The L-level control signal SG3 is supplied to the first drive transistor Q3
Of the first driving transistor Q3
Turns on. Based on the turning on of the first drive transistor Q3, the gate charge of the second lower arm transistor SWb2 is quickly discharged via the third resistor R14, the second diode D2, and the first drive transistor Q3. As a result, the second lower arm transistor SWb2 is quickly turned off.

Incidentally, after the first control signal SG3 rises to the H level, the second lower arm transistor SWb2
Is longer than the time until the first control signal SG3 is turned on.
Is shorter than the time when the second lower arm transistor SWb2 is turned off after the signal falls to the L level.

The emitter terminal of the first drive transistor Q3 is connected to the gate terminal of the first upper arm transistor SWa1 via a fourth resistor R15, a third diode D3 for preventing backflow, and a fifth resistor R16. An electrolytic capacitor C12 is connected between the cathode terminal of the third diode D3 and the source terminal of the first upper arm transistor SWa1.
Is connected. Also, the first upper arm transistor S
A fourth diode D4 is provided between the gate and source terminals of Wa1.
Are connected, the anode terminal is connected to the source terminal, and the cathode terminal is connected to the gate terminal.

The emitter terminal of the first driving transistor Q3 is connected to the base terminal of a second driving transistor Q4 as a grounding transistor via a sixth resistor R17. The emitter terminal of the second drive transistor Q4 is grounded, and the second drive transistor Q4
A seventh resistor R18 is connected between the base and emitter terminals of the fourth. The collector terminal of the second drive transistor Q4 is connected to the gate terminal of the first upper arm transistor SWa1 via the eighth resistor R19. In the present embodiment, the resistance value of the fifth resistor R16 is 180 kΩ and the resistance value of the eighth resistor R19 is 2.2 kΩ.

Therefore, when the first control transistor Q1 is turned on (when the second lower arm transistor SWb2 is turned on), the first drive transistor Q3 is turned off by the H level control signal SG3, and the second drive transistor Q4 Turns on. When the second driving transistor Q4 is turned on, the electric charge at the gate of the first upper arm transistor SWa1 is discharged via the eighth resistor R19 and the second driving transistor Q4. As a result, the first upper arm transistor S
Wa1 is turned off. At this time, the H-level control signal SG3 is charged to the electrolytic capacitor C12 via the first diode D1, the fourth resistor R15, and the third diode D3.

That is, the first upper arm transistor SW
When a1 is in the off state, the upper arm transistor S
The gate of Wa1 is grounded based on the fact that the second drive transistor Q4 is on and the fifth resistor R16 has a high resistance. In addition, while being grounded, the power supply voltage for turning on the upper arm transistor SWa1 charges the electrolytic transistor C12 based on the H-level drive signal SG3.

Conversely, when the first control transistor Q1 is turned off (when the second lower arm transistor SWb2 is turned off), the first drive transistor Q3 is turned on by the L level control signal SG3, and the second drive transistor is turned on. Q4 turns off. Based on the turning off of the second drive transistor Q4, the charge of the electrolytic transistor C12 is injected into the gate of the first upper arm transistor SWa1, and the upper arm transistor SWa1 is turned on. Since the injection of the charge into the gate is performed through the fifth resistor R16 having a high resistance value of 180 kOhm, the first upper arm transistor SWa1 is turned on relatively slowly. That is, the second lower arm transistor SWb
2 is turned off first, and then the first upper arm transistor SWa1 is turned on.

That is, the first upper arm transistor SW
When a1 is in the ON state, the first drive transistor Q3 is turned on, and the switching control circuit 12 and the electrolytic transistor C12 are isolated by the backflow preventing third diode D3. As a result, the charging voltage of the electrolytic capacitor C12 becomes the first upper arm transistor SW
It is used as a power supply voltage for driving a1.

Therefore, the switching control circuit 12 reliably drives the first upper arm transistor SWa1 in a state of being isolated from the first upper arm transistor SWa1.

The operation of the DC-AC converter configured as described above will be described. Now, when the first control signal SG3 output from the switching control circuit 12 to the first drive circuit 13 rises to the H level, the first diode D
1, the first control signal SG3 is applied to the gate of the second lower arm transistor SWb2 via the second resistor R13 and the third resistor R14 to be turned on. On the other hand, the second drive transistor Q4 is turned on based on the first control signal SG3, and the electric charge at the gate of the first upper arm transistor SWa1 is discharged via the second drive transistor Q4.
Based on this discharge, the first upper arm transistor SWa
1 turns off.

This second lower arm transistor SWb2
, And the turn-off timing of the first upper arm transistor SWa1 is performed earlier than the turn-off timing of the first upper arm transistor SWa1. That is, the turn-on timing of the second lower arm transistor SWb2 is determined by the second resistor R1.
3 and the capacitor 13 and it takes time for the second lower arm transistor SWb2 to turn on. In that respect, the first upper arm transistor S
When the second drive transistor Q4 is turned on, the discharge of the electric charge is started quickly, so that the second lower arm transistor SWb1 is turned off faster than the turn-on. Therefore, there is no state in which the first upper arm transistor SWa1 and the second lower arm transistor SWb2 are simultaneously turned on, so that a problem such as arm short-circuit does not occur.

Further, the charging of the electrolytic capacitor C12 is started based on the first control signal SG3 at the H level. At this time, since the fifth resistor R16 has a high resistance value of 180 kOhm and the second drive transistor Q4 is on, charge injection into the gate of the first upper arm transistor SWa1 based on charging of the electrolytic capacitor C12. Is not done.

On the other hand, the switching control circuit 12 outputs the second drive circuit 14 together with the H-level first control signal SG3.
The second control signal SG4 which falls to the L level. Second control signal SG output to second drive circuit 14
4 falls to the L level, the first drive circuit 14
The driving transistor Q3 turns on. The gate charge of the first lower arm transistor SWb1 is quickly discharged via the third resistor R14, the second diode D2, and the first drive transistor Q3 based on the turning on of the first drive transistor Q3. During this discharge, the switching control circuit 12 and the electrolytic capacitor C12 (upper arm transistor SWa2) are isolated by the third diode D3 for preventing backflow.

Further, based on the turning on of the first driving transistor Q3, the second driving transistor Q4 turns off. Based on the turning off of the second drive transistor Q4, the charge of the electrolytic transistor C12 is changed to the second upper arm transistor SW
The upper arm transistor SWa2 is injected into the gate of a2, and is turned on. Since the injection of the charge into the gate is performed via the fifth resistor R16 having a high resistance value, the second upper arm transistor SWa2 is turned on relatively slowly. That is, after the first lower arm transistor SWb1 is turned off first, the second upper arm transistor SWa2 is turned on.

Therefore, the second upper arm transistor SW
Since there is no state where a2 and the first lower arm transistor SWb1 are turned on at the same time, a problem such as arm short-circuit does not occur.

Thereafter, the first and second driving circuits 13 and 14
Is the first and second control signals SG whose levels alternate.
3 and SG4, the same operation as that of the above-mentioned driving circuit is performed, and each transistor SWa of the H-bridge circuit 11
1, SWb1, SWa2, and SWb2.

Next, the features of this embodiment of the DC-DC converter configured as described above will be described below. In the above embodiment, the second driving transistor Q4
First to turn on the first and second lower arm transistors
And the control terminals of the first and second upper arm transistors are grounded in response to the second control signal. At this time, the first and second control signals SG3 and SG4 are charged to the electrolytic capacitor C12 as driving power sources by the third diode D3 and the fourth resistor R15. Further, the control terminals of the first and second upper arm transistors are cut off from the ground state in response to the first and second control signals for turning off the first and second lower arm transistors by the second drive transistor Q4. I made it. At this time, the charging voltage charged in the electrolytic capacitor C12 by the third diode D3 and the fourth resistor R15 is supplied to the control terminals of the first and second upper arm transistors, respectively.

Accordingly, the first and second upper arm transistors can be driven without isolating the first and second upper arm transistors in a floating state by a transformer, a photocoupler, or the like. Can be achieved.

In the present embodiment, the first and second lower arm transistors SWb1 and SWb2 are turned off before the first and second upper arm transistors SWa1 and SWa2 are turned on, and conversely, the first and second lower arm transistors SWb1 and SWa2 are turned off. The upper and lower arm transistors SWa1 and SWa2 are first and second
The lower arm transistors SWb1 and SWb2 are each turned off before being turned on. Therefore, when the first and second upper arm transistors SWa1 and SWa2 are turned on, and when the first and second lower arm transistors SWb
When 1, SWb2 is turned on, no arm short circuit occurs in the H-bridge circuit.

The embodiment of the present invention is not limited to the above embodiment, but may be implemented as follows. In the above embodiment, the transistor of the H bridge circuit 11 is embodied by a MOS transistor, but may be embodied by a semiconductor switching element such as a bipolar transistor.

In the above embodiment, the first and second drive transistors Q3 and Q4 are implemented by bipolar transistors, but may be implemented by MOS transistors or other semiconductor switching elements.

[0051]

According to the first and second aspects of the present invention, the first and second upper arm transistors can be isolated from the floating first and second upper arm transistors without using a transformer, a photocoupler or the like. Since each of the transistors can be driven, there is an excellent effect that the size can be reduced at low cost.

According to the invention described in claim 3, according to claim 2
In addition to the effects described above, the present invention has an excellent effect of preventing the H-bridge circuit from causing an arm short circuit when the first and second upper arm transistors are turned on.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram illustrating a driving circuit of an H-bridge circuit.

FIG. 2 is an electric circuit diagram illustrating a driving circuit of a conventional H-bridge circuit.

[Description of References] 11 ... H bridge circuit, 12 ... Switching control circuit,
13, 14: drive circuit, 15: load, SWa1, SWa
2. First and second upper arm transistors, SWb1,
SWb2: first and second lower-arm transistors, Q
1, Q2... First and second control transistors, Q3, Q4
... first and second drive transistors, D1 to D3 ... first to first
Third diode, C12: electrolytic capacitor, R16: fifth resistor.

Continuation of front page (56) References JP-A-60-148383 (JP, A) JP-A-5-347546 (JP, A) JP-A-2-106177 (JP, A) JP-A-2-33594 (JP) , U) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H02M 7/5387 H03K 17/687

Claims (3)

(57) [Claims] The first and second upper arm transistors, both having one end to which a DC power supply voltage is applied, and the first and second lower arm transistors, both having one end grounded, are connected to the first upper and lower arm transistors. An H-bridge circuit having the other end of the first lower arm transistor both connected to one output terminal and the other ends of the second upper and second lower arm transistors both connected to the other output terminal; A switching control circuit for generating and outputting first and second control signals respectively output to control terminals of the first and second lower arm transistors to alternately turn on and off the second lower arm transistor; and The first and second control signals correspond to the first and second control signals, respectively.
When the lower arm transistor is turned on, the control terminals of the first and second upper arm transistors are grounded by the first and second control signals, respectively, and the first and second control signals are turned on. the driving power generated respectively Te, the first and second control signals are the first and second lower arm tiger
When turning off the Njisuta, transistor drive apparatus comprising a drive circuit for applying the driving power is shut off from the ground respective control terminals of the first and second control signals to said first and second upper arm transistor based respectively . 2. The transistor driving device according to claim 1, wherein one end of the driving circuit is connected to a control terminal of each of the first and second lower arm transistors and the other end is grounded, respectively. A grounding transistor that is turned on / off based on a second control signal, a capacitor that charges the first and second control signals as a driving power source, and supplies the first and second control signals to the capacitor, respectively. A transistor drive comprising: a backflow prevention diode; and a resistor for supplying a drive power source for the capacitor so that the first and second upper arm transistors are turned on after the first and second lower arm transistors are turned off. apparatus. 3. The transistor driving device according to claim 2, wherein the driving circuit turns off the first and second lower arm transistors before the first and second upper arm transistors turn on. A transistor driving device provided with a discharging circuit for causing a discharge.