JP3240049B2 - Semiconductor laser drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser drive circuit for supplying a bias current to a semiconductor laser diode.

More specifically, the present invention relates to a semiconductor laser driving circuit in which a resistance for detecting a bias current flowing through a laser diode is improved.

[0003]

2. Description of the Related Art As is conventionally known, in order to drive a laser diode, in addition to a modulation current corresponding to an optical signal, a bias current for causing the laser diode to emit light with a minimum light output is always applied. It is necessary to put. FIG. 1A is a diagram showing this fact, and the horizontal axis shows two relationships between the bias current and the modulation current.

FIG. 1B is a diagram showing a circuit configuration for driving the laser diode shown in FIG. In the figure, an input signal corresponding to an optical signal to be transmitted is input to a drive circuit 2 and sent out as a complementary output signal. The complementary output signal output from the drive circuit 2 is input to each gate of two FETs 4A and 4B forming the differential circuit 4. These FETs 4A, 4B
Are connected in common and are connected to the drain of the modulation current control FET 6. The source of the modulation current control FET 6 is connected to the negative power supply.

[0005] Of the two FETs forming the differential circuit 4, the drain of one FET 4 A is directly connected to the positive power supply, and the drain of the other FET 4 B is connected to the cathode of the laser diode 8.

By adjusting the bias voltage applied to the gate of the modulation current control FET 6,
The magnitude of the current flowing between the source and the drain of the modulation current control FET 6 (that is, the modulation current) can be controlled.

Two FETs 4 included in the differential circuit 4
Since complementary output signals are applied to the gates of A and 4B, when one FET is turned on, the other FE is turned on.
T is always off. Accordingly, the modulation current flows into the laser diode 8 or flows from the positive power supply to the negative power supply without passing through the laser diode 8. As a result, the laser diode 8 emits light corresponding to the input signal.

Here, the cathode of the laser diode 8 is also connected to the negative power supply via the bias current monitoring resistor 10 and the drain / source of the bias current control FET 12. Therefore, the bias current control F
By adjusting the bias voltage applied to the gate of the ET 12, the bias current flowing through the laser diode 8 can be controlled. Since this bias current is not turned on / off according to the input current, it is possible to always keep the light emission minimum current value (light emission threshold) of the laser diode 8.

To both terminals of the bias current monitoring resistor 10, interstage resistors 14 and 16 having a high resistance value are connected to detect a voltage drop value at the resistor 10.

In the laser diode driving circuit shown in FIG. 1B, conventionally, a bias current monitoring resistor 10 is provided outside a semiconductor integrated circuit (IC) constituting the driving circuit in order to monitor a bias current. Had been provided.

That is, as a wiring board on which a semiconductor integrated circuit is mounted, it is common to use a ceramic substrate as in the case of an ordinary hybrid IC. Conventionally, in order to provide a resistor on this ceramic substrate, The configuration as shown in FIG. 2 was adopted.

As shown in FIG. 2, the ceramic substrate 2
As the resistor 22 on the zero, a metal oxide powder such as RuO ₂ (ruthenium oxide) is applied in the form of a resistance pattern, which is baked, and a wiring material (wiring metal such as Cu, Au) 24 is put on both ends. It was composed by that. Here, a screen transfer method is generally used for applying the powder.

[0013]

When the above-described bias current monitoring function is performed by the resistor 22 (FIG. 2) on the wiring board, the bias current monitoring resistor 10 (FIG. 1) directly connected to the bias current path is used. The resistance value needs to be as small as about several ohms.
The inter-stage resistors 14 and 16 connected to both ends of the capacitor have a resistance of several kΩ or less so as not to affect the magnitude of the bias current.
It is necessary to have a value of several tens kΩ.

However, if a resistor having such extreme resistance values is to be realized with a single resistor material (ie, a screen resistor formed on a substrate), only one type of sheet resistor is used as the resistor. Therefore, there is a problem that the area occupied by one of the resistors increases.

For example, when the sheet resistance of the resistance material is set to several ohms / square in accordance with the required resistance value of the bias current monitoring resistor 10, a very elongated pattern is formed as the inter-stage resistors 14, 16. Must. Conversely, when the sheet resistance is set to several kΩ / □, a very wide pattern is required for the bias current monitoring resistor 10. As a result, some 1mm
An inconvenient state could occur, which would be □.

In addition, in the case of such a resistor having a large area, the size of the hybrid IC substrate on which the resistor is to be mounted must be large, which is not only a factor that hinders downsizing of the module. , The capacitance between the resistor and the metal formed on the back of the substrate (parasitic capacitance)
Has become large, which has hindered the speeding up of the module.

To cope with such a problem, it is possible to prepare resistance materials having different sheet resistance values, but screen printing must be performed a plurality of times, and this is a practical solution. I can't get it. In addition, the accuracy of each resistor (especially, high accuracy is required for the bias current monitoring resistor) also becomes a problem.

Accordingly, an object of the present invention is to provide
It is an object of the present invention to provide a semiconductor laser drive circuit configured so that the entire module can be miniaturized and high-frequency characteristics do not deteriorate.

[0019]

According to another aspect of the present invention, there is provided a semiconductor laser driving circuit for supplying a bias current to a semiconductor laser diode, the semiconductor laser driving circuit being connected in series with the laser diode. A bias current monitoring resistor that is connected to the bias current and that passes through the bias current; and an external circuit for detecting both ends of the bias current monitoring resistor and a voltage drop in the bias current monitoring resistor due to the bias current. A bias current monitoring resistor and the inter-stage resistance integrated with an element constituting the laser drive circuit.

Here, at least one of the bias current monitoring resistor and the inter-stage resistor can be formed using an impurity implantation layer. Or,
At least one of the bias current monitoring resistor and the interstage resistor can be configured using a metal resistance layer.

As described above, in the semiconductor laser drive circuit according to the present invention, the bias current monitoring resistor and the inter-stage resistance are integrated into an integrated circuit with the elements constituting the laser drive circuit. It is possible to select a resistor having an optimum sheet resistance value from various resistors used inside the semiconductor integrated circuit, and to form each resistor. For example, in a resistor using an injection layer of a transistor, a plurality of types of sheet resistance values can be used depending on the injection conditions.

As a result, not only can the size of the resistor itself be made very small, but also the wiring pattern to this resistor can be made thinner and shorter, so that the effect on the high-frequency characteristics due to stray capacitance or parasitic capacitance, etc. Can be minimized.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 shows a configuration example of a sheet resistor to which the present invention is applied. 1A corresponds to the bias current monitoring resistor 10 shown in FIG. 1B corresponds to the inter-stage resistors 14 and 16 shown in FIG.

First, FIG. 3A will be described. A resistor directly inserted into the bias current path for monitoring the bias current is formed to have a length of 8 μm and a width of 240 μm using the n ⁺ injection layer of the FET. That is,
Since the sheet resistance of the n ⁺ injection layer is 300 ± 10Ω / □, if this layer is used and the length: width = 1: 30, a resistance of 10 ± 2Ω (accuracy 5%) can be obtained. Is possible.

Next, FIG. 3B will be described.
As for the resistance of 3 kΩ used as the inter-stage resistance, an injection resistance layer in the same semiconductor integrated circuit can be used. This layer has a sheet resistance of 500 ± 50Ω / □.
Therefore, if a pattern of length: width = 6: 1 is formed using this sheet resistance (in this example, the length is set to 60 μm and the width is set to 10 μm), then 3000 ± 30.
A resistance of 0Ω (accuracy 10%) is obtained.

FIG. 4 is a view showing a manufacturing process based on a general cross-sectional structure of a semiconductor integrated circuit using an FET (particularly, one using GaAs as a material). Hereinafter, the illustrated steps will be described.

In the first step, semi-insulating GaAs is used.
Using a resist as a mask, an n-type impurity (Si is generally used and Sn or S can be used) is formed in the substrate by a selective ion implantation method. The conditions of the implantation depend on the threshold voltage (characteristic value) of the finally required FET, but generally, the acceleration voltage is 30 keV and the dose is 2.0 to 5.0 × 10 4
¹² / cm ² is used.

In the step (2), in the implantation region formed in the previous step, on both sides except for the future formation of the gate electrode, conditions different from those of the active layer (conditions under which the carrier concentration increases, An n ⁺ layer is formed by increasing the voltage and increasing the number of implanted ions. Specifically, acceleration voltage 1
At a dose of 1.0 to 2.0 × 10 at 00 to 150 keV
¹³ / cm ² . A resist is generally used as a mask for implantation. However, when a future gate electrode is formed in a self-aligned manner with respect to this n ⁺ layer, other materials (SiN, SiO An insulating film such as ₂ ) can also be used.

In the next step, when using an implantation resistor on a circuit, selective ion implantation is performed on the implantation resistance layer, again using a resist as a mask, before the above or another step. The condition depends on the resistance value to be obtained.
A dose of 3.0 to 5.0 × 10 ^{12 at} 50 to 180 keV
/ Cm ² .

Through the above steps, there are three types of resistance values (sheet resistance values) already available on the circuit. That is, an active layer, an n ⁺ layer, and an R layer,
Each sheet resistance value is approximately ~ 3000Ω / □, ~ 3
00Ω / □, up to 500Ω / □.

In the step (3), the entire surface of the substrate is covered with an insulating film, and a heat treatment for activating the ions implanted in the steps (1) to (3) is performed. The conditions are 15 minutes to 30 minutes at 800 ° C. The reason why the surface is covered with the insulating film is to prevent As having a high vapor pressure from being dissociated from the substrate surface during the high-temperature treatment.

In the step (3), after the heat treatment, the FE
Each electrode of T is formed. That is, the drain and source electrodes are formed by forming an ohmic metal of AuGe / Ni on the n ⁺ layer and heat-treating the same at about 400 ° C. to form an alloy.
The gate metal is n ⁺ in the region between the ohmic metals.
A metal of Ti / Pt / Au is formed on the region where the layer is not formed. Various electrode metals are known in addition to these examples. For example, Au as an ohmic metal
Sn, AuGe / Pt / Au, etc. may be used as the gate metal as long as it is a metal that forms a Schottky connection to GaAs, such as Al, Ta, Pt.

Through the above steps, the FET is completed on the GaAs substrate. In a general IC, after completion of the FET, a plurality of wiring layers are provided which are separated from each other by an interlayer insulating film, and are electrically connected only at necessary portions by via holes, thereby forming an actual circuit. Here, a metal resistance layer may be provided during the formation of the wiring layer. Hereinafter, the method will be described with reference to FIG.

In the step (3), a metal resistance layer is formed on the interlayer insulating film of the wiring. The method is not limited to sputtering, vapor deposition and the like. Further, the thickness of the layer depends on the sheet resistance value of the resistor finally required.

In the step (3), a resist is formed on the metal resistance layer so as to cover only necessary portions, and unnecessary portions are removed. As a removing method, trimming, etching, or the like can be used.

In the step (3), after removing the resist, an interlayer insulating film is formed again, a via hole is opened at a predetermined position, and the next wiring forming step is performed. Here, by providing via holes at both ends of the metal resistor layer prepared in the above, the metal resistor can be incorporated into the circuit in the next wiring step.

Effect of Embodiment As described above, a plurality of injection layers, metal resistance layers, and the like are present in the IC as the types of resistors to be incorporated in the circuit. As compared with the case where only one type of screen resistor provided on the (wiring board) is used, the module can be downsized and the high-frequency characteristics can be improved.

For example, a resistor provided on a wiring board has a parasitic capacitance component of up to 3.0 pF, but by using a resistor inside the IC, it is substantially 0 pF (meaning measurement is impossible). 0.1 to judge from various characteristics
pF or less). In addition, regarding the area of the wiring board, it is unnecessary to use a resistor which is conventionally divided by about 4 × 2 mm ² as the resistor. Although the reduction is only about 3% with respect to the entire substrate (25 × 9.5 mm ² ), the elimination of this resistor pattern greatly improves the design tolerance of the layout of other patterns.

[0040]

As described above, according to the present invention, it is possible to obtain a semiconductor laser drive circuit which can be reduced in size as a whole and which does not cause deterioration of high frequency characteristics.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a semiconductor laser drive circuit which is a premise of the present invention.

FIG. 2 is a sectional view showing a resistor formed on a ceramic substrate.

FIG. 3 is an explanatory diagram in a case where two types of sheet resistors are formed by applying the present invention.

FIG. 4 is an explanatory view showing each step to which the present invention is applied.

FIG. 5 is an explanatory view showing each step to which the present invention is applied.

[Explanation of symbols]

 REFERENCE SIGNS LIST 2 drive circuit 4 differential circuit 6 modulation current control FET 8 laser diode 10 bias current monitor resistor 12 bias current control FET 14, 16 interstage resistance

Claims (3)

(57) [Claims] 1. A semiconductor laser drive circuit for supplying a bias current to a semiconductor laser diode, comprising: a bias current monitoring resistor connected in series with the laser diode, the bias current monitoring resistor passing the bias current; And an inter-stage resistor connected between an external circuit for detecting a voltage drop in the bias current monitoring resistor due to the bias current, and the bias current monitoring resistor and the The interstage resistance is
A semiconductor laser drive circuit, which is integrated with an element constituting the laser drive circuit. 2. The semiconductor laser drive circuit according to claim 1, wherein at least one of the bias current monitoring resistor and the inter-stage resistor is formed using an impurity implantation layer. 3. The semiconductor laser drive circuit according to claim 1, wherein at least one of the bias current monitoring resistor and the inter-stage resistor is formed using a metal resistance layer.