JPH05175431A - Monolithic microwave integrated circuit - Google Patents

Abstract

PURPOSE:To make a resistor compact by forming the resistor of several tens of KOMEGA by the selective ion implantation. CONSTITUTION:An N<+> layer, which is to become a source region 102 and a drain region 103 of an FET, is formed on a semi-insulating substrate 101 by selective ion implantation with photoresist 100 as a mask. Then, an FET operating layer 104 and a first resistor 105 are formed by selective ion implantation. Then, a second resistor 106 comprising a P-type layer is formed by selective ion implantation. After the photoresist 100 is removed, capless annealing is performed. Then, a source 107 and a drain 108 of the FET and an electrode 109, which is in ohmic contact with the first resistor, are formed. Thereafter, an electrode 110, which is in ohmic contact with the second resistor, is formed. Since the second sheet resistance is rhos-5,000OMEGA/square, the circuit can be made compact to 1/5 in comparison with a conventional circuit. The selective ion implantation conditions of the layers are as follows: the N<+> layer (Si, 250KeV and 4E12); the P-type layer (Zn<+>, 750KeV and 4E12); and the FET operating layer (Si<+>, 70KeV and 4E12).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic microwave integrated circuit (hereinafter abbreviated as MMIC), and more particularly to improvement of MMIC requiring high resistance.

[0002]

2. Description of the Related Art III-V compound semiconductors, especially GaAs
An MMIC in which a field effect transistor (hereinafter abbreviated as “FET”) using, a resistor, and a capacitor are integrated on one chip is under development as a microwave band amplifier or oscillator, and is partially put into practical use. In recent years, MMICs have been required to operate at low voltage and consume low current.
In addition to the low voltage operation and the improvement in efficiency, a resistance value of several hundreds of KΩ or more has been demanded due to the circuit configuration such as a bias circuit of FET. Generally, the resistors used in the MMIC are metal thin film resistors such as NiCr and TaN, and F.
A semiconductor resistor using an n-type semiconductor layer that can be formed similarly to the ET operation layer, for example, a Si ⁺ ion implantation layer is used. However, the maximum value of these resistances is usually up to several tens of KΩ, and if it is attempted to form a resistance value higher than this, problems such as difficulty in downsizing the circuit and poor reproducibility of characteristics occur. It was not possible to construct an MMIC having a resistance of KΩ or more.

As a conventional example of the present invention, a case of forming a resistor using an n-type semiconductor layer will be described below with reference to FIG.

A photoresist 202 is applied at a predetermined position on the semi-insulating GaAs substrate 201 to form an opening 215 (FIG. 3A). Next, for example, injection energy 70K
Si ⁺ is ion-implanted under the condition of an eV implantation amount of 4E12 cm ⁻² , the photoresist is removed, and then 850 ° C. for 15 minutes
Capless annealing is performed to form the resistance layer 205 (FIG. 3B). Next, Pt / AuGe electrodes 209 are formed on both ends of the semiconductor layer 205 by a lift-off method.
Heat treatment is performed at 50 ° C. to form an ohmic electrode (FIG. 3).
(C)).

The semiconductor resistance value (R) formed by the above method can be expressed by the following equation.

R = ρs · L / W ---------- (1) ρs: Sheet resistance of the resistance layer L: Length of the resistance layer W: Width of the resistance layer Ρs of resistance layer is about 100
Since it is 0Ω □, for example, when L / W = 10, R = 1
A resistance value of 0 KΩ is obtained. It is also possible to change the resistance value by changing the ion implantation condition, that is, ρs of the resistance layer. For example, when a resistance value lower than that in the above example is required, the implantation amount and the implantation energy may be increased. For example, when Si ⁺ ions are implanted under the condition of 250 KeV 4E13 cm ^-2 , ρs is 100Ω □, and when L / W = 1, R is
= 100Ω and L / W = 10, R = 1000Ω is obtained. On the contrary, when a high resistance value is required, the injection amount and the injection energy may be reduced. However, when the injection amount is reduced, the carrier concentration (n) decreases,
Due to the electron depletion layer extending from the GaAs substrate surface, the resistance value is easily influenced by the surface state. The reproducibility and controllability of ρs deteriorate because the activation rate of implanted atoms is easily influenced by the amount of impurities in the semi-insulating substrate, such as the amount of carbon or oxygen in the substrate. Therefore, there is a limit to increase ρs, and therefore, the L / W ratio must be increased to realize high resistance. However, when the L / W ratio is increased, the length of the resistance is inevitably increased. For example, in order to obtain a resistance value of 100 KΩ, when ρs = 1000Ω and W = 10 μm, L = 1000 μm, which makes it difficult to miniaturize the MMIC chip. In recent years, low voltage operation and low current consumption of MMICs have been required, so that resistances of several hundreds KΩ or more are required in terms of circuit configuration. For example, the FET shown in the figure
In order to reduce the current consumption of the resistors R1 and R2 connected to the gate side in the gate bias circuit of
2 must be 100 KΩ to 1 MΩ, but the current n
Type semiconductor resistance is several tens of KΩ in terms of size, reproducibility and controllability.
Since it is difficult to form the resistance described above, there is a problem that the current consumption of the MMIC cannot be reduced.

[0007]

As described above, when the conventional n-type semiconductor is used to form the resistance for the bias circuit, the length of the resistance layer is required to obtain high resistance (several tens of KΩ or more). There is a problem that it becomes difficult to make the MMIC chip small in size because it becomes long, and if it is attempted to increase ρs, reproducibility of resistance value and controllability are deteriorated.

It is an object of the present invention to provide a miniaturized MMIC, which is excellent in reproducibility and controllability by miniaturizing the bias resistance in the MMIC.

[0009]

A monolithic microwave integrated circuit according to the present invention comprises a bias circuit including at least one field effect transistor and a resistor formed of a p-type semiconductor layer on a semi-insulating compound semiconductor substrate. According to the present invention, it is possible to provide an MMIC having a high semiconductor resistance layer of several tens of KΩ or more.

[0010]

According to the present invention, a bias resistor having a resistance value of several tens of KΩ or more is formed by selective ion implantation of p-type impurities. The p-type semiconductor layer has a mobility of several minutes as compared with the n-type semiconductor layer. Since it is as small as one to one tenth, as shown in the equation (1), ρs becomes several times to ten times even at the same carrier concentration.
Therefore, it is possible to easily form a resistor having a resistance value of several tens of KΩ or more, and it is possible to reduce the chip size, improve the reproducibility of the resistance value, and improve the controllability as compared with the MMIC configured using the n-type semiconductor layer.

[0011]

Embodiment 1 (Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are cross-sectional views showing the steps of manufacturing an MMIC having a GaAs FET and a resistor in the order of steps.

On the semi-insulating substrate 101, selective ion implantation (implantation condition Si ⁺ 2 is carried out) on the n ⁺ layer to be the FET source region 102 and drain region 103 by using the photoresist 100 as a mask.
50 KeV 4E13), respectively (FIG. 1 (a)). Next, the active layer 104 of the FET and the first resistor 105 are selectively ion-implanted (implantation conditions: Si ⁺ 70 Ke
V 4E12) respectively (Fig. 1
(B)). Next, as the resistance layer according to the present invention, the second resistor 106 made of a p-type layer is selectively ion-implanted (implantation condition Z
n ⁺ 70 Kev 4E12), the photoresist 100 is removed, and then capless annealing is performed at 850 ° C. for 15 minutes (FIG. 1C). Next, a source 107 and a drain 108 of the FET and an electrode (Pt / AuGe) 109 having an ohmic property with the first resistance are formed (FIG. 1D). Subsequently, an electrode (Pt / AuZn) 110 that makes ohmic contact with the second resistor is formed (FIG. 2A). Next, the gate electrode of the FET (Ti / A
l) After forming 111 by the lift-off method, a SiN film (thickness 2000A) 112 is formed as a surface protection film by the plasma CVD method (FIG. 2B). By removing a predetermined region of the SiN film 112 by etching, S
After forming the opening 113 in the iN film, the wiring electrode (Au / Pt / Ti) 114 is finally formed at a predetermined position by the lift-off method to connect the FET to the first and second resistors ( FIG. 2C).

In the MMIC shown in the above embodiment, since the second sheet resistance is ρs to 5000 Ω □, Si ⁺ ions of the conventional example are ion-implanted under the conditions of 70 KeV 4E12 cm ^-2 to form the resistance layer. 5 times ρs
Is obtained. Therefore, for example, in order to realize a bias resistance of 100 KΩ, when W = 10 μm, L = 200 μm, and it is possible to reduce the size to 1/5 of the conventional one.

Although the case where Zn is used as the ion species for ion implantation for forming the p-type layer has been illustrated in the above embodiment, the present invention is not limited to this.
An ionic species that forms a p-type layer such as g or Be may be used. Further, the conditions of ion implantation and the like are appropriately selected according to the required resistance value.

[0016]

As described above, according to the present invention, a resistance of several tens KΩ or more is formed by selective ion implantation of p-type impurities, so that the resistance can be made smaller than that of an n-type semiconductor resistance. Therefore, it becomes possible to form an MMIC having a bias resistance excellent in reproducibility and controllability.

[Brief description of drawings]

1A to 1D are MMs of an embodiment according to the present invention.
Sectional drawing which shows the manufacturing process of IC in order of process.

2A to 2C are cross-sectional views each showing the manufacturing process of the MMIC of one embodiment in the order of steps, continuing from FIG.

3A to 3C are cross-sectional views each showing a manufacturing process of a conventional MMIC using an n-type semiconductor layer as a resistor in the order of processes.

FIG. 4 is a gate bias circuit of an example FET.

[Explanation of symbols]

 100 photoresist 101 semiconductor substrate 102 source region 103 drain region 104 FET operating layer 105 n-type semiconductor layer 106 p-type semiconductor layer 109 Pt / AuGe electrode 110 Pt / AuZn electrode

Claims (1)

[Claims] 1. A monolithic microwave integrated circuit comprising at least one field effect transistor on a semi-insulating compound semiconductor substrate, and a bias circuit composed of a resistor formed of a P-type semiconductor layer.