JP3239967B2 - Image signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal generating circuit which uses an image memory to generate an image signal or the like as a pattern suitable for display on a display for adjusting the display.

[0002]

2. Description of the Related Art When adjusting convergence of a display device, it is necessary to display an image pattern such as a cross hatch pattern on a display (display tube). When all the image signal generating circuits for generating this image pattern are constituted by logic circuits, the circuit scale is increased in order to generate a complicated image pattern, and practicability is lacking. Therefore, a method of displaying a desired image pattern using an image memory capable of storing an image pattern for one screen is used. Hereinafter, description will be made with reference to the drawings.

FIG. 2 is a configuration diagram showing a configuration of a conventional image signal generation circuit using an image memory. In the figure,
It is assumed that an image pattern for one screen is stored in the image memory 22. First, the contents of the image memory 22 are read using an address generation circuit 21 that generates an address signal corresponding to screen scanning, and an image pattern is displayed on the display tube 9 via the video signal processing circuit 8.

The video signal processing circuit 8 is a circuit for converting a signal read from the image memory 22 into a waveform suitable for driving the display tube 9. In addition, a desired image pattern can be displayed by rewriting the content stored in the image memory 22 by operating the CPU (central processing unit) 6.

The operation will be described in more detail using a specific display example. FIG. 3 is an image pattern display diagram showing an example (lattice pattern) of the image pattern displayed on the display tube 9 of FIG. 4A is a data map showing storage data of the image memory 22 corresponding to a part (small area S surrounded by a dotted line) on the display screen of FIG.
(B) is an image pattern display diagram in which the image pattern display corresponding to (a) of FIG. 4 is displayed so as to be clear for each pixel.

When the conventional image signal generating circuit shown in FIG. 2 is used to display the image pattern shown in FIG. 3, it corresponds to a small area S surrounded by a dotted line in the image pattern shown in FIG. The contents stored in the image memory 22 are as shown in FIG. In FIG. 4A, the display tube 4 is turned on only at the portion where the data becomes 1, and the image pattern shown in FIG. 4B is displayed on the display tube 4 surface.

[0007]

When the image pattern shown in FIG. 4B is displayed on the display screen for the purpose of adjusting the display, the width L of the vertical line image is obtained.
When 1 is large, it is difficult to check the convergence state, for example, it is difficult to check the color shift. Therefore, the width L1 of the vertical line image needs to be sufficiently small.

However, in order to generate a vertical line image pattern signal having a narrow horizontal width using the conventional image signal generating circuit shown in FIG. 2, as shown in FIG. The resolution of the horizontal data density must be increased. Therefore, in order to obtain a practical image pattern (a vertical line image pattern with a narrow horizontal width), a large-capacity image memory must be used, resulting in a problem that the cost increases.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art, and to provide an image capable of generating a desired pattern signal such as a narrow vertical line image without using a large-capacity image memory. It is to provide a signal generation circuit.

[0010]

[0011]

[0012]

In order to achieve the above object, according to the present invention, in an image signal generating circuit, image information is stored in a circuit.
An image memory stored on a memory surface of the memory, and a binary pulse which is an image signal read from each address of the memory surface is converted into a second pulse different from the first pulse width by the pulse width conversion means. A first output unit that converts the data into a width and outputs it as a dot output; and a series of binary pulses that are image signals read from each address on the memory surface.
Pattern detection means for generating a discrimination output when a certain specific pattern is formed (for example, when the data string is 1 in the horizontal direction and 1 is continuous);

When a discriminant output is generated from the pattern detection means, the first output means bypasses the pulse width conversion means, thereby providing a binary signal which is an image signal read from each address on the memory surface. The pulse
A second output unit that outputs the first pulse width as a mark output as it is, and a dot output from the first output unit and a mark output from the second output unit are input and combined and output; Synthesizing means.

[0014]

[0015]

In most of the image patterns required for display adjustment (a cross hatch pattern is a typical example), the horizontal line image is continuous in the horizontal direction. Since the dots are discontinuous in the direction, a narrow dot output is used. Therefore, if the data string read from one memory surface is continuous in the horizontal direction (1 if logical 1), it is determined to be a horizontal line image, so that a mark is output. Since the judgment is made, a vertical line with a narrow width is displayed by using dot output. Thus, even when the capacity of the image memory is small and a sufficient image resolution in the horizontal direction cannot be obtained, a desired pattern signal (image signal) having a narrow width can be generated.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Before that, reference examples useful for understanding the present invention will be described.
deep. FIG. 1 is a configuration diagram showing a configuration of a reference example useful for understanding the present invention.

In FIG. 1, reference numeral 51 denotes an address generation circuit for generating an address signal corresponding to screen scanning, and 52, an image memory for dividing an image pattern for one screen into two memory surfaces and storing the same. 53 and dot output 5
4 outputs. That is, the image memory 52
An image pattern for one screen is decomposed into two patterns, stored in two respective memory surfaces, and a first memory surface of the two memory surfaces is formed. If the image signal read out from the memory is output as the mark output 53, the image signal read out from the second memory surface of the two memory surfaces is output as the dot output 54. .

4 is a pulse width control circuit for controlling the pulse width (a circuit for shortening the pulse width of an input pulse and outputting it as an output pulse), and 5 is an OR circuit for performing a logical sum operation.
Note that 6, 8, and 9 perform the same operations as those in FIG. 2, and thus description thereof will be omitted.

Hereinafter, the operation of the reference example shown in FIG. 1 will be described. First, an address signal corresponding to screen scanning is generated by the address generation circuit 51, and the contents of the image memory 52 are read. From the image memory 52, a wide mark output 53 is obtained by reading the first of the two memory surfaces constituting the memory, thereby obtaining the second of the two memory surfaces. By reading, a narrow dot output 54 is obtained.

The mark output 53 is directly input to the OR circuit 5. The dot output 54 is a pulse width control circuit 4
After that, the pulse is converted into a pulse having a small width, and then input to the OR circuit 5. The mark output and the dot output are combined by the OR circuit 5, and the display tube 9 is output via the video signal processing circuit 8.
To display the intended image pattern.

Here, a specific example of the configuration of the pulse width control circuit 4 in FIG. 1 will be described with reference to FIG. FIG. 5 is a configuration diagram showing a configuration of the pulse width control circuit 4 in FIG.
In FIG. 5, 61 is an input terminal, 62 is a capacitor, 6
3 is a variable resistor, 64 is a gate circuit (comparator) for converting an analog value to a digital value, and 65 is an output terminal.

In FIG. 5, the input of the input terminal 61 changes from 0 (Lo) to 1 (Hi) (due to the input of a pulse).
, The input voltage a of the gate circuit 64 sharply rises and then gradually decreases due to the capacitor 62 and the variable resistor 63. The output of the gate circuit 64 is 1 (Hi) during a period from the rise of the input voltage of the gate circuit 64 to the fall to a certain level (L level). Therefore, a narrow pulse is obtained from the output terminal 65.

FIG. 6 is an operation waveform diagram of the circuit shown in FIG. A pulse waveform (a wide rectangular wave) applied to the input terminal 61, a waveform of the input voltage a of the gate circuit 64, and an output waveform (a narrow rectangular wave) from the output terminal 65 are shown. . In FIG. 6, when the resistance value of the variable resistor 63 is changed, the width of the output pulse can be arbitrarily changed.

Hereinafter, a specific operation of the reference example shown in FIG. 1 will be described with reference to an example in which the image pattern shown in FIG. 4B is displayed. FIGS. 7B and 7D show respective patterns when the image pattern shown in FIG. 4B is decomposed into two. That is, since the image pattern in FIG. 4B is considered to be a collection of vertical line images and horizontal line images,
This is decomposed into a vertical line image and a horizontal line image, and FIG. 7B shows a horizontal line image, and FIG. 7D shows a vertical line image.

Here, FIG. 7A is a data map corresponding to the horizontal line image of FIG. 7B, and FIG.
Is a data map corresponding to the vertical line image in FIG. The image memory 52 shown in FIG. 1 corresponds to (a) and (c) in FIG.
The two memory surfaces shown in FIG. The mark output 53 of the image memory 52 corresponds to the read output of FIG. 7A, and the dot output 54 of the image memory 52 is
This corresponds to the read output of FIG.

Here, the data of the read output (mark output) in FIG.
(Hi). Therefore, when the mark output is displayed on the screen, the horizontal line image shown in FIG. 7B can be obtained. On the other hand, the data of the read output (dot output) in FIG.
(Hi).

If this dot output data is displayed as it is, it becomes a wide vertical line image as shown by LM in FIG. 7D. By shortening, FIG. 7D
A thin vertical line image having a width L2 shown in FIG. OR circuit 5
(B) and (d) of FIG.
Are obtained, and the display pattern shown in FIG. 7E is obtained.

Hereinafter, the memory capacity required for the image memory will be compared between the case of the prior art and the case of the reference example (FIG. 1). If the ratio between the memory capacity required to display the entire screen of FIG. 3 and the memory capacity required to display the portion of the small area S surrounded by the dotted line in FIG. In the case, the memory capacity of horizontal 12 × vertical 9 × n = 108 × n bits is obtained from FIG.
It is needed for the image memory 22.

On the other hand, in the case of the reference example , the horizontal 3 × vertical 9 × 2 systems × n = 5 from FIGS.
A similar display pattern can be displayed with a memory capacity of 4 × n bits = (１ ／) the memory capacity in the case of the related art.

As described above, according to the reference example ,
A desired display pattern with a small width can be generated without using a large-capacity image memory. Further, the horizontal width of the display pattern can be arbitrarily changed by adjusting the variable resistance of the pulse width control circuit.

In the reference example , the display is performed by using the pulse having the width of two systems. However, by using the pulse having the width of three or more systems (that is, one image is decomposed into three, and each image is divided into three). It is also possible to display more complex image patterns (by providing three memory planes for storing the decomposed images).

Next, the present invention in which the memory capacity is further reduced.
An embodiment will be described. FIG. 8 shows one embodiment of the present invention .
FIG. 3 is a configuration diagram showing an example configuration. 8, reference numeral 1 denotes an address generation circuit that generates an address signal corresponding to screen scanning, 2 denotes an image memory that stores an image pattern for one screen, 3 denotes a latch circuit that holds an output of the image memory, and 7 denotes a latch circuit. 3 is an AND circuit that performs a logical product operation of the input and the output of the third circuit. 4 to 6, 8, and 9 perform the same operations as those in FIG. 1, and therefore description thereof is omitted.

The operation of this embodiment will be described below. In FIG. 8, first, an address signal corresponding to screen scanning and a clock signal are generated by the address generation circuit 1. Each time the clock signal changes from logic 0 (Lo) to logic 1 (Hi), the address signal changes to the next address. Data is read from the image memory 2 using the address signal generated by the address generation circuit 1. The read data is held by the latch circuit 3 for only one clock.

When the output of the image memory 2 becomes logic 1 (Hi) continuously for two or more clocks, the input and output of the latch circuit simultaneously become logic 1 (Hi). Then, the output of the AND circuit 7 becomes 1 (Hi), and the output of the OR circuit 5 also becomes 1 (Hi).
i). On the other hand, the output of the image memory 2 becomes (2
When the logic 1 is attained for only one clock (without consecutive clocks), the input and output of the latch circuit 3 do not become logic 1 at the same time. Therefore, the output of the AND circuit 7 becomes 0
While keeping (Lo), the output of the latch circuit 3 becomes 1 (Hi).

Since the output of the latch circuit 3 is input to the pulse width control circuit 4, the dot output having a narrow pulse width output from the pulse width control circuit 4 is input to the OR circuit 5. At this time, since the output of the AND circuit 7 is 0, a dot pattern having a narrow width is displayed on the display tube 9.

Hereinafter, a specific operation of the present embodiment (FIG. 8) will be described with reference to an example in which the image pattern of FIG. 4B is displayed. Assuming that the image pattern shown in FIG. 9B, which is a pattern similar to the image pattern shown in FIG. 4B, is the image pattern displayed according to the present embodiment (FIG. 8), FIG. (a) is a data map corresponding to the image of FIG. 9 (b). That is, the image memory 2 in FIG. 8 is composed of the data map shown in FIG.

In the data map shown in FIG. 9A, where the data changes from 0 → 1 → 0 when viewed in the horizontal direction of the data, the input and output of the latch circuit 3 in FIG. Therefore, the output of the AND circuit 7 remains at 0 (Lo), and the output of the latch circuit 3 is output via the OR circuit 5 in a form in which the pulse width is reduced by the pulse width control circuit 4.

On the other hand, in the data map shown in FIG. 9A, 1 → 1 → 1 and 1
At locations where (Hi) is continuous (that is, at locations corresponding to horizontal line images), the input and output of the latch circuit 3 in FIG. 8 match. Therefore, the output of the AND circuit 7 is 1 (Hi),
A pulse (a pulse whose pulse width is not shortened) from the AND circuit 7 is output via the OR circuit 5. The OR circuit 5 also outputs a pulse whose pulse width is reduced by the pulse width control circuit 4 at the same time, but the pulse from the AND circuit 7 whose pulse width is not reduced is more effective.

As a result, in the data map shown in FIG. 9A, where the data changes from 0 → 1 → 0 when viewed in the horizontal direction of the data, as shown in FIG. Is displayed (a horizontal line image corresponding portion) where dots 1 → 1 → 1 and 1 (Hi) are continuous when viewed in the horizontal direction of the data (horizontal line image corresponding portion). The pattern is displayed. Since the logical sum of the dot pattern and the mark pattern is displayed on the display tube 9 of FIG. 8, (b) of FIG.
The same image pattern as that according to the prior art shown in FIG.

As in the case of the reference example of the present invention described above, when the required memory capacity of the image memory is calculated, FIG.
From (a), horizontal 3 × vertical 9 × n = 27 × n bits =
It can be seen that a display pattern similar to that of the prior art can be displayed by the image memory having a capacity of 1/4 that of the prior art. That is, according to the embodiment of the present invention, it is possible to generate a display pattern having a smaller horizontal width by using an image memory having a smaller capacity than in the reference example .

It is needless to say that the width of the vertical line image can be arbitrarily changed by adjusting the variable resistance of the pulse width control circuit as in the case of the reference example . In this embodiment (FIG. 8), the continuity (1 → 1 → 1) of the data string of the image memory is detected (by the latch circuit 3), and the pulse width of the display pulse is switched. Even when the width of the display pulse is switched when it is detected that the data sequence is a specific pattern (not just continuity), still another image pattern can be generated. Further, as in the case of the reference example , it is possible to display a more complicated image pattern by using pulses having a width of three or more systems.

[0042]

According to the present invention, it is possible to use a small-capacity image memory to generate an arbitrary narrow-width image signal for display display suitable for various adjustments of a display device. There is an advantage that an inexpensive image signal generating circuit suitable for use can be provided. Further, since the width of the display pattern can be freely adjusted without changing the storage contents of the image memory, a user-friendly image signal generating circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a reference example useful for understanding the present invention.

FIG. 2 is a configuration diagram showing a configuration of a conventional image signal generation circuit.

FIG. 3 is an explanatory diagram showing an example of an image pattern to be displayed.

FIG. 4 is an image memory data map and an image pattern display diagram in a conventional image signal generation circuit.

FIG. 5 is a circuit diagram showing a specific example of a pulse width control circuit in FIG. 1;

FIG. 6 is a waveform chart showing operation waveforms of respective parts of the circuit of FIG. 5;

FIG. 7 is an image memory data map and an image pattern display diagram in the reference example of FIG. 1;

FIG. 8 is a configuration diagram showing a configuration of an embodiment of the present invention.

9 is an image memory data map and an image pattern display diagram in the embodiment of FIG. 8;

[Explanation of symbols]

1,51 ... address generation circuit, 2,52 ... image memory,
3 ... Latch circuit, 4 ... Pulse width control circuit, 5 ... OR circuit, 6 ... CPU, 7 ... AND circuit, 8 ... Video signal processing circuit, 9 ... Display tube.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasushi Noguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Video Media Research Laboratories (72) Michitaka Osawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (56) References JP-A-63-231487 (JP, A) JP-A-5-76053 (JP, A) JP-A-63-211994 (JP, A) JP JP-A-5-134833 (JP, A) JP-A-4-1344981 (JP, A) JP-A-57-133481 (JP, A) JP-A-48-65850 (JP, A) JP-A-58-116580 (JP, A) A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 17/00-17/06 G09G 5/00-5/42

Claims (3)

(57) [Claims] 1. A circuit for generating an image signal to be displayed on a display device, wherein image information is stored on a single memory surface.
Image memory to be read from each address on the memory surface.
A binary pulse which is an output image signal is converted into pulse width conversion means.
The second pulse, which is different from the first pulse width
The first output which is converted to a pulse width and output as dot output
Means and an image read from each address of the memory surface
A sequence of binary pulses that are signals creates a certain pattern
When forming, a pattern detection method that generates the discrimination output
Stage and when a discrimination output is generated from the pattern detection means
Means for outputting said pulse width conversion means in said first output means.
By bypassing the stages, each address on the memory plane is
A binary pulse which is an image signal read from the
The second output that outputs as the mark output with the pulse width of 1
Force means, dot output from the first output means and the
The mark output from the second output means is input and synthesized.
Combining means for outputting to the display device,
An image signal generation circuit, comprising: 2. The image signal generating circuit according to claim 1,
Wherein the pulse width conversion means receives a binary pulse as input.
Charge / discharge time constant circuit, and the output level of the charge / discharge time constant circuit.
And the certain level, the former exceeds the latter
A comparator that generates an output only for a certain period
Image characterized in that it comprises a pulse width varying means.
Signal generation circuit. 3. The image signal generating circuit according to claim 1, wherein
A display device comprising: