JP3239023B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit. In recent years, in DRAMs and the like, the power supply voltage has been reduced from the conventional 5 V to 3.3 V in order to reduce power consumption and suppress the hot carrier effect. However, at present, since the transition period is from 5 V to 3.3 V, such low-voltage DRAMs and the like are
Based semiconductor integrated circuits (eg microcomputers)
Are connected to form one system. In this case, input / output circuits such as a low-voltage DRAM include:
An input voltage exceeding the allowable voltage will be applied. In the present invention, when connecting such semiconductor integrated circuits having different power supply voltages, the input / output circuit is devised so that a stable interface can be obtained.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional semiconductor integrated circuit. In the figure, 1 is an input circuit, 2 is an output circuit, and both are connected to an input / output terminal 3 in common. The input / output terminal 3 is connected to another integrated circuit 4. The input circuit 1
It comprises a clocked inverter 5 and a latch circuit 6 which receives an output of the clocked inverter 5 and temporarily holds input data. The clocked inverter 5 includes an input transistor 10 having an input voltage Vin applied to its gate,
And control transistors 12 and 13 controlled by an input control signal φ and its inverted signal * φ. The output circuit 2 includes output transistors 14 and 15
And a control circuit 16. The output control circuit 16 includes a NAND circuit 17 and an inverter 18,
One input terminal of the NAND circuit 17 has an output control signal * D
ES has been input. The power supply voltage Vcc2 of the above-mentioned semiconductor integrated circuit is, for example, 3.3V, and the power supply voltage Vcc1 of the other semiconductor integrated circuits 4 is, for example, 5V.

Next, the operation of the above circuit will be described with reference to FIG. First, in the input mode, the input control signal φ goes high, the clocked inverter 5 is activated, and the input voltage applied to the input / output terminal 3 is input to the internal circuit via the clocked inverter 5. You. At this time, the output control signal * DES is at the L level, the output of the output control circuit 16 is at the L level, and the output transistors 14 and 15 are both in the off state, that is, in the output prohibited state.

Next, in the output mode, the input control signal φ goes low, the clocked inverter 5 becomes inactive, and the input is inhibited. Data input before that is held by the latch circuit 6. , The output control signal * DES rises to the H level, and in response to this, the output inhibition state is released, and the output transistors 14 and 15
Outputs data to the input / output terminal 3.

[0005]

However, in the above input mode, the gates of the input transistors 10 and 11 constituting the clocked inverter 5 have a voltage of 5 V which is the power supply voltage Vcc1 of another semiconductor integrated circuit. Is applied, and the reliability of the gate oxide films of the input transistors 10 and 11 deteriorates. This is because a relatively thin gate oxide film is employed in a low-voltage semiconductor integrated circuit.

In addition, since a maximum voltage of 5 V is applied between the gate and the drain of each of the output transistors 14 and 15 in the output prohibited state, the reliability of the gate oxide film is similarly deteriorated. The present invention has been made in view of the above problems, and when connecting semiconductor integrated circuits having different power supply voltages, an input / output circuit is devised so that a highly reliable interface can be obtained. is there.

[0007]

The invention according to claim 1 is
An N-channel pass transistor 7 is provided between the input / output terminal 3 of the low-voltage semiconductor integrated circuit and the input / output circuits 1 and 2, and the power supply voltage Vc is connected to the gate of the pass transistor 7.
A voltage equal to c2 is supplied. The invention according to claim 2 is characterized in that N
A channel type pass transistor 7 is provided, and the gate of the pass transistor 7 is higher than the power supply voltage Vcc2,
Voltage V of power supply voltage Vcc1 or less of other semiconductor integrated circuit 4
p (Vcc2 <Vp ≦ Vcc1).

[0008]

According to the first aspect of the present invention, even when the voltage of Vcc1 (5 V) is applied to the input / output terminal 3, the maximum voltage applied to the input transistors 10, 11 and the like by the pass transistor 7 is Vcc2 ( 3.3V) -Vt, so that the problem of the reliability of the gate oxide film can be solved. Here, Vt is a threshold voltage of the pass transistor 7. For example, when Vt is 0.5V, the voltage becomes 2.8V.

According to a second aspect of the present invention, the impedance of the pass transistor 7 is reduced to speed up the input / output operation. That is, according to the present invention,
Since a voltage Vp (Vcc2 <Vp ≦ Vcc1) higher than the power supply voltage Vcc2 and lower than the power supply voltage Vcc1 of the other semiconductor integrated circuit 4 is supplied to the gate of the transistor 7, the maximum voltage applied to the input transistors 10, 11 and the like is , Vp-Vt. Therefore, the impedance of pass transistor 7 can be reduced within a range that does not affect the reliability of the gate oxide film. For example, Vp
Is set to 4V, the voltage becomes 3.5V.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit according to the present invention will be described below with reference to FIGS. (1) First Embodiment As shown in FIG. 1, an input / output terminal 3 of a semiconductor integrated circuit,
It is characterized in that an N-channel type pass transistor 7 is provided between the input / output circuits 1 and 2, and a gate voltage Vp of the pass transistor 7 is supplied with a voltage equal to the power supply voltage Vcc2. This pass transistor 7 operates in the same manner as a single-channel transmission gate that is always on. The other circuit configuration is the same as that of the conventional example, and the power supply voltage of the semiconductor integrated circuit is Vcc2 (3.3
V), the power supply voltage of the other semiconductor integrated circuit 4 connected thereto is Vcc1 (5 V).

According to this embodiment, in the input mode,
Vcc1 is applied to the input / output terminal 3 from another semiconductor integrated circuit 4.
(5V) is applied, the N-channel type
By providing the transistor 7, the maximum voltage applied to the input transistors 10, 11 and the like is Vcc2 (3.3
V) -Vt, the problem of the reliability of the gate oxide film can be solved. Here, Vt is the threshold voltage of pass transistor 7. Therefore, for example, when Vt is 0.5V, the voltage becomes 2.8V.

Further, in the output inhibited state (* DES = 0V), the maximum voltage applied between the gate and drain of the output transistors 14 and 15 also decreases, so that the problem of the reliability of the gate oxide film is similarly solved. You. On the other hand, in the output mode, the output data is
Is output to the input / output terminal 3 via the interface, the same voltage drop occurs as described above, but this can be dealt with by adjusting the threshold value of the input circuit of the other semiconductor integrated circuit 4.

(2) Second Embodiment In the first embodiment, since the pass transistor 7 is provided, the input / output impedance increases, and the data input / output speed decreases. Therefore, in the present embodiment, the gate voltage Vp of the pass transistor 7 is boosted from Vcc2 within an appropriate range to reduce the impedance. The gate voltage Vp is higher than the power supply voltage Vcc2, and is equal to or lower than the power supply voltage Vcc1 of another semiconductor integrated circuit 4 (V
cc2 <Vp ≦ Vcc1). According to such a setting, the maximum voltage applied to the input transistors 10, 11 and the like is Vp-Vt. Therefore, as long as the reliability of the gate oxide film is not affected, the pass transistor 7
Can be reduced. For example,
Assuming that Vt = 0.5V, when Vp is set to 4V, the voltage becomes 3.5V. Vp = Vcc1
If it is set to (5V), the voltage will be 4.5V. Considering the balance between the reliability of the gate oxide film and the reduction in impedance, it is most suitable to set Vp to about 4V.

As a method for generating Vp, the voltage can be generated inside the semiconductor integrated circuit without using an external voltage by using a booster circuit. An example circuit is shown in FIG. This circuit, upon receiving the rising of the boost signal φp, changes the power supply voltage Vcc2 to (1 + α) Vcc2-V
a booster circuit 20 for boosting the voltage to a voltage of t;
And a ring oscillator 22 for supplying an operation clock to the pump circuit 21 to maintain the boosted voltage within a certain range. Here, Vt is the threshold value of the N-channel MOS transistor 23. 23, 25, 26, 28, 2
Numerals 9 and 30 are N-channel MOS transistors, 24 is a P-channel MOS transistor, 2
7, 31 are coupling capacitors. Also, α
Is a value determined by the division ratio between the coupling capacitance C1 and the parasitic capacitance C2 of the node B (0 <α <1).

FIG. 3 is a timing chart showing the operation of this circuit. When the boost signal φp rises to Vcc2, the node B is connected to Vcc via the coupling capacitor 27.
From 2-Vt, it changes to (1 + α) Vcc2-Vt.
Since the transistor 24 is on, Vp is:
(1 + α) Vcc2-Vt is output. When Vp decreases due to a leak current or the like, the pump circuit 21
Works, and Vp is maintained at a voltage of (1 + β) Vcc2-2Vt. Here, β is a value determined by the division ratio between the coupling capacitance C3 and the parasitic capacitance C4 (0 <β <1).
In this way, Vp is kept within a predetermined voltage range.

[0016]

As described above, according to the semiconductor integrated circuit of the present invention, by providing the pass transistor 7 and applying the power supply voltage Vcc2 to the gate thereof, the input / output terminal 3 is connected to the Vcc1 (5V). Even if voltage is applied,
The maximum voltage applied to the input transistors 10, 11 and the like by the transistor 7 is reduced to Vcc2 (3.3V) -Vt, so that the problem of the reliability of the gate oxide film can be solved. This makes it possible to ensure the reliability of the low-voltage semiconductor integrated circuit when interfacing the low-voltage semiconductor integrated circuit with the normal-voltage semiconductor integrated circuit.

A voltage Vp (Vcc2 <Vp ≦ Vc) that is higher than the power supply voltage Vcc2 and lower than the power supply voltage Vcc1 of another semiconductor integrated circuit 4 is applied to the gate of the pass transistor 7.
c1), the input transistors 10,
The maximum voltage applied to 11 and the like is Vp-Vt. Therefore, the impedance of the pass transistor 7 can be reduced within a range that does not affect the reliability of the gate oxide film, and a decrease in the data input / output speed can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit for generating a gate voltage Vp of a pass transistor.

FIG. 3 is an operation timing chart of the circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a conventional semiconductor integrated circuit.

FIG. 5 is an operation timing chart of the circuit shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input circuit 2 Output circuit 3 I / O terminal 4 Other semiconductor integrated circuits 5 Clocked inverter 6 Latch circuit 7 Pass transistor 10, 11 Input transistor 14, 15 Output transistor 20 Boost circuit 21 Pump circuit 22 Ring oscillator

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-243321 (JP, A) JP-A-7-99437 (JP, A) JP-A-8-97703 (JP, A) JP-A-8-97 65135 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17/70 H03K 19/00-19/007

Claims (1)

(57) [Claims] 1. An input voltage V supplied from another semiconductor integrated circuit (power supply voltage: Vcc1) having a relatively high power supply voltage.
an input circuit for receiving the input voltage, an input transistor forming a part of the input circuit, the input voltage Vin being applied to a gate, an output circuit commonly connected to the input circuit and an input / output terminal, and the output circuit A power supply voltage: Vcc2, comprising an output transistor which forms a part of the circuit and outputs the input voltage between the gate and the drain when the output circuit is in the output inhibited state. Installed between input and output circuits
N-channel type pass transistor and power supply
And a booster circuit for boosting the voltage Vcc2.
Pump circuit to keep the applied voltage within a certain range
And the output of the booster circuit and the pump circuit is
Commonly connected to the gate of N-channel type pass transistor
The gate of the pass transistor.
Greater than source voltage Vcc2 and less than or equal to power supply voltage Vcc1
Voltage Vp (Vcc2 <Vp ≦ Vcc1)
A semiconductor integrated circuit characterized by the above.