JPH0897703A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To secure high reliability by providing an N-channel path transistor(TR) between an input terminal and an input circuit and applying a voltage equal to a power supply voltage to a gate of the path TR so as to prevent application of a voltage exceeding a permissible range to the integrated circuit designed to be operated at a low voltage. CONSTITUTION: An N-channel path TR 7 is provided between an input terminal 3 of a low voltage semiconductor integrated circuit and an input circuit 1 and a voltage equal to a power supply voltage Vcc2 is fed to a gate of the path TR 7. Through the constitution above, even when a voltage of Vcc1 (5V) is applied to an input output terminal 3 from other semiconductor integrated circuit 4, since a maximum voltage applied to input TRs 10, 11 is as low as Vcc2(3.3V)-Vt through the provision of the N-channel path TR 7, a problem of the reliability of a gate oxide film is solved, where Vt is a threshold voltage of the path TR 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit. In recent years, in DRAMs and the like, the power supply voltage is being reduced from the conventional 5V to 3.3V in order to reduce the power consumption and suppress the hot carrier effect. However, at the present time, it is in the transitional period from 5V to 3.3V, so such low voltage DRAM etc.
System semiconductor integrated circuit (for example, microcomputer)
It is performed by connecting and to configure one system. In this case, an input voltage exceeding the allowable voltage is applied to the input circuit such as the low voltage DRAM. The present invention provides a stable interface by devising the input circuit portion when connecting such semiconductor integrated circuits having different power supply voltages.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit is shown in FIG. In the figure, 1 is an input circuit, which is connected to an input terminal 3. The input terminal 3 is connected to another integrated circuit 4. The input circuit 1 includes a clocked inverter 5 and a latch circuit 6 that receives the output of the clocked inverter 5 and temporarily holds the input data. The clocked inverter 5 includes input transistors 10 and 11 to which an input voltage Vin is applied to their gates, and control transistors 12 and 1 controlled by an input control signal φ and its inverted signal * φ.
3 and 3.

Power supply voltage Vcc2 of the above semiconductor integrated circuit
Is 3.3V, for example, and the power supply voltage Vcc1 of the other semiconductor integrated circuit 4 is 5V, for example. Next, the operation of the above circuit will be described. First, in the input mode, the input control signal φ becomes H level, the clocked inverter 5 is activated, and the input voltage applied to the input terminal 3 is input to the internal circuit via the clocked inverter.

Next, the input control signal φ becomes L level,
The clocked inverter 5 becomes inactive and enters an input prohibited state. The data input before that is held by the latch circuit 6.

[0005]

However, the input transistor 1 forming the clocked inverter 5 is
A voltage of 5 V, which is the power supply voltage Vcc1 of another semiconductor integrated circuit, is directly applied to the gates of 0 and 11.
There is a problem that the reliability of the gate oxide film of the input transistors 10 and 11 deteriorates. This is because a low voltage semiconductor integrated circuit uses a relatively thin gate oxide film.

The present invention has been made in view of the above problems. When connecting semiconductor integrated circuits having different power supply voltages, the input circuit is devised so that a highly reliable interface can be obtained. It is a thing.

[0007]

The invention according to claim 1 is
An N-channel type pass transistor 7 is provided between the input terminal 3 of the low voltage semiconductor integrated circuit and the input circuit 1, and a voltage equal to the power supply voltage Vcc2 is supplied to the gate of the pass transistor 7. . In the invention according to claim 2, an N-channel type pass transistor 7 is provided between the input terminal 3 and the input circuit 1, the gate of the pass transistor 7 is higher than the power supply voltage Vcc2, and the other semiconductor integrated circuit is provided. Voltage Vp (Vcc less than power supply voltage Vcc1 of circuit 4)
2 <Vp ≦ Vcc1) is supplied.

[0008]

According to the invention of claim 1, V is applied to the input terminal 3.
Even if a voltage of cc1 (5V) is applied, the maximum voltage applied to the input transistors 10 and 11 by the pass transistor 7 is as low as Vcc2 (3.3V) -Vt, which causes a problem of reliability of the gate oxide film. Can be resolved. Here, Vt is a threshold voltage of the pass transistor 7, and for example, when Vt is 0.5V, the voltage is 2.8V.

According to the second aspect of the invention, the impedance of the pass transistor 7 is lowered to speed up the data input operation. That is, according to the present invention, the gate of the pass transistor 7 is supplied with the voltage Vp (Vcc2 <Vp ≦ Vcc1) higher than the power supply voltage Vcc2 and lower than the power supply voltage Vcc1 of the other semiconductor integrated circuit 4. The maximum voltage applied to the transistors 10 and 11 is Vp-Vt. Therefore, the impedance of the pass transistor 7 can be lowered within a range that does not affect the reliability of the gate oxide film. For example, Vp
Is set to 4V, the voltage becomes 3.5V.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a semiconductor integrated circuit of the present invention will be described below with reference to FIGS. (1) First Embodiment As shown in FIG. 1, an N-channel type pass transistor 7 is provided between an input terminal 3 of a semiconductor integrated circuit and the input circuit 1.
Is provided and a voltage equal to the power supply voltage Vcc2 is supplied to the gate voltage Vp of the pass transistor 7. This pass transistor 7 operates in the same manner as a single-channel transmission gate that is always on. The other circuit configuration is the same as that of the conventional example, the power supply voltage of the semiconductor integrated circuit is Vcc2 (3.3 V), and the power supply voltage of the other semiconductor integrated circuit 4 connected thereto is Vcc1.
(5V).

According to this embodiment, another semiconductor integrated circuit 4
Therefore, even if a voltage of Vcc1 (5V) is applied to the input / output terminal 3, the maximum voltage applied to the input transistors 10 and 11 is Vcc2 (3.3V) by providing the N-channel type pass transistor 7. Since it will be as low as −Vt,
It is possible to solve the problem of reliability of the gate oxide film.
Where Vt is the threshold voltage of pass transistor 7. Therefore, for example, when Vt is 0.5 V,
The voltage is 2.8V.

(2) Second Embodiment In the first embodiment, since the pass transistor 7 is provided, the input / output impedance increases and the data input speed becomes slow. Therefore, in this embodiment, the gate voltage Vp of the pass transistor 7 is set to V within an appropriate range.
The impedance was lowered by boosting the voltage from cc2. The gate voltage Vp is higher than the power supply voltage Vcc2 and is equal to or lower than the power supply voltage Vcc1 of another semiconductor integrated circuit 4 (Vc).
c2 <Vp ≦ Vcc1). With this setting, the maximum voltage applied to the input transistors 10 and 11 is Vp-Vt. Therefore, the impedance of the pass transistor 7 can be lowered within a range that does not affect the reliability of the gate oxide film. For example, Vt
= 0.5V, when Vp is set to 4V,
The voltage is 3.5V. Also, Vp = Vcc1 (5
When it is set to V), the voltage becomes 4.5V. Considering the balance between the reliability of the gate oxide film and the low impedance, it is most suitable to set Vp to about 4V.

A booster circuit can be used as a method of generating Vp. An example of the circuit is shown in FIG. This circuit receives the rising edge of the boosting signal φp and receives the power supply voltage Vc.
A booster circuit 20 that boosts c2 to a voltage of (1 + α) Vcc2-Vt, and a pump circuit 2 that is connected to the output Vp of the booster circuit 20 and holds the boosted voltage.
1 and a ring oscillator 22 that supplies a clock to the pump circuit 21. Here, Vt is the threshold value of the N-channel MOS transistor 23. 23, 2
5, 26, 28, 29 and 30 are all N channel type MOS transistors, and 24 is a P channel type MOS transistor.
Transistors 27 and 31 are coupling capacitors. Further, α is a value determined by the division ratio of the coupling capacitance C1 and the parasitic capacitance C2 at the node B (1 <
α <1).

FIG. 3 is a timing chart showing the operation of this circuit. When the boosted signal φp rises to Vcc2, the node B becomes Vcc through the coupling capacitor 27.
It changes from 2-Vt to (1 + α) Vcc2-Vt.
Since the transistor 24 is in the ON state, Vp is
(1 + α) Vcc2-Vt is output. Further, when Vp decreases due to a leak current or the like, the pump circuit 21
And Vp is held at a voltage of (1 + β) Vcc2-2Vt. Note that β is a value determined by the division ratio of the coupling capacitance C3 and the parasitic capacitance C4 (1 <β <1).
In this way, Vp is maintained in the predetermined voltage range.

[0015]

As described above, according to the semiconductor integrated circuit of the present invention, since the pass transistor 7 is provided and the power supply voltage Vcc2 is applied to its gate, the voltage of Vcc1 (5V) is applied to the input terminal 3. Is applied, the maximum voltage applied to the input transistors 10 and 11 by the pass transistor 7 is as low as Vcc2 (3.3V) -Vt, so that the problem of reliability of the gate oxide film can be solved. . This makes it possible to ensure the reliability of the low-voltage semiconductor integrated circuit when interfacing the low-voltage semiconductor integrated circuit with the normal-voltage semiconductor integrated circuit.

A voltage Vp (Vcc2 <Vp≤Vc) which is higher than the power supply voltage Vcc2 at the gate of the pass transistor 7 and is equal to or lower than the power supply voltage Vcc1 of the other semiconductor integrated circuit 4.
By supplying c1), the input transistor 10,
The maximum voltage applied to 11 is Vp-Vt. Therefore, the impedance of the pass transistor 7 can be lowered and the reduction of the data input speed can be suppressed as much as possible within the range that does not affect the reliability of the gate oxide film.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit for generating a gate voltage Vp of a pass transistor.

FIG. 3 is an operation timing chart of the circuit shown in FIG.

FIG. 4 is a circuit diagram showing a semiconductor integrated circuit of a conventional example.

[Explanation of symbols]

 1 Input Circuit 3 Input Terminal 4 Other Semiconductor Integrated Circuit 5 Clocked Inverter 6 Latch Circuit 7 Pass Transistor 10,11 Input Transistor 14,15 Output Transistor 20 Booster Circuit 21 Pump Circuit 22 Ring Oscillator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/003 E

Claims (3)

[Claims] 1. An input voltage V supplied from another semiconductor integrated circuit (power supply voltage: Vcc1) having a relatively high power supply voltage.
A semiconductor integrated circuit (power supply) having an input terminal to which in is applied, an input circuit connected to the input terminal, and an input transistor that forms a part of the input circuit and has the gate to which the input voltage Vin is applied. Voltage: Vcc2),
An N-channel type pass transistor is provided between the input terminal and the input circuit, and a voltage equal to the power supply voltage Vcc2 is supplied to the gate of the pass transistor. 2. An input voltage V supplied from another semiconductor integrated circuit (power supply voltage: Vcc1) having a relatively high power supply voltage.
A semiconductor integrated circuit (power supply) having an input terminal to which in is applied, an input circuit connected to the input terminal, and an input transistor that forms a part of the input circuit and has the gate to which the input voltage Vin is applied. Voltage: Vcc2),
An N-channel type pass transistor is provided between the input terminal and the input circuit, and the gate of the pass transistor has a voltage Vp (Vcc2 higher than the power supply voltage Vcc2 and lower than the power supply voltage Vcc1 of the other semiconductor integrated circuit). <V
A semiconductor integrated circuit characterized by supplying p ≦ Vcc1). 3. A booster circuit for boosting a voltage Vp supplied to the gate of a pass transistor to a power supply voltage Vcc2,
A pump circuit connected to the output of the booster circuit for holding the boosted voltage in a constant range, and a ring oscillator for supplying an operating clock to the pump circuit, are generated by a circuit. Item 2. The semiconductor integrated circuit according to item 2.