JP3238035B2 - Drive circuit for capacitive load - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-voltage capacitive load used for driving a flat display panel such as a gas discharge display panel (plasma display panel) or an electroluminescent display panel (EL display panel). It relates to a drive circuit.

[0002]

2. Description of the Related Art Conventionally, a driving circuit as disclosed in JP-A-59-15327 has been used for displaying a flat display panel as described above. In this circuit, a load current flows when the lower bipolar transistor is turned on, and a current flows through a diode disposed in a forward direction between the base terminal of the bipolar transistor disposed on the upper side and the emitter terminal of the bipolar transistor. Since a reverse bias is applied between the base and the emitter of the transistor, the upper bipolar transistor is turned off. On the other hand, when the lower bipolar transistor is off, the base terminal of the upper bipolar transistor
Since the power supply is connected via the resistor, the upper bipolar transistor is turned on. This circuit enables display driving of a panel with a simple circuit configuration.

On the other hand, the above publication or Japanese Patent Application Laid-Open No. 59-1532
The drive circuit described in Japanese Patent Application Laid-Open No. 8-108 aims to improve the rounding of the output waveform and reduce the power consumption. However, the circuit configuration has a large number of elements used.

[0004]

According to the above prior art, firstly, the output waveform is rounded, and secondly, the base driving resistance of the upper bipolar transistor which is generated when the lower bipolar transistor is turned on. There is a problem in that the consumed power is large.

On the other hand, the prior art has a circuit configuration using many elements. This requires about 480 channels as a driving circuit for a flat panel display, which may lead to an increase in chip area in order to integrate the driving circuit.

In view of the above, in order to obtain a sharp output waveform with a simple circuit configuration, a circuit configuration using a controlled gate bipolar transistor (hereinafter referred to as IGBT) capable of high-speed operation as a switching element is considered. However, there is still a problem that the waveform is rounded. This will be described with reference to FIGS.

FIG. 1 shows a circuit configuration for driving a plasma display panel (hereinafter referred to as a PDP). P
The DP, that is, the load 1, is a gas discharge tube, and can be regarded as a capacitive Zener diode equivalently. Therefore, during the period t1 when the lower IGBT 2 is turned on, the current (io) flowing there is represented by the sum of the capacitance component and the DC current component. FIG. 2 shows the waveform at this time. Next, the lower IG
When the BT2 is turned off, in the period t2, before the upper IGBT3 is turned on, the output voltage rises due to the load characteristics and the tail characteristics of the IGBT2. In the period t3, the upper IGBT 3 is not turned on as before, and the zener voltage of the load can be seen. This indicates the reverse recovery characteristic of the diode 4. When the reverse recovery is completed, the gate voltage of the upper IGBT 3 is supplied via the resistor 5 and the upper IGBT 3 is turned on. This is the period t4.

As the above phenomenon indicates, the larger the dc current component of io, the longer the diode reverse recovery time, so that the rise of the voltage waveform is delayed and a sharp output waveform cannot be obtained.

An object of the present invention is to provide a driving circuit for a capacitive load capable of obtaining a sharp output waveform with a simple circuit configuration in view of the above problems.

[0010]

Means for solving the problem will be described with reference to FIG.

In FIG. 1, which is a conventional circuit configuration, another IGBT 9 having the same gate and emitter terminal as the lower IGBT 2 is provided, and the collector terminal of the IGBT 9 is connected to the emitter terminal of the upper IGBT 3. As a result, a part of the load current io is shared by the IGBT 9, and thus has the function of reducing the current flowing through the diode 4. Therefore, there is an effect of reducing the influence of the reverse recovery characteristic of the diode.

[0012]

According to the above-mentioned means, since there is an effect of minimizing a delay at the time of reverse recovery in the diode 4 when the lower IGBT 2 shifts from on to off, a sharp output waveform having a fast rise is obtained. There is an effect that can be obtained.

[0013]

FIG. 3 is a circuit diagram showing the configuration of a circuit according to an embodiment of the present invention.

When the output of the pulse power supply 8 is "L", the lower IGBTs 2 and 9 are off. At this time, the upper IGBT
The gate terminal 3 has a floating power supply 7 via a resistor 5.
, The terminal is constantly on, and both terminals of the load 1 are at the same potential.

Next, when the pulse power supply output goes "H", the lower IGBTs 2 and 9 are turned on. At this time, the charging current flows instantaneously due to the capacity of the load 1 via the diode 4 by the IGBT 2. With this, IGBT3
Are reverse biased by a forward voltage drop by the diode 4, and the IGBT 3 is turned off. Also, IGB
T9 is turned on at the same time as the IGBT2, but the load 1 is larger than the stray capacitance Cge on the collector side of the IGBT2 and the stray capacitance (capacitance component of the load 1) on the collector side of the IGBT9. The transition is (IGB
Collector potential of T2) <(collector potential of IGBT9)
IGBT3 operates so that the gate voltage does not exceed threshold value Vth. Therefore, no penetration occurs when the IGBT 3 and the IGBT 9 are simultaneously turned on.

In the steady state where the pulse power supply output is "H", the load 1 has a Zener characteristic.
This is a state in which a current is flowing through the GBT 9.

Next, the pulse power supply output changes from "H" to "L".
The operation when the state changes to will be described. First I
The current flows through the GBT 2 and the IGBT 9 as described above, and the current naturally flows through the diode 4. However, the IGBT 2 and the IGBT 9 share current depending on their size ratio. When the lower IGBT 2 is turned off, the current is cut off instantaneously.
Due to the tail current characteristic of the BT, the current is not completely cut off and remains to some extent. Due to this current, a forward voltage drop remains in the diode 4, and the IGBT 3 cannot be turned on. Further, since the diode cannot instantly cut off the reverse voltage due to the reverse recovery characteristic, the IGBT 3 remains off because the gate voltage of the IGBT 3 cannot increase during the reverse recovery. Therefore, IGB
T3 starts to be turned on immediately after the reverse recovery of the diode 4 is completed and immediately after the voltage of the floating power supply 7 is applied to the gate via the resistor 5.

The points for sharpening the output waveform in the above operation are: 1) To suppress the tail current of the IGBT 2.

2) To speed up the reverse recovery characteristic of the diode.

3) A resistor 5 which is a gate resistance of the IGBT 3
To be smaller.

[0021] However, the above 3) cannot be extremely reduced because the resistor 5 becomes a load when the IGBT 2 is turned on and leads to an increase in power consumption. Therefore, it is necessary to improve the effect by devising 1) and 2).

In the embodiment of FIG. 1, the bias current of the diode 4 is reduced to reduce the reverse recovery time.
Further, by selecting the size ratio of the IGBT 9 and the IGBT 2 to be equal to the ratio between the capacitance component of the load 1 and the gate-emitter capacitance of the IGBT 3, that is, by setting the area of the active region of the IGBT 9 to be larger than that of the IGBT 2, Without causing IGBT 9 penetration
The current of the diode 4 can be minimized.

It is to be noted that the use of a diode having a high-speed reverse recovery characteristic by irradiation with a Schottky barrier diode, an electron beam or the like is more effective. Furthermore,
A Zener diode may be used for the purpose of protecting the gate of the upper IGBT 3.

Next, the lower IGBTs 2 and 9 in FIG. 3 will be described with reference to FIG. 4 which shows a cross-sectional structure of a horizontal IGBT. In the figure, the structure of the horizontal IGBT is an N-MOS
It has a composite structure of a transistor and a PNP bipolar transistor. A P-type layer 23 serving as a substrate and a channel layer constituting an N-MOS transistor is formed on the surface of an N-type substrate 21, and an N + serving as a source is formed in the P-type layer 23.
The layer 24 is formed. The N + layer 24 corresponds to the N emitter of the IGBT. The P layer 23 and the N + layer 24 are short-circuited by the electrode 27. The electrode 27 corresponds to an emitter electrode of the IGBT. The gate electrode 25 is made of P serving as a channel layer.
It is arranged on the layer 23 and forms the gate of the N-MOS transistor. On the other hand, in the PNP bipolar transistor, a P + layer 22 is formed on the surface of an N-type substrate 21 separately from the P-layer 23, so that the P + layer 22 is a P-emitter, the N-type substrate 21 is an N-base, The layer 23 is configured as a collector. The P + layer 22 corresponds to the collector of the IGBT.

In the lateral IGBT having such a structure, the ON operation is performed by applying a positive voltage to the gate of the N-MOS transistor to make the channel conductive, whereby the emitter electrode 27, the N + layer 24, and the P layer 23 are turned on. An electron current flows through the surface channel inversion layer, the N-type substrate 21 and the P + layer 22. This electron current becomes a base current of the PNP bipolar transistor, a hole is injected from the P + layer 22 into the N-type substrate 21, and flows through the P layer 23 to the emitter electrode 27 as a hole current. In the OFF operation, 0 V is applied to the gate to cut off the electron current. Electrons that remain transiently after applying 0 V to the gate are extracted via the P + layer 22. On the other hand, holes continue to be injected from the P + layer 22 until electron current stops flowing, and become holes. The holes are drawn out to the emitter electrode 27 through the P layer 23. Generally, the mobility of holes is 1/3 of that of electrons, so that the switching speed in the off state depends on the disappearance of the hole current. This phenomenon is the above-mentioned tail current of the IGBT.

In order to reduce the tail current, the N-type substrate 21
FIG. 5 shows another embodiment in which an N @ + layer 26 is provided thereon, an N substrate terminal 30 is taken out, and the N substrate terminal 30 is connected to the anode side of the diode 4. FIG. Thereby, IG
A reverse bias is applied between the collector (P + layer 22a) of the BT2 and the N-type substrate 21 by a potential difference corresponding to a forward voltage drop of the diode 4, thereby suppressing injection of holes from the collector, thereby reducing the tail current at the time of off. It is intended. In FIG. 4, the P + layer 22a and the N + layer 26 need not be in contact with each other.

In the circuit shown in FIG. 5, even if the lower IGBT 9 is not provided, there is an effect of sharpening the output waveform by reducing the tail current of the lower IGBT 2.

In order to reduce the number of components in the circuit configuration, FIG.
It is also possible to eliminate the diode 4 in. In this case, by connecting the N-substrate terminal 30 to the gate of the upper IGBT 3, the two collectors (2
A diode is formed between 2a and 22b), and the same effect as diode 4 can be expected.

If the following conditions are satisfied, the diode 4 can be omitted without connecting the N-substrate terminal. In FIG. 3, first, the capacitance component of the load 1 is larger than the gate-emitter capacitance of the IGBT 3. This is the same as the operation when the diode 4 is present because the gate voltage of the upper IGBT 3 always rises earlier than the voltage on the emitter side during a transition. Second, when the lower IGBT 2 is on, the lower IGBT 9 is lower than the collector voltage of the lower IGBT 9.
2 so that the collector voltage is always low.
This is to prevent the gate voltage of the upper IGBT 3 from becoming positive. According to the above circuit configuration, it is not necessary to consider the delay due to the reverse recovery operation in the diode 4, so that a sharper output voltage can be obtained. Furthermore, connecting the N-substrate terminal 30 to the emitter of the upper IGBT 3 has the effect of reducing the tail current of the lower IGBT.

FIG. 6 shows an example of a pattern layout of an IC in which the circuit of FIG. 3 is made monolithic with multiple channels. Since the symbols in this figure correspond to those in FIG. 3, the description of the symbols is omitted. Each element is separated from the substrate, but the two lower I
GBTs 2 and 9 are formed without being separated as shown in FIG. Therefore, the number of constituent elements is small, and it is not necessary to separate the substrates of the two lower IGBTs, so that the chip size can be reduced.

In the above embodiment, the semiconductor switching element used is an IGBT, but the present invention is not limited to this.
Other semiconductor switching elements such as SFETs and bipolar transistors may be used.

[0032]

According to the present invention, the reverse recovery current of the diode can be minimized, and the tail current of the lower IGBT can be reduced, so that the output waveform is sharpened.

[Brief description of the drawings]

FIG. 1 is a drive circuit according to the prior art.

FIG. 2 is a diagram showing operation waveforms of the circuit shown in FIG.

FIG. 3 is a circuit showing an embodiment according to the present invention.

FIG. 4 is a circuit diagram of the lower IGBT in the circuit of FIG.
It is the figure represented by the cross-section of BT.

FIG. 5 is a circuit showing another embodiment of the present invention.

6 is an example of a pattern layout of an IC in which the circuit of FIG. 3 is made monolithic with multiple channels.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Load (gas discharge tube etc.), 2 ... Lower IGBT, 3 ... Upper IGBT, 4 ... Diode 4, 5 ... Resistance, 6 ... High voltage power supply, 7 ... Floating power supply, 8 ... Pulse power supply, 9 ... Another Lower IGBT, 20 insulating film, 21 N-type substrate, 22a P emitter layer (corresponding to collector of lower IGBT 2), 22b P emitter layer (corresponding to collector of lower IGBT 9), 23 P layer, 24 ... N + layer, 25a ...
Electrode (corresponding to the gate of the lower IGBT2), 25b ...
Electrode (corresponding to the gate of lower IGBT 9), 26 ... N + layer for taking out N-type substrate, 27 ... emitter electrode, 30
... N substrate terminal, 31 ... emitter terminal, 32 ... gate terminal.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shoichi Ozeki 3-10-2 Bentencho, Hitachi City, Ibaraki Prefecture Inside Tachihara-cho Electronic Industry Co., Ltd. (56) References JP-A-59-15327 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 17/56 H03K 17/06

Claims (6)

(57) [Claims] 1. A first and second semiconductor element having one main terminal, the other main terminal, and a control terminal; one main terminal of the first semiconductor switching element and the other of the second semiconductor switching element. And a diode connected between the other main terminal of the second semiconductor switching element and the control terminal, and a diode connected between the other main terminal of the first semiconductor switching element and the second main terminal of the first semiconductor switching element. A power supply is connected between one main terminal of the second semiconductor switching element and a capacitive load is connected between one main terminal and the other main terminal of the second semiconductor switching element. A third semiconductor switching element connected to the other main terminal of the second semiconductor switching element and the other main terminal connected to the other main terminal of the first semiconductor switching element. Drive circuit for the load. 2. A driving circuit for a capacitive load according to claim 1, wherein the first and third semiconductor switching elements are formed on the same semiconductor substrate. 3. The semiconductor switching element according to claim 1, wherein the first semiconductor switching element is an insulated gate bipolar transistor, and a substrate terminal of the insulated gate bipolar transistor is connected to the other main terminal of the second semiconductor switching element. A driving circuit for a capacitive load. 4. The driving circuit for a capacitive load according to claim 1, wherein an active area of the third semiconductor switching element is larger than an active area of the first semiconductor switching element. 5. A semiconductor device comprising first and second semiconductor elements having one main terminal, the other main terminal, and a control terminal, wherein one main terminal of the first semiconductor switching element and the second semiconductor switching element. Is connected to the other main terminal of the first semiconductor switching element, and a power supply is connected between the other main terminal of the first semiconductor switching element and one main terminal of the second semiconductor element. A capacitive load is connected between the main terminal and the other main terminal, one main terminal is connected to the other main terminal of the second semiconductor switching element, and the other main terminal is connected to the first semiconductor switching element. An insulated gate bipolar transistor connected to the other main terminal, wherein the first semiconductor switching element and the insulated gate bipolar transistor are formed on the same semiconductor substrate; Ring elements or insulated gate bipolar substrate terminal of the transistor is the capacitive load driving circuit that can, wherein connected to the control terminal of the second semiconductor switching element. 6. An insulated gate bipolar transistor and a semiconductor switching element having one main terminal, the other main terminal, and a control terminal; one main terminal of the insulated gate bipolar transistor and the other main terminal of the semiconductor switching element. And a diode connected between the other main terminal of the semiconductor switching element and the control terminal, and the other main terminal of the insulated gate bipolar transistor and one main terminal of the semiconductor switching element. A power supply is connected between the semiconductor switching element and a capacitive load is connected between one main terminal and the other main terminal of the semiconductor switching element, and the substrate terminal of the insulated gate bipolar transistor is connected to the other main terminal of the semiconductor switching element. driving circuits for capacitive load, characterized in that it is connected.