JP3235612B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display driver IC such as an LCD driver, a multi-bit drive IC such as a printer driver IC, a multi-input / output IC such as a sensor interface IC, a gate array, and the like. More specifically, the present invention relates to a semiconductor device having an array structure in which a plurality of circuit cells having the same circuit configuration and their input or output electrodes are arranged in pairs and a data input / output device using the same.

[0002]

2. Description of the Related Art For example, a common drive semiconductor integrated circuit for LCDs
The circuit corresponds to the number N of clock pulses as shown in FIG.
Data coming in through the data signal input electrode 1 every
Data signal (display data signal) D_INClock electrode 2
The first stage is synchronized with the clock pulse CP
3₁From the last stage 3_NSerial transfer to
Through the external output electrode 4 for connecting the_NOutput
Q_NIs the output data signal D_OUTAs data output power
N bits (N) supplied from the pole 4 to the next similar integrated circuit
Stage) ・ Shift register circuit section 3 and its shift register
Data string ｛Q converted from serial to parallel by the circuit unit 3₁,
Q₂, ... Q_NLatch them correspondingly
N-bit latch circuit 5 and the output of each stage of this circuit 5
LCD drive from low voltage (3-5v) logic voltage level
N-bit level shift for boost conversion to operating voltage level
One-to-one correspondence between the circuit unit 6 and each output of the circuit unit 6
LCD drive power supply voltage V₀, V₂, V₃, V₅To
Selected and based on the AC waveform clock M applied to the electrode 9.
Then, each voltage is converted into an AC drive waveform to apply an applied voltage Y₁
~ Y _NOutput electrode 8₁~ 8_NN bits to send to
And a driver circuit section 7.

[0003] In the integrated circuit, the circuit configuration has an identical, it pair output electrode (pad) corresponding to 1 8 ₁ to 8 _N for each bit (each stage). Since the N-bit shift register circuit portion 3 and the N-bit latch circuit 5 is driven at a low voltage V _CC of the power supply voltage applied to the electrode 10 (3 to 5 V), the low voltage portion L. V. Is composed. On the other hand, N-bit level shift circuit units 6 and N
The bit driver circuit section 7 has electrodes 11, 12, 13, 1
4, the liquid crystal driving voltages V ₀ (for example, about 38 V), V ₂ (about 36 V), V ₃ (about ₂ V), V
₅ requires (approximately 0 v), also a high supply voltage _{V H} applied to the electrodes 15 is about 40v. Therefore, the N-bit level shift circuit section 6 and the N-bit driver circuit section 7 include the high-voltage section H.264. V. Is composed.

A pair with such a circuit cell (a cell composed of each bit 3 _i , 5 _i , 6 _i , 7 _{i of a} shift register circuit, a latch circuit, a level shift circuit, and a driver circuit) is formed. The general chip layout of the output electrode _8i employs a parallel array structure of each bit as shown in FIG. It should be noted that the solid line zigzag portion shown in FIG. As a whole, the cells and the electrodes are arranged symmetrically with respect to the center line in the X direction of the chip. That is, the cell array is divided into a first block 16 is divided into two tip region and a second block 17, each stage 3 ₁ to 3 _N shift register circuit portion in the chip inner region, and each stage of the driver circuit portion 7 _{1 to} 7
_N is formed on the edge side of the chip 18 (around the long side). Each stage of the output electrode ₈ 1-8 ₁ driver section 7
It is arranged in ₁ to _7-N outer (tip periphery). The high voltage V _H , the liquid crystal drive power supply voltages V ₀ , V ₂ ,
The wirings of V ₃ and V ₅ pass from the pads on the first block 16 of the driver circuit section 7 and the level shift circuit section 6 in the X direction, and extend in the −Y direction, and then on the second block 17 −. It extends in the X direction. In addition, low power supply voltage V
_{The CC} wiring also passes from the pad on the first block 16 of the latch circuit section 5 and the shift register circuit section 3 in the X direction and extends in the -Y direction, and then extends on the second block 17 in the -X direction. Are there.

The chip 18 of the LCD driving semiconductor integrated circuit having such a chip layout is mounted on a tape carrier (film) by, for example, a tape carrier method (T).
AB implementation). Further, as shown in FIG. 11, the chip 18 is directly mounted on the liquid crystal panel (COG mounting). That is, the liquid crystal panel is the lower glass substrate G ₁ and the upper glass substrate G ₂ and spacing held by spacer 19, which was filled with a liquid crystal material LC is the gap, the transparent column electrodes on the substrate and the transparent row electrodes 20 21 Are formed. As shown in FIG. 11B, on the surface of the frame region (non-display region) 22 of the glass substrate,
The chip 18 is directly mounted on a plane by COG (Chip On Glass) technology. The bump 2 is formed on the electrode (pad) of the chip 18.
The bumps and the transparent row electrodes 20 or the transparent column electrodes 21 are outer bonded by, for example, a thermocompression bonding method or a solder welding method. The lead 23 extending to the edge of the frame region 22 is a connection terminal with the wiring board (not shown).

[0006]

The above-mentioned power supply
In the chip 18 of the wiring layout, the power supply voltage
V_H , V₀, V₂, V₃, V₅, V_CCOr ground
The wiring of the voltage GND is the electrode on the chip surface around the chip surface.
Starting from (pad) and wrapping around in a U-shape (open loop)
Last stage 3 of the second block_N, 5_N, 6_N, 7
_NHas been interrupted. For this reason, each
The pressure tends to fluctuate differently from the value of the introduced voltage near each pad.
The wiring length (wiring impedance) increases toward the final stage
It is to increase. For example, the length of the liquid crystal power supply wiring is 10
Even when the wiring material is several mm or more and the wiring material is metal, the wiring resistance is
It has reached 0Ω. Such power supply voltage fluctuations or
Variations cause uneven contrast of the LCD display
I have. The power supply wiring is not interrupted at the last stage,
The final stage wiring and the first stage wiring are multi-layered
Connections can be made by wiring technology,
Since the number of cross points between power supply wiring and signal wiring increases, wiring
Inevitably introduces impedance variations,
The output characteristics of the circuit section become non-uniform for each bit. More
Without using multi-layer wiring technology,
It is possible to increase the wiring occupation area.
Good. To increase the chip size, as shown in FIG.
The width dimension W of the frame area 2 on which the
means. Non-display area of LCD panel
There is a request to reduce the width W of the area 22 as much as possible.
You. In particular, chips that support high-definition pixels in LCD panels
As the number of bits increases, the width W increases.
It tends to be forced, so the area occupied by wiring is further reduced.
Must be controlled.

In view of the above problems, an object of the present invention is to improve the chip layout in a semiconductor device having an array structure in which circuit cells and input or output electrodes form a pair, so that the wiring space is not increased. Another object of the present invention is to provide a semiconductor device that realizes uniform input or output characteristics by suppressing variations in wiring impedance of each cell, and provides a data input / output device that realizes a reduced chip mounting surface. Is to do.

[0008]

A semiconductor device such as an LCD driving IC has a circuit cell array composed of a plurality of cells having substantially the same circuit configuration. In a semiconductor device having such a circuit configuration, an electrode / wiring pattern having a pair of unique electrodes, such as one-to-one, for obtaining electrical connection with the outside of each cell is provided. In this type of semiconductor device, the present invention does not make the area of the circuit cell array, which is a core circuit configuration, closer to the peripheral part of the semiconductor chip as in the related art, but instead places the electrode in the inner area of the peripheral area of the semiconductor chip. And a layout in which a circuit cell array is formed in a non-peripheral region between the electrode column and the peripheral region of the semiconductor chip. According to the layout in which the electrode rows are arranged in the inner region, it is possible to plan a thinner chip, and it is also possible to prevent an edge short of a lead at the time of bonding the electrode and the lead in the lead mounting stage.

In such TAB mounting of a semiconductor chip or the like, the connection structure between the inner lead and the electrode is such that the electrode row and the chip side which is substantially parallel to the longer side of the chip are parallel to the inner side with respect to the electrode. It is desirable to connect the leads and increase the overlap length between the inner lead and the chip. As a chip mounting method for the substrate of the device, the outer lead side through the lead out from the inner lead is connected to the electrode wiring of the substrate, thereby compressing the substrate mounting area or occupied width due to the presence of the overlap length. be able to.

In a semiconductor device having a circuit cell array structure divided into two or more blocks, the electrodes of a plurality of cells are naturally connected to the first block in the first block.
In this case, the first circuit cell array belonging to the first block is provided with the first long side of the semiconductor chip. And a first non-peripheral region sandwiched between the first electrode row formed in the inner region and the first electrode row,
The second circuit cell array belonging to the second block has a second circuit cell array sandwiched between a second long side opposed to the first long side of the semiconductor chip and a second electrode row formed inside the second long side. A layout in which it is formed in a non-peripheral region is adopted. According to the semiconductor device having such a layout, of course, the overlap length between the chip and the inner lead can be increased, so that the same effects as described above can be obtained.

Although it is desirable that both electrode rows are arranged adjacent to each other, they need not be aligned. For example, when the electrode groups of both electrode rows are arranged in a staggered arrangement, the chip width can be reduced, and the chip mounting area width can be reduced. The arrangement of the power supply electrode or the ground electrode is desirably formed in a region adjacent to both ends or one end outside in the arrangement direction of the electrode row of the circuit cell array. This is because the electrode group becomes linear on the inner region of the chip. As a layout of the connection wiring in the chip having such a linear electrode group, it is desirable to use a closed loop wiring (ring connection) in which a plurality of wirings of the power supply electrode or the grounding electrode go around them. Shortening of the wiring length and reduction of the wiring cross points can be achieved at the same time, and the input or output characteristics for each bit can be made uniform. Furthermore, when a row of input / output electrodes for obtaining an electrical connection with the outside is formed in the short side region of the semiconductor chip adjacent to the power supply electrode or the ground electrode, all the electrodes are substantially I-shaped. Form. This I-shaped electrode arrangement exerts a self-parallelizing function by those electrodes in direct mounting of chips. As for the method of connecting the chip and the inner lead, it is desirable to adopt an inner lead having a double-hanging or double-supported beam structure with respect to the electrode of the circuit cell. By adopting the linear arrangement of the electrode group, it becomes easy to obtain the chip parallelism at the time of collective bonding, and a reduction in stress can be expected. Therefore, the yield of collective binding is improved by improving the alignment property. In addition, it is possible to prevent the chip active surface from being injured when bonding by shielding and covering the chip surface with the inner leads, and to improve the heat radiation characteristics. By mounting the chip on which such leads are mounted on the substrate by the above-described method, the width of the mounting area can be reduced and the device can be made more compact.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is a chip layout diagram of a semiconductor device according to Embodiment 1 of the present invention. It should be noted that the solid line zigzag portion shown in FIG.

The semiconductor chip 30 is an LCD driving type IC.
In order to suppress the width dimension of the frame region at the time of COG mounting, it is rectangular or elongated. The integrated circuit built in the chip 30 has an N-bit (for example, 100-bit) shift register circuit section 3, a latch circuit section 5, a level shift circuit section 6, and a driver as a core circuit configuration, as in the related art. A circuit section 7 is provided. And it unique output for each bit of the circuit array (driver output) Y _N rectangular output electrode (pad) 8 _N of is the shortest adjacent region of each stage 7 _N of the driver circuit portion 7. The circuit cell array is divided into a first block 31 and a second block 32. That is, the long side 31 of the chip
a, the first block 31 in its side regions as a substantial boundary center line L ₁ parallel to 32a and the second block 3
Two are sorted. The bits belonging to the first block 31 are 1 to i, and the bits belonging to the second block are i
+1 to N. Here, N is an even number. Accordingly, the cell area because substantially equal to each other, the first bit of the cell and the N-th bit of the cell on both sides with respect to the center line L _1, the second bit of the cell and N-1 bit of the cell as Are arranged. Focusing on one certain circuit cell, each stage of the shift register circuit unit 3 is formed on the peripheral region side of the chip 30, and each stage of the driver circuit unit is connected to the center line L _{1 of the} chip.
It is built on the side. Such a built-in form is exactly the opposite of the form of the conventional chip.
Thus, the signal electrodes 8 ₁ to 8 _N for each bit is formed in the X-axis strip region (central region) 33 along the center line L ₁ adjacent to the driver circuit portion. First block 3
The output electrodes 8 ₁ to 8 _i of the bits belonging to 1 and the output electrodes 8 _{i + 1} to 8 of the bits belonging to the second block 32.
_N are mutually arranged in a staggered pattern (zigzag pattern).
Output electrodes 8 _i , 8 adjacent to each other by such a staggered arrangement
Since _{i + 1} each other with overlapping portions in the Y direction, it is possible to suppress the chip width (Y direction length).
Also, the shift register circuit section 3 and the long sides 31a, 3 of the chip
2a is a region where no electrode (pad) is formed,
The shift register circuit section 3 should have the long sides 31a and 32 as long as possible.
It can be built up to a. From this point as well, the width dimension of the chip can be suppressed. Of course, the length of the chip (length in the X direction) is increased by that much, but the pixel of the LCD is sufficiently large with respect to the pitch of the output electrode 8 (about 80 microns). It is advantageous.

Outside the both ends of the circuit cell array formation region, the control logic portion 34,
35 are built. The power supply electrodes 10 to 15 and a rectangular ground electrode 19 of the rectangle are formed at both ends outside the output electrodes 8 ₁ to 8 _N forming region serving center line L ₁ of the band-like region 33. The length of the formation region in the X direction is the band-like region 33.
, And six electrodes (pads) are formed in two rows and three columns in the area. Each of the power supply electrodes 10 to 15 and the ground electrode 19 formed on the outer sides of both ends of the band-shaped region 33 has a center line L ₂ parallel to the short sides 35 a and 35 b.
Are symmetrically arranged with respect to Column centerline L ₂ side as shown in FIG. 1 is an electrode 15 of the power supply voltage V _H of the liquid crystal drive power source electrode 11 of the voltage V ₀ and the high-voltage power supply unit for supplying. Adjacent rows of outer this column is an electrode 12 of the electrode 13 of the liquid crystal driving power source voltage V ₃ crystal driving power supply voltage V _2. Electrode 1 of the outermost row of the left side is the electrode 19 of the ground voltage GND liquid crystal driving power source voltage V ₅
4. The outermost row on the right side of the figure shows the electrode 10 of the power supply voltage V _CC for supplying the low power supply section and the electrode 1 of the liquid crystal drive power supply voltage V ₅ .
4. Left and right electrodes 15, 15 of high power supply voltage V _H
The power supply wiring (Al wiring) 36 connected to the belt-like region 33 is adjacent to the band-shaped region 33 and circulates. The power supply wiring 36 supplies power to the driver circuit section 7 which is a high voltage section. One side electrode 15
Can be omitted, but is used when a cascade connection is made to similar chips. Similarly, the power supply wiring 37 connected to the left and right electrodes 11 and 11 of the liquid crystal drive power supply voltage V ₀ circulates adjacent to the outside of the power supply wiring 36 connected in a closed loop (ring connection). This power supply wiring 3
7 supplies power to the driver circuit section 7 which is a high voltage section.
Although the electrode 11 on one side can be omitted, it is used for cascade connection with a similar chip. The power supply wiring 38 connected to the electrodes 12, 12 of the left and right liquid crystal drive power supply voltages V _{2 in} the drawing also circulates adjacent to the outside of the closed-loop connection power supply wiring 37. The power supply wiring 38 also supplies power to the driver circuit section 7 which is a high voltage section. One electrode 12
Is an electrode for cascade connection. LCD drive power supply voltage V
_The power supply line 39 connected to the _third electrodes 13 also circulates outside the power supply line 38 in the closed loop connection. The area where the power supply wiring 38 is laid is near the level shift circuit section 6 of the driver circuit section 7 to supply power to the driver circuit section 7. One electrode 13 is an electrode for cascade connection.
Power wiring 40 connected to the electrodes 14, 14 of the last of the liquid crystal drive power supply voltage V ₅ is also orbiting adjacent the outer power supply wiring 39 of the closed-loop connection. The power supply wiring 40 supplies power to the driver circuit unit 7. One electrode 14 is an electrode for cascade connection. As described above, the power supply voltages V _H , V ₀ , V ₂ , V
₃ power supply wires 36,37,38,39,40 of, V ₅ is 1 cyclic closed loop connected around the output electrodes 8 ₁ to 8 _N of the inner region. Therefore, since these wirings do not cross each other, it is possible to suppress uneven display contrast due to uniform wiring impedance. FIG.
As is apparent from comparison with the wiring arrangement shown as 0, the wiring length of each power supply wiring is reduced. Each power supply wiring is because orbiting adjacent around the band-like region 33 of the center line L ₁ of the chip. In particular, the decrease in the length in the Y direction is remarkable. Therefore, the fluctuation or variation of the power supply voltage of each bit due to the decrease of the wiring resistance can be suppressed.
This also improves the uneven display contrast.

The ground wiring connected to the electrode 19 of the ground voltage GND is branched into three on each of the first block 31 side and the second block side 32, and the ground wiring 41 on the inner side is connected to the driver circuit section 7. In the boundary area between the level shift circuit section 6 and the level shift circuit section 6, the intermediate ground wiring 42 is provided in the boundary area between the level shift circuit section 6 and the latch circuit section 5, and the outer ground wiring 43 is provided in the outer area of the shift register circuit section 3. Has been laid. A first block 31 outside of the power supply wiring 44 which is branched from the power supply line 36 of the power supply voltage V _H in each of the second blocks 32 is laid on the level shift circuit 6. Furthermore, the electrode 10 of the low-voltage power supply _VCC
Are provided in the boundary area between the latch circuit section 5 and the shift register circuit section 3. The ground wirings 41, 42, 43, the branched power supply wiring 44, and the normal power supply wiring 45 can also be connected in a closed loop.
Since the display characteristics are not affected, the embodiment is in an open loop state as in the prior art.

The low-voltage power supply voltage _VCC and the ground voltage GND are also supplied to the logic controllers 35 and 36. The data signal D is located in the central area near the short sides 35a and 35b of the chip.
Required input / output signal electrode row 4 such as _IN , output data D _OUT , clock pulse CP, AC waveform clock M, etc.
6, 47 are formed. For this reason, the groups of electrodes 8 ₁ to 8 _{N, 10} to 15 _and 19 along the center line L ₁ and the rows 46 and 47 of input / output signal electrodes orthogonal to both ends of the group are formed by I
It is shaped like a letter. The first block 31 on either side of the center line L ₁ as a boundary and the division circuit layout in the second block 32, even because it is equal in both blocks, on both sides to the input and output signal electrodes even boundary center line L ₁ It is desirable to assign to. This is for achieving the symmetry of the layout of these signal wirings and the equality of the wiring length. I-shaped electrode group, as described below, wearing substrate straight chip (COG) is also possible to secure the superiority in the implementation, orthogonal to the input and output signals at both ends of the linear electrode group along the center line L ₁ The presence of the electrode rows 46 and 47 facilitates parallelization of the chip itself during COG mounting. Of course, the paralleling process does not depend only on the input / output signal electrode rows 46 and 47, but the longer the chip length (the length in the X direction), the more significant the significance.

In this embodiment, dummy electrodes (dummy pads) 48a to 48d for positioning and supporting are formed separately at the corners of the chip. In order to increase the number of bits, signal electrodes for driver output are conventionally formed at the corners of the chip as shown in FIG. 10, and it has been problematic to provide dummy electrodes for positioning. examples formed in a strip region 33 of the center line L ₁ is the driver output signal electrode group, moreover since the row of input and output electrodes also formed on both ends thereof, the dummy electrodes 48a to corner
There is a derivative benefit that can secure ~ 48d.

FIG. 2 is a cross-sectional view showing the chip according to this embodiment in a TAB mounting state, and FIG. 3 is a plan view thereof. The chip 30 having the above-described layout configuration shows the state of the stage of the diffused wafer. After that, Au bumps 51 are formed on the respective electrodes (pads), and the wafer with bumps is completed. Be transformed into (Chip process). On the other hand, the tape carrier (film) 52 used in the assembling process has a sprocket hole 52a and a device hole 52b in which a lead pattern corresponding to the electrode arrangement of the chip 30 is formed.
Is formed on a plastic film (for example, a polyimide film) having. The opening area of the device hole 52a is smaller than the plane area of the chip 30, substantially, the central band-like region which is formed on the output electrode 8 _1-8 chip 30
It is limited to only a region where the bump 51 such as _N is exposed in a plane. This tape carrier 52 has a device hole 52.
In addition, slits 53a and 53b for wrapping around the resin are provided outside a. The tape carrier 52 is a film with an adhesive (2) in which an adhesive layer 55 is adhered on a plastic film 54.
Layer film). A metal foil such as a copper foil is laminated on this film, and a lead pattern as shown in FIG. 3 is formed using a photoresist technique or an etching technique. The lead pattern protrudes into the device hole 52a, and includes a finger lead (inner lead) 56 to be subjected to inner lead bonding with the bump 51;
It has an outer lead 57 to be bonded to a row or column electrode on the LCD panel side and an outer lead, and a lead lead portion 58 for integrally connecting the finger lead 56 and the outer lead 57. Note that a lead lead portion 58 connected to the printed wiring board side of the film 52.
A terminal 58 is formed at the tip of the.

An assembling process (TAB mounting) of the tape carrier 52 manufactured by such a tape process and the above-described chip 30 with bumps is performed. That is, the chip 30 is fed up with the finger lead 5 while the tape is being fed.
6 and the finger lead 51 and the bump 51 are subjected to inner lead bonding by a bonding tool. Thereafter, the chip 30 is sealed with a molding resin 59 by a potting method. At the time of potting, since the film 52 itself has slits 53a and 53b for wrapping around the resin outside the device hole 52, the entire surface of the chip 30 can be completely sealed.
Of course, by setting the opening area of the device hole 52a to be equal to or larger than the area of the chip 30, the unsealed portion of the resin mold can be eliminated. However, the device hole 52a of the film 52 and the slit for the resin 53a,
Opening edge portions 60a and 60b with 53b serve as a backing reinforcement portion of the lead. These opening edges 60
a, because 60b is present near the bumps 51 of substantially the chip 30, the cantilever length of the finger leads 56 (projecting length) is _{Y 1.} Opening edge portion 60a, since the cantilever length when 60b is not present is a _{Y 2, Y 1}
<In _{Y 2,} shortening the length of the beam length (overhang length) is substantially _Y 2 -Y _1. The shorter the length of the finger lead 56 is, the easier the alignment at the time of inner lead bonding is, and the stronger the support force of the chip can be. Further, since the bumps 51 are arranged in a straight line, the alignment property at the time of collective bonding is improved, and the bonding property is not impaired even in a large-sized chip. Since the inner lead group covers almost the entire surface of the chip, damage to the chip surface by the collective bonding tool can be suppressed. Collective bonding is possible even when the bump pitch is a fine pitch of 100 microns or less. The point that the amount of bending is reduced by the shortened finger lead 56 and the bump 51 or the electrode (pad) is formed on the chip 3
Since the finger lead 56 and the edge of the chip 30 do not easily come into contact with each other since they are formed in the central region of 0, edge short-circuiting can be prevented. This can eliminate the danger of contact between the two by the weight of the molding resin 59 particularly by potting. When there is no opening edge portion 60a, 60b, there is no advantage in the ease of alignment between the finger lead 56 and the bump 51, but an insulating layer can be formed on the finger lead 56 near the chip edge. This is because the bump 51 is not formed near the chip edge.
Also in such a case, edge short-circuit can be prevented.
Further, the heat radiation characteristic is improved by the inner lead group covering the chip surface.

FIG. 4 is a sectional view showing another TAB mounting state of the above-mentioned chip. In this tape carrier 60, the inner leads 61 protruding into the device holes 52b have a doubly supported structure with respect to the film. Since the bumps 51 are present in the central region (inner region) of the chip 30, there is no necessity for the inner lead to have a cantilever structure. According to this doubly supported or double suspended structure, FIG.
As compared with the cantilever structure shown in FIG. 1, the accuracy of alignment with the bumps 51 is further improved, and the support force is doubled. Of course,
The problem of chip edge short does not occur. Furthermore, damage prevention on the chip surface can be ensured, and the heat radiation characteristics are also excellent.

FIG. 5A shows a frame region 62 of the liquid crystal panel.
It is a top view showing the state where COG mounting was carried out. LCD panel
The lead-out lead portion 58 of the lead is a flat surface of the chip 30.
It overlaps on top. By the way, in general, withdraw
The lead portion 58 starts from the pitch of the bump 51 and
The significance of gradually adjusting to longer pixel row or column spacing
is there. The finer the pitch of the bumps 51, the more the pull
It is necessary to increase the length of the extension lead portion 58. Succumb
The tighter the curvature, the longer the distance between leads
This is because it becomes smaller than the height and it becomes easy to short-circuit.
Therefore, it is necessary to increase the number of bits or the electric power in LCD driving ICs, etc.
Suppresses lead bending under extremely fine pitch
Drawer lead portion 58 is inevitable
Must be longer. Such drawer lead
The lengthening of the minute 58 is the glass substrate G₁ , G₂Of the picture frame area
This results in increasing the width dimension (overhang length). But
In this embodiment, as shown in FIG.
All of the tape portions 58 are on the tape carrier 52
Instead, a part 58a of the extraction lead portion 58 is not
Overlaps the loop 30. This is bump 51
Is formed in the central area of the chip 30,
Drawn between the pump 51 and the long side 31a, 32a of the chip 30
This is because a portion 58a of the lead portion 58 can be formed.
You. The length of the overlap portion 58a is the same as the length of
Reduced length Y of inner lead 56₂-Y ₁And practically
equal. Therefore, according to the schematic evaluation, FIG.
As shown in FIG.
Its width dimension W₁Is 2 (Y₂-Y₁Only) small.
The compression of the width dimension of the frame region 62 indicates that the non-display area
Means shrinking or slenderness, and means that
Liquid crystal display devices that are compact or have external appearance (design
Contributing to the improvement of In other words, the width of the frame area 62
It is possible to increase the number of bits in a chip without increasing the size.
Elongation can be achieved.

[0022]

FIG. 6 is a chip layout diagram of a semiconductor device according to a second embodiment of the present invention.

This semiconductor chip 70 is also an LCD drive type IC.
In order to reduce the width of the frame area during COG mounting
In a rectangular or elongated shape. This chip 70
The embedded integrated circuit is the same as in the first embodiment.
The n-bit shift register circuit section 3
Switch circuit 5, level shift circuit 6, and driver circuit
A part 7 is provided. And only one block of circuit cells
Each bit of the ray has its own output (driver output) Y
₁~ Y_nRectangular output electrode (pad) 8₁ ~ 8_n
Are the respective stages 7 of the driver circuit section 7.₁~ 7_nShortest neighbor
Formed in the area. n-bit shift register circuit
3 is built in the peripheral area of the long side 71a,
The bus circuit section 7 is formed in the chip inner area. Soshi
The output electrodes (pads) 8 are formed in a line in the X direction.
You.

FIG. 6 shows the outside of both ends of the cell array forming region.
Control logic units 72 and 73
Is built in. The center of the peripheral area of the long side 71b
The control logic part 74 indicated by the dashed line is also built in the part
Have been. Data in the X direction inside the control logic 74
Signal D_IN, Output data D_OUT, Clock pulse C
P, required input / output signal electrodes of AC waveform clock M, etc.
A row 75 is formed which is adjacent and parallel to the row of output electrodes 8.
are doing. The rectangular power supply electrodes 11 to
14 and a rectangular ground electrode 19 or low-voltage power supply electrode 10 are formed.
Have been. A high-voltage power supply
An electrode 15 is formed. Therefore, the electrode group on the chip
Are arranged in two rows in the X direction. High left and right power supply voltage shown
V_HThe power supply wiring 76 connected to the electrodes 15
Close to row 8. This power supply wiring 36 is a high voltage part.
The power is supplied to the driver circuit unit 7. One side electrode 15
Can be omitted.
Used when connecting with a cable. Similarly, the left
Right LCD drive power supply voltage V₀Electrodes 11 and 11
The power supply line 77 is adjacent to the long side 71a of the power supply line 36.
ing. This power supply wiring 77 is a driver circuit which is a high voltage part.
Power is supplied to the unit 7. Omit electrode 11 on one side
Can be cascaded to similar chips
Used in cases. Left and right liquid crystal drive power supply voltage V₂
The power supply wiring 78 connected to the electrodes 12, 12 is also the power supply wiring 7
7 is adjacent to the long side 71a side. This power supply wiring 78
Power is supplied to the driver circuit section 7 which is a high voltage section. one side
Are electrodes for cascade connection. LCD drive
Power supply voltage V₃Power supply wiring 7 connected to the electrodes 13
Reference numeral 9 also extends toward the long side 71a of the power supply wiring 78. this
The laying area of the power supply wiring 78 is the level system of the driver circuit section 7.
Power is supplied to the driver circuit section 7 near the shift circuit section 6.
You. One electrode 13 is a cascade connection electrode.
is there. Last liquid crystal drive power supply voltage V₅Electrodes 14, 14
The power supply line 80 connected to the power supply line 79 is also on the long side 71a side.
Is adjacent to The power supply wiring 70 is connected to the driver circuit section 7.
Power is supplied to One electrode 14 is cascaded
It is an electrode for connection. Thus, the driver circuit unit 7
Power supply voltage V to be supplied_H, V₀, V₂, V
₃, V₅Power supply wiring 76, 77, 78, 79, 80
Are parallel on that area. These wirings are
It is not a closed loop connection that goes around the column once, but the power supply voltage V_H
Electrodes 15 are formed at both ends of the column of the electrodes 8 and the power supply voltage V
₀, V₂, V₃, V₅Electrodes 11, 12, 13,
14 and the number of electrodes at both ends of the row of the electrode 8 constitute two rows.
You. The ground wiring connected to the electrode 19 of the ground voltage GND is 3
The book is branched, and the ground wiring 81 inside it is dry.
In the boundary area between the circuit section 7 and the level shift circuit section 6,
The ground wiring 82 between the level shift circuit 6 and the latch circuit
The outer ground wiring 83 is connected to the shift register
Each of them is laid in a region outside the star circuit portion 3. In addition,
Source voltage V_HOutside power supply branched from the power supply wiring 36
The wiring 84 is laid on the level shift circuit section 6.
Furthermore, a low voltage power supply V_CCPower supply wiring connected to the electrode 10
85 is a boundary area between the latch circuit unit 5 and the shift register unit 3
Is laid. And the electrodes 11, 12, 13, 1
A row 75 of input / output signal electrodes intervenes in the middle area of row 4
I have.

As described above, according to the layout in which the power supply wiring is routed around both ends of the column of the electrodes 8, the wiring length of the power supply wiring or the signal wiring can be suppressed as compared with the conventional method.
The present example provides a suitable layout of electrodes and wirings corresponding to a thinner chip. 73a and 73b are long sides 7
A dummy electrode (pad) for positioning and assisting is formed at a corner portion on the side of 1a.

FIG. 7 shows the TAB of the chip according to the above embodiment.
It is a top view showing a mounting state. In FIG.
The same reference numerals are given to the same portions as the portions, and the description thereof is omitted.
Abbreviate. A chip 70 having the above-described layout configuration
The tape carrier (film) 92 for the
The lead pattern according to the pole arrangement is the sprocket hole 52a.
And formed on plastic film with device holes 92b
Has been established. This tape carrier 92 has a different opening area.
With slits 93a and 93b for wrapping around the resin
I have. The lead pattern protrudes into the device hole 92a.
And the inner lead is bonded to the bump 51
Shoulder finger lead (inner lead) 56 and LC
Row or column electrode on D panel side and outer lead bondin
Outer leads 57 to be plugged and finger leads
A drawer that integrally connects the outer lead 57 and the outer lead 57
And a card portion 88. In addition, film 5
2 the end of the lead-out lead portion 88 connected to the printed wiring board side
A terminal 58 is formed at the end. Such a tape mechanic
Tape carrier 92 and bumps described above
TAB mounting of the chip with chip 70 is performed in the same manner as in the first embodiment.
Is Cantilever length of finger lead 56 (overhang length
Sa) is Y₁It is. Opening edge 70b on the LCD panel side
The length of the cantilever beam without Y₃Because
Y₁<Y₃ And the shortened length of the beam length (extended length) is substantial
Typically Y₃-Y₁It is. This shortened length is
Y₂-Y₁Is greater.

FIG. 8A is a plan view showing a state in which the chip is mounted on the frame area 102 of the liquid crystal panel by COG after TAB mounting. In the figure, the same parts as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. Also in this mounting, a part 88 a of the lead-out lead portion 88 overlaps the chip 30. This is because the bump 51 is formed apart from the long side 71a of the chip 70. This overlap portion 88a
Is the shortened length Y ₃ of the inner lead 56 described above.
-Y ₁ substantially equal. Considering that the width dimension of the chip 70 can be reduced as compared with that of Example 1, as shown in FIG. 8 (B), the width W ₂ of the frame region 102 of the present embodiment the width W of Example 1 It can be smaller than ₁ .

[0028]

As described above, the semiconductor device provided with the circuit cell array according to the present invention is not limited to the LCD driver IC, but may be a display driver IC, a printer driver IC, a sensor interface IC, a gate array, or the like. It can be widely applied to an IC having an array structure in which a circuit cell and its electrode are paired or a multi-output or multi-input multi-bit IC, and is suitable for saving the width of a mounting area in a data input or output device. ing.

[Brief description of the drawings]

FIG. 1 is a layout diagram illustrating a chip of a liquid crystal driving semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a state in which the chip according to the first embodiment is mounted on a TAB.

FIG. 3 is a plan view illustrating a state in which the chip according to the first embodiment is mounted on a TAB;

FIG. 4 is a sectional view showing a TAB mounting state different from the TAB mounting.

FIG. 5A is a plan view showing a state where the chip according to the first embodiment is COG-mounted in a frame region of a liquid crystal panel, and FIG.
FIG. 3 is a cross-sectional view showing a frame region side in the same state.

FIG. 6 is a layout diagram illustrating a chip of a liquid crystal driving semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a plan view illustrating a state in which the chip according to the second embodiment is mounted on a TAB;

FIG. 8A is a plan view showing a state where the chip according to the second embodiment is COG-mounted in a frame region of a liquid crystal panel, and FIG.
FIG. 3 is a cross-sectional view showing a frame region side in the same state.

FIG. 9 is a block diagram showing a general circuit configuration of a liquid crystal driving semiconductor device.

FIG. 10 is a layout diagram showing a chip of a conventional liquid crystal driving semiconductor device.

FIG. 11 is a plan view showing a state where the chip is mounted on a frame area of a liquid crystal panel by COG.

[Explanation of symbols]

3: shift register circuit portion 5 ... latch circuit portions 6 the level shift circuit 7 ... driver circuit portion 7 N _... each stage 8 of the driver circuit portion N _... output electrode (pads) 10 to 15 ... power electrode 19 ... ground electrode 30 , 70 ... semiconductor chip 31 ... first block 32 ... second block 31a, 32a, 71a, 71b ... chip long side 33 ... X-direction band-shaped area (central area) 34, 35, 72, 73, 74 ... control Logic part 35a, 35b: Short side of chip 36, 37, 38, 39, 40, 44, 45 ... Power supply wiring (Al wiring) 41, 42, 43 ... Grounding wiring 46, 47, 75 ... Column of input / output signal electrodes 48a to 48d, 73a, 73b: Dummy electrode (dummy pad) 51: Bump 52, 60, 92 ... Tape carrier (film) 52a: Sprocket hole 52b, 92 ... Device holes 53a, 53b, 93a, 93b ... Slits 54 ... Plastic films 55 ... Adhesive layers 56, 61 ... Finger leads (inner leads) 57 ... Outer leads 58, 88 ... Lead-out lead portions 59 ... Molding resin 60a, 60b ... opening edge 62 ... frame region 76,77,78,79,80,84,85 ... power supply wiring of the liquid crystal panel 81, 82, 83 ... ground line L _1, L 2 _... center line Y N _... driver output Y _1, Y ₂ : Cantilever length (extended length) of finger lead V _H , V _CC , V ₀ , V ₃ , V ₂ , V ₅ : Power supply voltage

As described above, the semiconductor device provided with the circuit cell array according to the present invention is not limited to the LCD driver IC, but may be a display driver IC, a printer driver IC, a sensor interface IC, a gate array, or the like. It can be widely applied to an IC having an array structure in which a circuit cell and its electrode are paired or a multi-output or multi-input multi-bit IC, and is suitable for saving the width of a mounting area in a data input or output device. ing.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60

Claims (4)

(57) [Claims] 1. A substantially rectangular shape having long sides (31a, 31a).
b, 71a, 71b) output pads are arranged in rows in a direction _{(Y 1 ~ Y N, Y} 1 ~ Y n, V 0, V 2, V 3, V 5,
V _H, V _CC, chips with 19,46,47) (3
0, 70), and a carrier thin film having an opening and a plurality of wirings arranged thereon, wherein the carrier thin film is arranged on the chip such that the opening is on the input / output pad. And the input / output pad and the wiring are electrically connected via the opening, and the carrier thin film and the chip overlap,
The semiconductor device according to claim 1, wherein a distance between the plurality of wirings increases as the distance from the pad increases in a region where the carrier thin film and the chip overlap. 2. The chip according to claim 1, wherein said chip is a dummy pad supporting said carrier thin film.
73a, 73b). 3. The semiconductor device according to claim 1, wherein the input / output pads are arranged in two rows along the long side direction. 4. The semiconductor device according to claim 1, further comprising two circuit blocks, wherein the input / output pad is interposed between the two circuit blocks. A semiconductor device characterized by the above-mentioned.