JP3262115B2 - Semiconductor chip package and display using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display driver IC such as an LCD driver, a multi-bit drive IC such as a printer driver IC, a multi-input / output IC such as a sensor interface IC, a gate array, and the like. More specifically, the present invention relates to a semiconductor device having an array structure in which a plurality of circuit cells having the same circuit configuration and their input or output electrodes are arranged in pairs and a data input / output device using the same.

[0002]

2. Description of the Related Art For example, as shown in FIG. 9, a common drive semiconductor integrated circuit for an LCD has a data signal (display data signal) input via a data signal input electrode 1 at every cycle corresponding to the number N of clock pulses. ) D _IN is synchronized with the clock pulse CP coming through the clock electrode 2 to
Sequentially serially transferred from ₁ to final stage 3 _N, via the cascade connection for external output electrodes 4 next similar integrated from the data output electrode 4 to the output Q _N of the final stage 3 _N as the output data signal D _OUT and N-bit (N-stage) shift register circuit portion 3 for supplying the circuit, the shift register circuit portion 3 serial-parallel converted data sequence _{{Q 1, Q 2, ···} Q N} they correspond to N-bit latch circuit 5 for latching
An N-bit level shift circuit unit 6 for boosting the output of each stage of the circuit unit 5 from a low voltage (3 to 5 V) logic voltage level to an LCD drive voltage level;
LCD drive power supply voltages V ₀ ,
V _2, V _3, V ₅ is selected, the voltage applied to the respective voltage into an AC drive waveform based on an AC waveform of the clock M applied to the electrode 9 Y ₁ to Y _N output electrodes 8 ₁ to 8 _N And an N-bit driver circuit section 7 for transmitting the data to

In this integrated circuit, each bit (each stage) has the same circuit configuration, and has output electrodes (pads) 8 ₁ to 8 _N corresponding one-to-one. The N-bit shift register circuit unit 3 and the N-bit latch circuit unit 5 operate at a low voltage V of the power supply voltage (3 to 5 V) applied to the electrode 10.
It is driven by _CC, low voltage portion L. V. Is composed. On the other hand, the N-bit level shift circuit section 6 and the N-bit driver circuit section 7 provide a liquid crystal driving voltage V ₀ (eg, about 38) applied to the electrodes 11, 12, 13, and 14, respectively.
v), V ₂ (about 36v), V ₃ (about 2v), V ₅ (about 0
v) and the high power supply voltage V _H applied to the electrode 15 is about 40v. Therefore, the N-bit level shift circuit section 6 and the N-bit driver circuit section 7 include the high-voltage section H.264. V. Is composed.

A pair with such a circuit cell (cell composed of each bit 3 _i , 5 _i , 6 _i , 7 _{i of a} shift register circuit, a latch circuit, a level shift circuit, and a driver circuit) is formed. As shown in FIG. 10, the general chip layout of the output electrode _8i adopts a parallel array structure of each bit. It should be noted that the solid line zigzag portion shown in FIG. As a whole, the cells and the electrodes are arranged symmetrically with respect to the center line in the X direction of the chip. That is, the cell array is divided into a first block 16 is divided into two tip region and a second block 17, each stage 3 ₁ to 3 _N shift register circuit portion in the chip inner region, and each stage of the driver circuit portion 7 _{1 to} 7 _N are chips 18
Is formed on the edge side (around the long side). Output electrodes 8 _{1-8 1} are arranged outside the respective stages 7 ₁ to _7-N of the driver unit (the chip peripheral). Wirings for the high voltage V _H and the liquid crystal drive power supply voltages V ₀ , V ₂ , V ₃ , and V ₅ pass from each pad on the first block 16 of the driver circuit section 7 and the level shift circuit section 6 in the X direction, and After extending in the −Y direction, it extends on the second block 17 in the −X direction. The wiring of the low power supply voltage V _CC also passes from the pad on the first block 16 of the latch circuit section 5 and the shift register circuit section 3 in the X direction, and after extending in the −Y direction, on the second block 17. It extends in the -X direction.

The chip 18 of the LCD driving semiconductor integrated circuit having such a chip layout is mounted on a tape carrier (film) by, for example, a tape carrier method (T).
AB implementation). Further, as shown in FIG. 11, the chip 18 is directly mounted on the liquid crystal panel (COG mounting). That is, the liquid crystal panel has a lower glass substrate G ₁ and an upper glass substrate G ₂ spaced by a spacer 19, and the gap is filled with a liquid crystal material LC. On the substrate, a transparent row electrode 20 and a transparent column electrode 21 are provided. Are formed. As shown in FIG. 11B, CO 2 is provided on the surface of the frame region (non-display region) 22 of the glass substrate.
The chip 18 is directly mounted on a plane by G (Chip On Glass) technology. A bump 20 is attached on the electrode (pad) of the chip 18, and the bump and the transparent row electrode 20 or the transparent column electrode 21 are outer bonded by, for example, a thermocompression bonding method or a solder welding method. The lead 23 extending to the edge of the frame region 22 is a connection terminal with the wiring board (not shown).

[0006]

Meanwhile [0006] In the chip 18 of the above-described power supply wiring layout, the power supply voltage _{V H, V 0, V 2} , V 3, V 5, V CC and the ground voltage GND
Is started from the electrodes (pads) at the periphery of the chip, goes around in a U-shape (open loop shape), and is interrupted at the final stage 3 _N , 5 _N , 6 _N , 7 _N of the second block. I have.
For this reason, each voltage in the last stage is apt to fluctuate differently from the value of the introduced voltage near each pad. This is because the wiring length (wiring impedance) increases toward the final stage. For example, the length of the liquid crystal power supply wiring is more than 10 mm and the wiring resistance reaches several tens Ω even when the wiring material is metal. Such fluctuations or variations in the power supply voltage cause uneven contrast in the liquid crystal display. The wiring of the final stage and the wiring of the initial stage can be connected by the multilayer wiring technology so that the power wiring is not interrupted at the final stage but makes one circuit (loop), but between the power wiring and between the power wiring and the signal wiring. , The variation in wiring impedance is inevitably caused, and the output characteristics of the driver circuit unit become non-uniform for each bit. Of course, without using the multi-layer wiring technology, it is also possible to route the wiring to form a loop, but this increases the area occupied by the wiring. An increase in chip size means an increase in the width W of the frame region 2 on which the chip 18 is to be mounted, as shown in FIG. In a liquid crystal panel, there is a demand that the width dimension W of the frame region 22, which is a non-display region, be reduced as much as possible. In particular, in a situation where the number of bits of the chip 18 is increased in response to the increase in the number of pixels of the liquid crystal panel, the width W tends to be increased, so that the area occupied by the wiring must be further reduced.

In view of the above problems, an object of the present invention is to improve the chip layout in a semiconductor device having an array structure in which circuit cells and input or output electrodes form a pair, so that the wiring space is not increased. Another object of the present invention is to provide a semiconductor device that realizes uniform input or output characteristics by suppressing variations in wiring impedance of each cell, and provides a data input / output device that realizes a reduced chip mounting surface. Is to do.

[0008]

Means for Solving the Problems A semiconductor chip mounting body of the present invention includes a substrate on which a wiring pattern is formed, a rectangular shape
Having an external connection electrode on the plane
An external connection between the substrate and the semiconductor chip.
A mounting body of a semiconductor chip mounted with the surface for forming a connection electrode facing each other, wherein the external connection electrode is the semiconductor
Along an imaginary center line between the first long side and the second long side of the chip
Is arranged roughly, and is connected to the external connection electrode.
At least part of the wiring pattern extending to the long side
The wiring pattern is characterized in that a bent portion is formed in a portion of the wiring pattern located in a region overlapping with the chip. Further, a semiconductor device such as an LCD driving IC has a circuit cell array composed of a plurality of cells having substantially the same circuit configuration. In a semiconductor device having such a circuit configuration, an electrode / wiring pattern having a pair of unique electrodes, such as one-to-one, for obtaining electrical connection with the outside of each cell is provided. In this type of semiconductor device, the present invention does not make the area of the circuit cell array, which is a core circuit configuration, closer to the peripheral part of the semiconductor chip as in the related art, but instead places the electrode in the inner area of the peripheral area of the semiconductor chip. And a layout in which a circuit cell array is formed in a non-peripheral region between the electrode column and the peripheral region of the semiconductor chip. According to the layout in which the electrode rows are arranged in the inner region, it is possible to plan a thinner chip, and it is also possible to prevent an edge short of a lead at the time of bonding the electrode and the lead in the lead mounting stage.

In such TAB mounting of a semiconductor chip or the like, the connection structure between the inner lead and the electrode is such that the electrode row and the chip side which is substantially parallel to the longer side of the chip are parallel to the inner side with respect to the electrode. It is desirable to connect the leads and increase the overlap length between the inner lead and the chip. As a chip mounting method for the substrate of the device, the outer lead side through the lead out from the inner lead is connected to the electrode wiring of the substrate, thereby compressing the substrate mounting area or occupied width due to the presence of the overlap length. be able to.

In a semiconductor device having a circuit cell array structure divided into two or more blocks, the electrodes of a plurality of cells are naturally connected to the first block in the first block.
In this case, the first circuit cell array belonging to the first block is provided with the first long side of the semiconductor chip. And a first non-peripheral region sandwiched between the first electrode row formed in the inner region and the first electrode row,
The second circuit cell array belonging to the second block has a second circuit cell array sandwiched between a second long side opposed to the first long side of the semiconductor chip and a second electrode row formed inside the second long side. A layout in which it is formed in a non-peripheral region is adopted. According to the semiconductor device having such a layout, of course, the overlap length between the chip and the inner lead can be increased, so that the same effects as described above can be obtained.

Although it is desirable that both electrode rows are arranged adjacent to each other, they need not be aligned. For example, when the electrode groups of both electrode rows are arranged in a staggered arrangement, the chip width can be reduced, and the chip mounting area width can be reduced. The arrangement of the power supply electrode or the ground electrode is desirably formed in a region adjacent to both ends or one end outside in the arrangement direction of the electrode row of the circuit cell array. This is because the electrode group becomes linear on the inner region of the chip. As a layout of the connection wiring in the chip having such a linear electrode group, it is desirable to use a closed loop wiring (ring connection) in which a plurality of wirings of the power supply electrode or the grounding electrode go around them. Shortening of the wiring length and reduction of the wiring cross points can be achieved at the same time, and the input or output characteristics for each bit can be made uniform. Furthermore, when a row of input / output electrodes for obtaining an electrical connection with the outside is formed in the short side region of the semiconductor chip adjacent to the power supply electrode or the ground electrode, all the electrodes are substantially I-shaped. Form. This I-shaped electrode arrangement exerts a self-parallelizing function by those electrodes in direct mounting of chips. As for the method of connecting the chip and the inner lead, it is desirable to adopt an inner lead having a double-hanging or double-supported beam structure with respect to the electrode of the circuit cell. By adopting the linear arrangement of the electrode group, it becomes easy to obtain the chip parallelism at the time of collective bonding, and a reduction in stress can be expected. Therefore, the yield of collective binding is improved by improving the alignment property. In addition, it is possible to prevent the chip active surface from being injured when bonding by shielding and covering the chip surface with the inner leads, and to improve the heat radiation characteristics. By mounting the chip on which such leads are mounted on the substrate by the above-described method, the width of the mounting area can be reduced and the device can be made more compact.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is a chip layout diagram of a semiconductor device according to Embodiment 1 of the present invention. It should be noted that the solid line zigzag portion shown in FIG.

The semiconductor chip 30 is an LCD driving type IC.
In order to suppress the width dimension of the frame region at the time of COG mounting, it is rectangular or elongated. The integrated circuit built in the chip 30 has an N-bit (for example, 100-bit) shift register circuit section 3, a latch circuit section 5, a level shift circuit section 6, and a driver as a core circuit configuration, as in the related art. A circuit section 7 is provided. Each bit of the circuit cell array has a rectangular output electrode (pad) 8 _N of its own output (driver output) Y _N formed in the shortest adjacent region of each stage 7 _N of the driver circuit section 7. The circuit cell array includes a first block 31 and a second block 3
It is divided into two. That is, the long sides 31a, 32 of the chip
the first block 31 in the side regions is the second block 32 are distributed as a substantial boundary center line L ₁ is parallel to a. The bit belonging to the first block 31 is 1
, The bits belonging to the second block are i + 1 to N. Here, N is an even number. Accordingly, since the cell area substantially equal to each other, the both sides with respect to the center line L ₁ 1
They are arranged like a cell at the bit, a cell at the Nth bit, a cell at the second bit, and a cell at the (N−1) th bit. Focusing on one circuit cell, the shift register circuit unit 3
Each stage is built in the peripheral area of the chip 30, each stage of the driver circuit portion is fabricated in the center line L ₁ of the chip of the. Such a built-in form is exactly the opposite of the form of the conventional chip. Thus, the signal electrodes 8 ₁ to 8 _N for each bit is formed in the X-axis strip region (central region) 33 along the center line L ₁ adjacent to the driver circuit portion. The output electrodes 8 ₁ to 8 _i of the bits belonging to the first block 31 and the output electrodes 8 _{i + 1} to 8 _N of the bits belonging to the second block 32 are arranged in a zigzag pattern. Since the output electrodes 8 _i and 8 _{i + 1} adjacent to each other in the staggered arrangement have an overlapping portion in the Y direction, the width of the chip (the length in the Y direction) can be suppressed. The shift register circuit section 3 and the long side 3 of the chip
1a and 32a are regions where no electrode (pad) is formed.
a, up to 32a. From this point as well, the width dimension of the chip can be suppressed. Of course, the length of the chip (length in the X direction) is increased by that much, but the pixel of the LCD is sufficiently large with respect to the pitch of the output electrode 8 (about 80 microns). It is advantageous.

Outside the both ends of the circuit cell array formation region, the control logic portion 34,
35 are built. The power supply electrodes 10 to 15 and a rectangular ground electrode 19 of the rectangle are formed at both ends outside the output electrodes 8 ₁ to 8 _N forming region serving center line L ₁ of the band-like region 33. The length of the formation region in the X direction is the band-like region 33.
, And six electrodes (pads) are formed in two rows and three columns in the area. Each of the power supply electrodes 10 to 15 and the ground electrode 19 formed on the outer sides of both ends of the band-shaped region 33 has a center line L ₂ parallel to the short sides 35 a and 35 b.
Are symmetrically arranged with respect to Column centerline L ₂ side as shown in FIG. 1 is an electrode 15 of the power supply voltage V _H of the liquid crystal drive power source electrode 11 of the voltage V ₀ and the high-voltage power supply unit for supplying. Adjacent rows of outer this column is an electrode 12 of the electrode 13 of the liquid crystal driving power source voltage V ₃ crystal driving power supply voltage V _2. Electrode 1 of the outermost row of the left side is the electrode 19 of the ground voltage GND liquid crystal driving power source voltage V ₅
4. The outermost row on the right side of the figure shows the electrode 10 of the power supply voltage V _CC for supplying the low power supply section and the electrode 1 of the liquid crystal drive power supply voltage V ₅ .
4. Left and right electrodes 15, 15 of high power supply voltage V _H
The power supply wiring (Al wiring) 36 connected to the belt-like region 33 is adjacent to the band-shaped region 33 and circulates. The power supply wiring 36 supplies power to the driver circuit section 7 which is a high voltage section. One side electrode 15
Can be omitted, but is used when a cascade connection is made to similar chips. Similarly, the power supply wiring 37 connected to the left and right electrodes 11 and 11 of the liquid crystal drive power supply voltage V ₀ circulates adjacent to the outside of the power supply wiring 36 connected in a closed loop (ring connection). This power supply wiring 3
7 supplies power to the driver circuit section 7 which is a high voltage section.
Although the electrode 11 on one side can be omitted, it is used for cascade connection with a similar chip. The power supply wiring 38 connected to the electrodes 12, 12 of the left and right liquid crystal drive power supply voltages V _{2 in} the drawing also circulates adjacent to the outside of the closed-loop connection power supply wiring 37. The power supply wiring 38 also supplies power to the driver circuit section 7 which is a high voltage section. One electrode 12
Is an electrode for cascade connection. LCD drive power supply voltage V
_The power supply line 39 connected to the _third electrodes 13 also circulates outside the power supply line 38 in the closed loop connection. The area where the power supply wiring 38 is laid is near the level shift circuit section 6 of the driver circuit section 7 to supply power to the driver circuit section 7. One electrode 13 is an electrode for cascade connection.
Power wiring 40 connected to the electrodes 14, 14 of the last of the liquid crystal drive power supply voltage V ₅ is also orbiting adjacent the outer power supply wiring 39 of the closed-loop connection. The power supply wiring 40 supplies power to the driver circuit unit 7. One electrode 14 is an electrode for cascade connection. As described above, the power supply voltages V _H , V ₀ , V ₂ , V
₃ power supply wires 36,37,38,39,40 of, V ₅ is 1 cyclic closed loop connected around the output electrodes 8 ₁ to 8 _N of the inner region. Therefore, since these wirings do not cross each other, it is possible to suppress uneven display contrast due to uniform wiring impedance. FIG.
As is apparent from comparison with the wiring arrangement shown as 0, the wiring length of each power supply wiring is reduced. Each power supply wiring is because orbiting adjacent around the band-like region 33 of the center line L ₁ of the chip. In particular, the decrease in the length in the Y direction is remarkable. Therefore, the fluctuation or variation of the power supply voltage of each bit due to the decrease of the wiring resistance can be suppressed.
This also improves the uneven display contrast.

The ground wiring connected to the electrode 19 of the ground voltage GND is branched into three on each of the first block 31 side and the second block side 32, and the ground wiring 41 on the inner side is connected to the driver circuit section 7. In the boundary area between the level shift circuit section 6 and the level shift circuit section 6, the intermediate ground wiring 42 is provided in the boundary area between the level shift circuit section 6 and the latch circuit section 5, and the outer ground wiring 43 is provided in the outer area of the shift register circuit section 3. Has been laid. In each of the first block 31 and the second block 32, an outer power supply line 44 branched from the power supply line 36 of the power supply voltage V _H is laid on the level shift circuit unit 6. Further, a power supply wiring 45 connected to the electrode 10 of the low-voltage power supply V _CC is laid in a boundary area between the latch circuit unit 5 and the shift register circuit unit 3. Although the ground wirings 41, 42, 43, the branched power supply wiring 44, and the normal power supply wiring 45 can be connected in a closed loop, they do not affect the display characteristics. Now, it is in an open loop state.

The low-voltage power supply voltage V _CC and the ground voltage GND are also supplied to the logic controllers 35 and 36. The data signal D _IN , in the central area near the short sides 35a and 35b of the chip
Required input / output signal electrode columns 46 and 47 for the output data D _OUT , clock pulse CP, AC waveform clock M, etc. are formed. Thus, electrodes 8 along the center line L _{1 1} ~
The group of 8 _{N , 10 to} 15 _and 19 and the rows 46 and 47 of input / output signal electrodes orthogonal to both ends of the group have an I shape. The first block 31 on either side of the center line L ₁ as a boundary and the division circuit layout in the second block 32, even because it is equal in both blocks, on both sides to the input and output signal electrodes even boundary center line L ₁ It is desirable to assign to. This is for achieving the symmetry of the layout of these signal wirings and the equality of the wiring length. I-shaped electrode group, as described below, wearing substrate straight chip (COG) is also possible to secure the superiority in the implementation, orthogonal to the input and output signals at both ends of the linear electrode group along the center line L ₁ The presence of the electrode rows 46 and 47 facilitates parallelization of the chip itself during COG mounting. Of course, the paralleling process does not depend only on the input / output signal electrode rows 46 and 47, but the longer the chip length (the length in the X direction), the more significant the significance.

In this embodiment, dummy electrodes (dummy pads) 48a to 48d for positioning and supporting are formed separately at the corners of the chip. In order to increase the number of bits, signal electrodes for driver output are conventionally formed at the corners of the chip as shown in FIG. 10, and it has been problematic to provide dummy electrodes for positioning. in the example driver output signal electrodes are formed on the band-like region 33 of the center line L _1, and since the column of the input and output electrodes are also formed on both ends thereof, the dummy electrode 48a~ the corner
There is a derivative benefit that can secure 48d.

FIG. 2 is a cross-sectional view showing the chip according to this embodiment in a TAB mounting state, and FIG. 3 is a plan view thereof. The chip 30 having the above-described layout configuration shows the state of the stage of the diffused wafer. After that, Au bumps 51 are formed on the respective electrodes (pads), and the wafer with bumps is completed. Be transformed into (Chip process). On the other hand, the tape carrier (film) 52 used in the assembling process has a sprocket hole 52a and a device hole 52b in which a lead pattern corresponding to the electrode arrangement of the chip 30 is formed.
Is formed on a plastic film (for example, a polyimide film) having. The opening area of the device hole 52a is smaller than the plane area of the chip 30, substantially, the output electrode 8 _1-8 formed in the central zone area of the chip 30 _N
Is limited to only the area where the bump 51 is exposed in a plane. The tape carrier 52 has slits 53a and 53b for wrapping around the resin outside the device hole 52a. The tape carrier 52 is a plastic film 54
This is a film with an adhesive (two-layer film) on which an adhesive layer 55 is adhered. A metal foil such as a copper foil is laminated on this film, and a lead pattern as shown in FIG. 3 is formed using a photoresist technique or an etching technique. This lead pattern protrudes into the device hole 52a, and includes a finger lead (inner lead) 56 to be subjected to inner lead bonding with the bump 51,
It has an outer lead 57 to be outer lead bonded to a row or column electrode on the D panel side, and a lead lead portion 58 for integrally connecting the finger lead 56 and the outer lead 57. In addition, film 5
Terminals 58 are formed at the tips of the lead-out lead portions 58 connected to the printed wiring board 2 of FIG.

An assembling process (TAB mounting) of the tape carrier 52 manufactured by such a tape process and the above-described chip 30 with bumps is performed. That is, the chip 30 is fed up with the finger lead 5 while the tape is being fed.
6 and the finger lead 51 and the bump 51 are subjected to inner lead bonding by a bonding tool. Thereafter, the chip 30 is sealed with a molding resin 59 by a potting method. At the time of potting, since the film 52 itself has slits 53a and 53b for wrapping around the resin outside the device hole 52, the entire surface of the chip 30 can be completely sealed.
Of course, by setting the opening area of the device hole 52a to be equal to or larger than the area of the chip 30, the unsealed portion of the resin mold can be eliminated. 53a,
Opening edge portions 60a and 60b with 53b serve as a backing reinforcement portion of the lead. These opening edges 60
a, because 60b is present near the bumps 51 of substantially the chip 30, the cantilever length of the finger leads 56 (projecting length) is Y _1. Opening edge portion 60a, since the cantilever length when 60b is not present is a Y _2, Y ₁ <Y ₂
And the shortened length of the beam length (extended length) is substantially Y ₂ −Y
_Is one. The shorter the length of the finger lead 56 is, the easier the alignment at the time of inner lead bonding is, and the stronger the support force of the chip can be. Further, since the bumps 51 are arranged in a straight line, the alignment property at the time of collective bonding is improved, and the bonding property is not impaired even in a large-sized chip. Since the inner lead group covers almost the entire surface of the chip, damage to the chip surface by the collective bonding tool can be suppressed.
Collective bonding is possible even when the bump pitch is a fine pitch of 100 microns or less. Further, since the amount of bending is reduced by the shortened finger lead 56 and the bump 51 or the electrode (pad) is formed in the central region of the chip 30, the finger lead 56 and the edge of the chip 30 are hardly in contact with each other. And edge short-circuit can be prevented. This can eliminate the danger of contact between the two by the weight of the molding resin 59 particularly by potting. When there is no opening edge portion 60a, 60b, there is no advantage in the ease of alignment between the finger lead 56 and the bump 51, but an insulating layer can be formed on the finger lead 56 near the chip edge. This is because the bump 51 is not formed near the chip edge. Also in such a case, edge short-circuit can be prevented. Further, the heat radiation characteristic is improved by the inner lead group covering the chip surface.

FIG. 4 is a sectional view showing another TAB mounting state of the above-mentioned chip. In this tape carrier 60, the inner leads 61 protruding into the device holes 52b have a doubly supported structure with respect to the film. Since the bumps 51 are present in the central region (inner region) of the chip 30, there is no necessity for the inner lead to have a cantilever structure. According to this doubly supported or double suspended structure, FIG.
As compared with the cantilever structure shown in FIG. 1, the accuracy of alignment with the bumps 51 is further improved, and the support force is doubled. Of course,
The problem of chip edge short does not occur. Furthermore, damage prevention on the chip surface can be ensured, and the heat radiation characteristics are also excellent.

FIG. 5A is a plan view showing a state in which COG mounting is performed on the frame region 62 of the liquid crystal panel. The lead-out lead portion 58 among the leads of the liquid crystal panel overlaps the plane of the chip 30. By the way, in general, it is meaningful that the lead-out lead portion 58 starts from the pitch of the bumps 51 and gradually adjusts to a longer pixel row or column interval. As the pitch of the bumps 51 becomes finer, the length of the lead-out lead portion 58 needs to be increased. This is because the tighter the degree of bending, the smaller the distance between the leads than the bump pitch, and the easier it is to short-circuit.
Therefore, under multi-bit or finer electrode pitch as in LCD driving ICs, it is necessary to suppress the degree of bending of the leads, and the lead 58 must be inevitably lengthened. Such an increase in the length of the lead-out lead portion 58 results in an increase in the width dimension (extended length) of the frame region of the glass substrates G ₁ and G ₂ . However,
In this embodiment, as shown in FIG. 3, not all of the lead-out lead portions 58 are on the tape carrier 52, but a part 58a of the lead-out lead portion 58 is
0 overlaps. This is because the bumps 51 are formed in the central region of the chip 30, so that a part 58a of the lead-out lead portion 58 can be formed between the bumps 51 and the long sides 31a, 32a of the chip 30. The length of the overlap portion 58a is substantially equal to the shorter length Y ₂ -Y ₁ of the inner leads 56 described above. Therefore, according to the schematic evaluation, FIG. 5 (B), the its width W ₁ of the present embodiment as compared to the width W of the conventional frame region ₂ (Y 2 -Y ₁₎ Only small. The reduction in the width of the frame region 62 means a reduction in the non-display area or an increase in the length of the non-display area, which contributes to a reduction in the size of the liquid crystal display device as a mounted product of the LCD panel and an improvement in the external appearance (design). In other words, it is possible to further increase the number of bits or to make the chip thinner without increasing the width of the frame region 62.

[0022]

FIG. 6 is a chip layout diagram of a semiconductor device according to a second embodiment of the present invention.

This semiconductor chip 70 is also an LCD drive type IC.
In order to reduce the width of the frame area during COG mounting
In a rectangular or elongated shape. This chip 70
The embedded integrated circuit is the same as in the first embodiment.
The n-bit shift register circuit section 3
Switch circuit 5, level shift circuit 6, and driver circuit
A part 7 is provided. And only one block of circuit cells
Each bit of the ray has its own output (driver output) Y
₁ ~ Y_n Rectangular output electrode (pad) 8₁ ~ 8 _n Is Dora
Each stage 7 of the iva circuit section 7₁ ~ 7_n Formed in the shortest adjacent area
Have been. The n-bit shift register circuit section 3 has a long side 7
1a, the driver circuit section 7
Are built in the chip inner area. And the output electrode
(Pad) 8 is formed in a line in the X direction.

FIG. 6 shows the outside of both ends of the cell array forming region.
Control logic units 72 and 73
Is built in. The center of the peripheral area of the long side 71b
The control logic part 74 indicated by the dashed line is also built in the part
Have been. Data in the X direction inside the control logic 74
Signal D_IN, Output data D_OUT , Clock pulse CP, exchange
A required input / output signal electrode array 75 for the waveform shaping clock M, etc.
Are formed, and this row is adjacent to and parallel to the row of the output electrodes 8.
You. On both outer sides of the row 75, rectangular power supply electrodes 11 to 14 are provided.
The rectangular ground electrode 19 or the low-voltage power electrode 10 is formed
I have. The electrodes 1 of the high-voltage power supply are located on both outer sides of the row of the output electrodes 8.
5 are formed. Therefore, the electrode group on the chip is two rows
Are arranged in the X direction. Left and right high power supply voltage V_H of
The power supply wiring 76 connected to the electrodes 15 and 15 is
Close. This power supply wiring 36 is a dry
The power is supplied to the power circuit 7. The electrode 15 on one side is omitted.
Can be cascaded to similar chips.
Used when continuing. Similarly, the left and right liquid crystal shown
Drive power supply voltage V₀ Power supply wiring connected to the electrodes 11, 11
77 is adjacent to the long side 71a side of the power supply wiring 36. This
The power supply wiring 77 is connected to the driver circuit section 7 which is a high voltage section.
Power. The electrode 11 on one side can be omitted
Is cascaded to similar chips.
Used. Left and right liquid crystal drive power supply voltage V_Two Electrode 1
The power supply wiring 78 connected to 2 and 12 also has the long side of the power supply wiring 77.
71a side. This power supply wiring 78 is also in the high voltage section.
Power is supplied to the driver circuit section 7. One electrode 1
Reference numeral 2 denotes a cascade connection electrode. LCD drive power supply voltage
V_Three The power supply wiring 79 connected to the electrodes 13 and 13 is also provided with a power supply.
The line 78 extends to the long side 71a side. This power supply wiring 7
The installation area of 8 is the level shift circuit section of the driver circuit section 7
At a position closer to 6, power is supplied to the driver circuit unit 7. Another piece
One electrode 13 is an electrode for cascade connection. last
LCD drive power supply voltage V _Five To the electrodes 14 and 14
The source wiring 80 is also adjacent to the long side 71a of the power wiring 79.
You. The power supply line 70 supplies power to the driver circuit section 7
I do. One electrode 14 is an electrode for cascade connection.
It is. Thus, power should be supplied to the driver circuit section 7.
Power supply voltage V_H , V₀ , V_Two , V_Three , V_Five Power supply wiring 7
6,77,78,79,80 are parallel on that area
You. These wires are connected in a closed loop around the row of electrodes 8.
Power supply voltage V_HThe electrode 15 of the row of the electrode 8
The power supply voltage V₀ , V_Two , V_Three these
The wiring is not a closed loop connection that goes around the column of the electrode 8 once.
Is the power supply voltage V_H, V_FiveElectrodes 11, 12, 13, 14
Two rows are formed with several electrodes on both ends of the row of the electrodes 8. ground
The ground wiring connected to the electrode 19 of the voltage GND is divided into three.
The ground wiring 81 on the inside is divided into the driver circuit section
In the boundary area between the level shifter 7 and the level shift circuit 6, an intermediate ground
The wiring 82 is connected between the level shift circuit 6 and the latch 5.
In the boundary area, the outer ground wiring 83 is a shift register circuit.
Each of them is laid in an area outside the part 3. Power supply voltage V
_H The outer power supply wiring 84 branched from the power supply wiring 36 of FIG.
It is laid on the level shift circuit section 6. Furthermore, low electricity
Voltage power supply V_CCThe power supply wiring 85 connected to the electrode 10 is a latch.
Laid in the boundary area between the circuit section 5 and the shift register section 3
I have. And the middle of the row of electrodes 11, 12, 13, 14
A row 75 of input / output signal electrodes is interposed in the region.

As described above, according to the layout in which the power supply wiring is routed around both ends of the column of the electrodes 8, the wiring length of the power supply wiring or the signal wiring can be suppressed as compared with the conventional method.
The present example provides a suitable layout of electrodes and wirings corresponding to a thinner chip. 73a and 73b are long sides 7
A dummy electrode (pad) for positioning and assisting is formed at a corner portion on the side of 1a.

FIG. 7 shows the TAB of the chip according to the above embodiment.
It is a top view showing a mounting state. In this figure, the same parts as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. The tape carrier (film) 92 for the chip 70 having the above-described layout configuration has a lead pattern corresponding to the electrode arrangement of the chip 70 having a sprocket hole 52a.
And a plastic film having device holes 92b. The tape carrier 92 has slits 93a and 93b for winding around the resin having different opening areas. The lead pattern protrudes into the device hole 92a, and includes a finger lead (inner lead) 56 to be subjected to inner lead bonding with the bump 51,
It has an outer lead 57 to be outer lead bonded to a row or column electrode on the D panel side, and a lead lead portion 88 for integrally connecting the finger lead 56 and the outer lead 57. In addition, film 5
A terminal 58 is formed at the tip of a lead-out lead portion 88 connected to the printed wiring board 2 of FIG. TAB mounting of the tape carrier 92 manufactured by such a tape process and the above-described bumped chip 70 is performed in the same manner as in the first embodiment. Cantilever length of the finger leads 56 (projecting length) is Y _1. Since the cantilever length of the case where the opening edge portion 70b of the LCD panel side is not present is Y _3, Y ₁
<In Y _3, shortening the length of the beam length (overhang length) substantially Y
It is a ₃ -Y _1. This shortened length is equal to Y ₂ −Y _{1 of the} first embodiment.
Is greater.

FIG. 8A is a plan view showing a state in which the chip is mounted on the frame area 102 of the liquid crystal panel by COG after TAB mounting. In the figure, the same parts as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. Also in this mounting, a part 88 a of the lead-out lead portion 88 overlaps the chip 30. This is because the bump 51 is formed apart from the long side 71a of the chip 70. This overlap portion 88a
Is the shortened length Y ₃ − of the inner lead 56 described above.
Y ₁ is substantially equal. Example 1 The width dimension of the chip 70 is
Considering that it can be made smaller than that of FIG.
As shown in (B), the width dimension W of the frame region 102 in this example is shown.
₂ can be made smaller than the width dimension W1 of the _first embodiment.

[0028]

As described above, the semiconductor device provided with the circuit cell array according to the present invention is not limited to the LCD driver IC, but may be a display driver IC, a printer driver IC, a sensor interface IC, a gate array, or the like. It can be widely applied to an IC having an array structure in which a circuit cell and its electrode are paired or a multi-output or multi-input multi-bit IC, and is suitable for saving the width of a mounting area in a data input or output device. ing.

[Brief description of the drawings]

FIG. 1 is a layout diagram illustrating a chip of a liquid crystal driving semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a state in which the chip according to the first embodiment is mounted on a TAB.

FIG. 3 is a plan view illustrating a state in which the chip according to the first embodiment is mounted on a TAB;

FIG. 4 is a sectional view showing a TAB mounting state different from the TAB mounting.

FIG. 5A is a plan view showing a state where the chip according to the first embodiment is COG-mounted in a frame region of a liquid crystal panel, and FIG.
FIG. 3 is a cross-sectional view showing a frame region side in the same state.

FIG. 6 is a layout diagram illustrating a chip of a liquid crystal driving semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a plan view illustrating a state in which the chip according to the second embodiment is mounted on a TAB;

FIG. 8A is a plan view showing a state where the chip according to the second embodiment is COG-mounted in a frame region of a liquid crystal panel, and FIG.
FIG. 3 is a cross-sectional view showing a frame region side in the same state.

FIG. 9 is a block diagram showing a general circuit configuration of a liquid crystal driving semiconductor device.

FIG. 10 is a layout diagram showing a chip of a conventional liquid crystal driving semiconductor device.

FIG. 11 is a plan view showing a state where the chip is mounted on a frame area of a liquid crystal panel by COG.

[EXPLANATION OF SYMBOLS] 3: shift register circuit portion 5 ... latch circuit portions 6 the level shift circuit 7 ... driver circuit portion 7 _N ... each stage 8 _N ... output electrode of the driver circuit portion (pad) 10 to 15 ... power electrode 19 Ground electrode 30, 70 Semiconductor chip 31 First block 32 Second block 31a, 32a, 71a, 71b Long side of chip 33 X-band (center area) 34, 35, 72 73, 74: Control logic part 35a, 35b: Short side of chip 36, 37, 38, 39, 40, 44, 45 ... Power supply wiring (Al wiring) 41, 42, 43 ... Grounding wiring 46, 47, 75 ... Array of output signal electrodes 48a to 48d, 73a, 73b ... Dummy electrodes (dummy pads) 51 ... Bumps 52, 60, 92 ... Tape carrier (film) 52a ... Sprocket holes 2b, 92b: Device hole 53a, 53b, 93a, 93b: Slit 54: Plastic film 55: Adhesive layer 56, 61: Finger lead (inner lead) 57: Outer lead 58, 88: Lead-out lead 59: Molding resin 60a , 60b ... frame region 76,77,78,79,80,84,85 ... power supply wiring of the opening edge portion 62 ... liquid crystal panel 81, 82, 83 ... ground line L _1, L ₂ ... center line Y _N ... driver output Y _1, Y ₂ ... cantilever length of the finger leads (overhang _{length) V H, V CC, V} 0, V 3, V 2, V 5 ... power supply voltage

Claims (7)

(57) [Claims] 1. A and the substrate on which a wiring pattern is formed, rectangular
Half having a plane of shape and having electrodes for external connection on said plane
A conductor chip, outside the substrate and the semiconductor chip.
The mounting of the semiconductor chip to be mounted by opposed the forming surface parts connecting electrodes, said external connection electrode and the first long side of the semiconductor chip
The wiring pattern roughly arranged along the virtual center line between the second long side and the wiring pattern connected to the external connection electrode.
That is, at least a part of the wiring pattern extending to the long side
The implementation of the semiconductor chip, characterized in that the bent portion at a site located in the tip and the phase overlap region in the wiring pattern is formed. 2. The semiconductor chip package according to claim 1, wherein said substrate is a glass substrate. 3. The semiconductor chip package according to claim 1, wherein the chip is a multi-bit drive type IC. 4. The chip is a display driver IC.
The semiconductor chip package according to claim 1, wherein: 5. The semiconductor chip package according to claim 1, wherein the chip is a printer driver IC. 6. The semiconductor chip package according to claim 1, wherein the chip is a multi-input / output type IC. 7. A display comprising a semiconductor chip mounted body according to claim 4, wherein said substrate is a liquid crystal display panel.