JP3234490B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, to a liquid crystal display (LCD).
Thin film transistor (TFT)
nsistor).

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a TFT as a switching element can perform static driving with a duty ratio of 100% in principle in a multiplex manner, and is used for a large-screen, high-definition moving image display.

An active matrix LCD has a substrate in which TFTs are connected to display electrodes arranged in a matrix (TFF substrate) and a substrate having a common electrode (counter substrate).
Are bonded together with a liquid crystal interposed therebetween. The opposing portion between the display electrode and the common electrode is a pixel capacitance using a liquid crystal as a dielectric layer, and is selected line by line by a TFT and a voltage is applied. The voltage applied to the pixel capacitance is O
The data is held for one field period by the FF resistor. The liquid crystal has electro-optical anisotropy, and the amount of transmitted light is finely adjusted according to the intensity of the electric field formed by the pixel capacitance. In this way, the distribution of light and dark whose transmittance is controlled for each pixel is visually recognized as a desired display image.

In recent years, by using polycrystalline (poly) silicon (p-Si) as a channel layer of a TFT,
An LCD integrated with a driving circuit in which a matrix pixel portion and a peripheral driving circuit portion are formed on the same substrate has been developed. Generally, p-Si has a higher mobility than amorphous silicon (a-Si). Therefore, the size of the TFT is reduced, and high definition is realized. Further, since high-speed operation is achieved by miniaturization by the gate self-aligned structure and reduction of parasitic capacitance, a high-speed driving circuit is formed by forming an electrically complementary connection structure of n-ch TFT and p-ch TFT, that is, CMOS. be able to. As described above, by integrally forming the driving circuit portion and the matrix pixel portion on the same substrate, reduction in manufacturing cost and downsizing of the LCD module can be realized. FIG. 16 shows such an LCD integrated with a driving circuit.
Is shown. A portion surrounded by a dotted line in the center is a matrix pixel portion, which includes a gate line (G1, G2,..., Gm) for controlling ON / OFF of a TFT and a drain line (D1, D2,...) For pixel signals. Dn) are arranged crossing each other. At each intersection, a TFT and a display electrode (not shown) connected to the TFT are formed. A gate driver (GD) for selecting a gate line (G1, G2,..., Gm) is disposed on the left and right of the pixel unit. ), The drain lines (D1, D1)
, Dn), a drain driver (DD) for applying a pixel signal voltage is arranged. The drain driver (DD) mainly includes a shift register circuit and a sampling circuit, and in some cases, a hold capacitor, and the gate driver (GD) mainly includes a shift register. Outside these gate driver (GD) and drain driver (DD), supply pads for external input signals such as a clock signal, a start pulse, a video signal, and a power supply voltage are formed.

FIG. 17 shows the structure of such a p-Si TFT. An island-patterned p-Si (101) is formed on a transparent insulating substrate (100) such as glass, and a gate electrode (103) faces the gate insulating film (102) such as SiO2. Are located. The gate electrode (103) is made of, for example, a polycide layer of doped poly-Si and silicide.

The p-Si (101) has a self-aligned structure using the gate electrode (103) as a mask, and has an n-type heavily doped source / drain region (1).
01S, 101D) and a non-doped or p-type doped channel region (101N) immediately below the gate electrode (103), and between the channel region (101N) and the source and drain regions (101S, 101D). Is an n-type lightly doped LD region (101)
L) is formed.

In the pixel portion, the gate electrode (103) is formed integrally with the gate line as a scanning line, and in the drive circuit portion, it is connected to a connection having a complementary structure. On the gate electrode (103), an injection stopper (105) for preventing counter doping during the process, and a gate electrode (10).
3) and sidewalls (104) necessary for self-alignment are formed on the side walls of the injection stopper (105). The p-Si (101) and the gate electrode (1
03) and the first surface such as SiO2
And a drain electrode (107) and a source electrode (10) made of a refractory metal such as Ti / AlSi on the first interlayer insulating film (106).
8) are provided and connected to the drain / source regions (101D, 101S) via contact holes (CT4, CT5) opened in the gate insulating film (102) and the first interlayer insulating film (106), respectively. ing. In the pixel portion, the drain electrode (107) is integrated with the drain line which is a signal line, and in the drive circuit portion, the drain electrode (107) and the source electrode (108) are connected in a complementary structure. Has been extended. These drain electrodes (10
7) and the entire surface covering the source electrode (108)
A second interlayer insulating film (109) having a flattening action such as (Spin On Glass) is formed. In the pixel section,
ITO (indium tin oxide) is formed on the second interlayer insulating film (109).
xide) is formed, and the source electrode (10
8) A contact hole is formed in the upper second interlayer insulating film (109) to connect to the source electrode (108).

As shown here, the drain region (10
1S) and the channel region (101N), and between the source region (101S) and the channel region (101N) with the low concentration LD region (101L) interposed therebetween.
Generally called LDD (lightlydoped drain), the strong electric field at the end of the channel region (101N) is reduced, so that the acceleration of carriers is suppressed and the withstand voltage is high. Since the LD region (101L) is also interposed as a resistor, the transconductance is reduced.
In the pixel portion, the OFF current can be suppressed, and the voltage holding ratio can be increased. On the other hand, since a sufficiently high ON current value is originally obtained with a p-Si TFT, an ON / OFF ratio can be improved by adopting an LDD structure.

Such a TFT having the LDD structure is manufactured as follows. First, a glass substrate (10
0) on the amorphous silicon (a) by CVD using silane SiH4 or disilane Si2H6 as a material gas.
-Si), and the a-Si is heated to 200 to 4
Polysilicon (p-Si) (101) that has been polycrystallized by excimer laser annealing or lamp annealing at 00 ° C., preferably 400 ° C., is etched by reactive ion etching, ie, RIE (reactive ion etch). As a result, an island layer serving as an active layer of the TFT portion is formed.

A process including a high-temperature treatment step of 900 ° C. or more using a high heat-resistant quartz glass or the like as the substrate (100) is generally called a high-temperature process. Law (SP
C: Solid phase crystallization). Alternatively, the film may be directly formed by high-temperature CVD.

If necessary, the n-ch TFT region of the driving portion is p-type channel-doped by implanting boron or the like, and then SiO2 is formed thereon by CVD to form a gate insulating film (102). Then, a-Si is laminated by CVD at 580 ° C. using SiH 4 as a material gas, and this is polycrystallized by excimer laser annealing (po).
ly-Si) and n-type doping by ion implantation of phosphorus to reduce the resistance, and then tungsten silicide (WSi)
Is sputtered, and SiO2 serving as an injection stopper (104) is formed by CVD. These SiO2 and po
The polycide layer of ly-Si and WSi is etched in the same pattern by RIE to form a gate electrode (103), a gate line connecting these to each other in a row in a pixel portion, and a connection in a drive circuit portion.

In the high temperature process, poly-Si is 6
It may be directly laminated by CVD at 00 to 650 ° C,
Further, the resistance may be reduced by a diffusion treatment using phosphoryl trichloride POCl3. Gate electrode (1
03) as a mask, 1 × 10 11-5 × 10 13 cm
-2 (where ↑ represents a power, 5 × 10 {13 cm})
-2 means 5 × (10 13) per square centimeter. ) Is implanted at a low dose, and the source and drain regions (101S, 101D) and the LD region (1) are implanted.
01L) at a low concentration. Subsequently, after a masking resist larger than the gate electrode (103) is formed, ion implantation of phosphorus is performed again at 1 × 10〜14 to 1 × 10 ↑ 16.
High concentration doping is performed at a high dose of cm @ -2, preferably 7 * 10 @ 14 to form a source region (101S) and a drain region (101D). This completes the LDD structure in which the low concentration LD region (101L) is interposed between the source and drain regions (101S, 101D) and the channel region (101N). p
Similarly, in the −ch TFT, the source and drain regions are doped p-type by boron ion implantation using a self-alignment technique.

By lamp annealing, the doped regions (101S, 101D, 101L,
After the impurity activation of 3), a first interlayer insulating film (106) is formed by depositing SiO2 to a thickness of 3000 to 5000 ° by CVD and annealing.
Then, after performing H2 annealing for the purpose of terminating dangling bonds in silicon, the gate insulating film (102) and the first interlayer insulating film (106) on the drain and source regions (101D, 101S) are subjected to RIE. Then, contact holes (CT4, CT5) are formed.

In the high temperature process, the first interlayer insulating film (1
06) is BPSG, that is, SiO2 containing boron and phosphorus.
A film may be formed by CVD and reflowed at 900 ° C. And sputtering Ti / AlSi,
This is patterned by RIE to form a drain electrode (107) and a source electrode (108), and a drain line connecting the drain electrode (107) for one row in a pixel portion, and a complementary connection and a lead line of a drive circuit portion. And so on. The drain electrode (107) and the source electrode (108) are respectively formed in contact holes (CT4, C4).
T5) through the drain and source regions (101D, 1
01S).

Again, after performing H plasma treatment for terminating dangling bonds in silicon, an SOG film, that is, a planarization insulating film mainly composed of a SiO 2 film formed by spin coating and firing is laminated. Second interlayer insulating film (109)
Is formed. Then, by RIE, in the second interlayer insulating film (109) on the source electrode (108) of the pixel portion,
A contact hole is formed, ITO is formed by sputtering, and this is patterned by RIE to form a display electrode in a pixel portion, and a source electrode (10
8).

In the above steps, p-Si (10
The ion implantation for forming the LDD structure of 1) and reducing the resistance of the gate electrode 103 is performed as follows. First, FIG. 18 is a schematic diagram of an ion implantation apparatus. (50) is an ion source, (51) is an extraction and acceleration system, (52) is a mass analysis system, (53) is an acceleration system,
(54) is a vertical scanning system, (55) is a horizontal scanning system,
(56) is a target system. The ion source (50)
An anode and a cathode are provided in a discharge tube provided with a gas inlet, and a plasma discharge is generated. For example, when performing phosphorus ion implantation, a source gas such as phosphine PH3 or phosphorus pentafluoride PF5 is introduced, and when performing boron ion implantation, a source gas such as boron trifluoride BF3 or diborane B2H6 is introduced. I do. This is ionized by discharge plasma, and P +, H +, H2 + or B +, F +, BF +,
Generates ions such as BF2 +. These generated ions are further extracted to the outside as a beam current by an extraction electrode arranged at the exit of the extraction system (51), and accelerated as necessary to become an ion beam. This ion beam enters the mass spectrometry system (52), where only necessary ions pass. The mass spectrometry system (52) passes an ion beam through a fan-shaped uniform magnetic field, and utilizes the fact that the orbital radius of ions moving in the magnetic field varies depending on the mass, and passes only ions of a specific mass, that is, ions of a specific element. It is. In particular, by providing a slit at the outlet, unnecessary ions are completely removed, and the analysis effect is further enhanced. The ion beam analyzed in this manner is accelerated by an acceleration system (53) comprising a single or multi-stage acceleration tube, and a desired implantation energy is applied. The ion beam is further passed through a vertical and horizontal scanning system (54, 55) comprising a pair of deflection electrodes, and a target system (56).
Is irradiated. In the target system (56), various measures are taken to facilitate the attachment / detachment / conveyance of the stage, which supports the target, that is, the predetermined electrode substrate, and the electrode substrate. In particular,
The stage is configured to be movable in the XY directions, and the scanning system (5
4, 55) can be considered to reduce the load on the apparatus.

Such an ion implantation method is particularly called an ion implantation method because only a specific ion to be doped is accelerated and implanted directly into a control layer. Also, the doped region (101S,
In particular, RTA (Rapid Thing) is used as lamp annealing for activating impurities of 101D, 101L, and 103) and silicidizing the gate electrode (103) including a silicide layer.
There is a method of performing high-temperature processing without damaging the substrate by performing high-speed scanning with a heat source close to the substrate, that is, the thermal annealing method.

FIG. 19 is a schematic diagram of an RTA apparatus. (6
0) is a substrate on which a film to be processed is formed, (61) is a xenon arc lamp as a heat source, (62) is a reflecting mirror for reflecting heat, (63) is a roller for transporting the substrate, and (64) is a pre-heating roller. The heater (65) is a post heater. The substrate (60) is preheated (6) by a roller (63).
4), is preheated, and is sent to a linear heating area composed of a xenon arc lamp (61) and a reflecting mirror (62) arranged so as to enclose the xenon arc lamp (61). The moving speed of the substrate (60) is controlled by the number of rotations of the roller (63). The substrate (60) is kept warm by the post-heater (65), so that rapid cooling is avoided. In this method, the scanning speed of the substrate (60) is adjusted arbitrarily (で は 30 mm / sec in the prototype).
c) The heating temperature can be controlled by adjusting the lamp power and the scanning speed. Therefore, heating time 1
In a short time of about seconds to several seconds, the substrate temperature is set in a temperature range of about 600 to 900 ° C., so that heat energy is particularly absorbed by the amorphous layer and the silicide, and heating is completed before the substrate is bent. By adjusting the temperature, high-temperature processing can be performed without deteriorating the substrate.

[0019]

In the ion implantation method described above, the controllability is extremely high as compared with the thermal diffusion method and the like, and the ion range is controlled by adjusting the amount of source gas, extraction voltage, and acceleration voltage. The distance is controlled, and the doping amount and the doping depth can be finely adjusted. In particular, the lateral diffusion length of the implanted impurity is small, and the doping region can be accurately defined by the mask pattern. Therefore, by adopting the gate self-aligned structure using the self-alignment technique as described above, the stability and high speed of the transistor can be achieved.

However, on the other hand, there are the following disadvantages. First, as a defect in characteristics, a large amount of lattice defects may occur during ion implantation. Although such lattice defects depend on implantation conditions, for example, implantation of boron B causes 100 to 1000 lattice defects per ion. In particular,
When implanting into a polysilicon film, an amorphous layer, that is, an amorphous silicon layer is formed near the surface, and the sheet resistance increases. Such lattice defects are recovered and recrystallized by annealing, but in a so-called low-temperature process of forming a TFT on an inexpensive glass substrate having a low heat-resistant temperature by setting the entire heat treatment step to 600 ° C. or lower,
Such recovery of crystallinity may not be sufficiently performed, and may adversely affect characteristics.

When the above-described RTA method is used for annealing for such recrystallization, a polycide film (WSi: 1000 ° /) used for a gate electrode and its wiring is used.
FIG. 20 shows the dependence of sheet resistance on lamp power for poly-Si: 2000 °). In the figure, the sheet resistance value of polycide when the scanning speed is 12 mm / sec is represented by △. In the drawing, the film temperature to be processed measured by a pyrometer for calculating the film temperature from the optical observation of the lattice state is entered. As shown in the figure, a sheet resistance of 2.5 kΩ / □ or less is obtained at a lamp power of 19 kW or more, and a sufficiently low value is obtained for the gate electrode wiring.

FIG. 21 similarly shows the dependence of the sheet resistance on the lamp power of the doped polysilicon film used for the source and drain regions. A p-type polysilicon film (dose amount: 1.5 × 10 15 cm 2), an n-type polysilicon with a dose amount of 3.0 × 10 15 cm 2, a dose of 7.0 × 10 14 cm 2 − 2 n
The type polysilicon film is represented by ○. The figure shows that the p-type polysilicon film has a relatively low value irrespective of the dose, and that the sheet resistance is constant at about 1.4 kΩ / □ when the lamp power is 19 kW or more. On the other hand, in the case of the n-type polysilicon film, the dose amount is 3.0 × 10
In the case of {15 cm} -2, the sheet resistance is extremely high when the lamp power is 19 kW or less, drops sharply when the lamp power exceeds 19 kW, and has a low value of 1.4 kΩ / □ when the power is 21 kW or more. Further, the dose amount is 7.0 × 10 °.
In case of 14cm３-2, 3k with lamp power over 18kW
It is constant at a slightly higher value of about Ω / □.

From this, it can be seen that, in the ion implantation of phosphorus, the sheet resistance greatly depends on the dose, and changes greatly depending on the annealing temperature. That is, despite the large dose, if the annealing temperature is low,
It can be seen that the resistance is higher than when the dose is small, and conversely, the higher the annealing temperature, the lower the sheet resistance when the dose is large than when the dose is small. This is presumed to be due to the fact that a large amount of implantation damage is caused by phosphorus ion implantation, an amorphous layer is generated, and phosphorus atoms have an effect of preventing recrystallization of silicon.

FIG. 22 shows the relationship between the film temperature required for recrystallization of the polysilicon film and the scanning speed. The marks in the figure are the same as those in FIG. The dotted line shows the case where the non-doped amorphous silicon layer is recrystallized without warping the substrate. From this, the allowable range of the temperature of the film to be processed and the scanning speed in terms of recrystallization and protection of the substrate are ○.
It can be seen that it is in the area between the marked curve and the dotted line. That is,
If the temperature exceeds the dotted line in setting the temperature of the film to be processed and the scanning speed, the substrate may be curved. From this figure, when recrystallizing an n-type polysilicon film having a dose amount of 3.0 × 10 15 cm 2, it exceeds this dotted line.
It turns out that it is not suitable for a low temperature process. Also,
In the case of 7.0 × 10 {14 cm} −2, it is below this dotted line and is applied to a low-temperature process. However, when the scanning speed is increased, the dotted line is approached, and when the scanning speed exceeds 10 mm / sec, the dotted line becomes smaller. This raises a problem in terms of the heat resistance of the substrate. Therefore, it becomes difficult to increase the scanning speed to increase the throughput. On the other hand, the p-type polysilicon film is far below the dotted line, and it can be seen that sufficient recrystallization is performed even at a low temperature and a high scanning speed.

As described above, in the ion implantation method, when the implantation dose is increased, the energy required for recovering crystal defects increases, which hinders the adaptation to a low-temperature process.
Alternatively, there is a problem that it is difficult to improve the throughput by increasing the scanning speed. There is another factor that reduces the throughput due to the principle. That is, since the impurity is uniformly implanted on the substrate by scanning with the focused ion beam, it is usually necessary to reach a predetermined implantation amount for one substrate due to limitations on the spot diameter, beam current, and the like. It takes a few minutes to tens of minutes,
The throughput is as low as 40 wafers / day, and furthermore, it gets worse as the substrate area increases. Further, in terms of the apparatus, the mass spectrometer is large-scale, and the inner wall surface is damaged by unnecessary ions.

[0026]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a low impurity concentration is obtained by implanting a first impurity having a predetermined conductivity type into a predetermined region of a semiconductor layer at a low dose. A first step of forming a region, and implanting a second impurity having the same conductivity type as the first impurity at a high dose except for a part of the low-concentration region. A method for manufacturing a semiconductor device, comprising: a second step of forming a high-concentration region in contact with a part; and a third step of performing heat treatment for activating impurities in the low-concentration region and the high-concentration region. In the first step, ions are extracted from a raw material containing the first impurity element by discharge and a high electric field, ions of the first impurity are extracted from these ions by mass spectrometry, and ions of the first impurity are extracted. To the semiconductor layer The second step is a step of extracting ions from a raw material containing a second impurity element by discharge and an electric field, and injecting all of these ions into the semiconductor layer; The step is a step of scanning at a predetermined speed by bringing the heat source close to the heat source.

Thus, the ion implantation of the first impurity with a low dose is performed by using the ion implantation method for performing mass spectrometry, whereby the controllability of the low concentration doping region is improved and the second impurity with a high dose is implanted. For ion implantation of impurities,
By not performing mass spectrometry, a large amount of ions can be implanted at a time, thereby increasing the throughput. In addition, the absence of mass spectrometry reduces the amount of amorphized regions due to implantation damage, so that the heat treatment temperature for recrystallization can be reduced, and the heat treatment time is shortened by increasing the scanning speed of the heat source. Thus, the throughput can be increased.

The raw material containing the second impurity element is a mixed gas of a hydrogen compound of the second impurity element and hydrogen. As a result, hydrogen implanted together with the second impurity functions to promote recrystallization, so that lattice defects due to implantation damage are recovered in advance, so that the heat treatment temperature for recrystallization can be lowered. The heat treatment time can be shortened.

Particularly, the predetermined speed is 10 mm /
sec or more, preferably 12 mm / sec or more. As a result, the processing time for one substrate is reduced from several seconds to several tens of seconds, and the throughput is increased. The ion implantation dose of the second impurity is 1 × 10 14 or more, preferably 7 × 10 14 or more.

As a result, high throughput and high concentration doping can be achieved while maintaining the heat resistance of the substrate. In particular, the implantation dose of the second impurity ions is 3 × 1.
The configuration is such that 0 ↑ 15 or more. Thereby, high throughput and formation of a further heavily doped region are realized while maintaining the heat resistance of the substrate.

In particular, the heating temperature in the third step is 600
° C or higher, preferably 780 ° C or higher. Thereby, sufficient recrystallization of the amorphous layer by the high-temperature treatment and high throughput at a higher scanning speed can be achieved.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an ion implantation method used in a method of manufacturing a semiconductor device according to the present invention will be described. In this method, unlike the ion implantation method described in the conventional example, the ion implantation is performed once in a large area without performing mass analysis, and is also called an ion shower.

FIG. 1 is a schematic view of an ion implantation apparatus for performing such an ion shower. (1) a plasma source as an ion source, (2) a gas inlet, (3) an RF high-frequency power supply, (4) an extraction electrode, (5) an acceleration electrode,
(6) is a suppression electrode, (7) is a ground electrode, and (8) is a stage for supporting an electrode substrate into which ions are to be implanted. The source gas is introduced from the gas inlet (2) to the plasma source (1). As a source gas, phosphine PH3 diluted with hydrogen is used for n-type doping, and B2H6 diluted with hydrogen is used for p-type doping. These source gases are 1
Ionized by a 3.56 MHz high frequency discharge,
+, H +, H2 +, B +, etc. These ions are extracted from the extraction electrode (4) and reach the acceleration electrode (5) by the extraction voltage. Furthermore, it is accelerated by the accelerating voltage to the suppression electrode (6) and the ground electrode (7), extracted as an ion beam, and irradiated to the target on the stage (8). Each electrode (4, 5, 6, 7) has thousands of fine holes through which ions pass, and a uniform ion beam is obtained by superimposing the ion beams extracted from these holes. Can be Further, the voltage of the suppression electrode (6) is set lower than the voltage of the ground electrode (7) so that a highly uniform ion beam can be obtained.

Such an ion shower method or an ion shower apparatus has the following advantages. First, since the ion beam is obtained as a large current of the same size as the plasma source, the beam diameter can be increased to 500 mm or more, and the uniformity of the beam current can be improved by optimally setting the acceleration voltage and the extraction voltage. It can be suppressed to ± 10% or less. For this reason, up to 500 mm x 500 mm
Substrates can be processed at one time, scanning with a beam line is not required, the time required for processing one substrate is reduced to 1 to 2 minutes, and the throughput is greatly increased as compared with the ion implantation method.

Further, since the method is such that phosphorus ions or boron ions are implanted together with hydrogen ions without performing mass spectrometry, the implantation is performed while compensating for implantation damage.
Therefore, at the time of implantation into the polysilicon film, the doping is performed while recrystallizing the amorphous layer formed on the surface, so that the activation annealing temperature can be lowered or becomes unnecessary.

Further, since the mass spectrometry system and the scanning system are not required, the apparatus is simplified, the size can be easily increased, and the area and the throughput can be increased. On the other hand, the ion shower method has a drawback that injection controllability at a low dose is low. For this reason, in the method of manufacturing a semiconductor device of the present invention, doping with a low dose is performed with high accuracy by the conventional ion implantation method, and doping with a high dose is performed with high throughput by the ion shower method.

FIG. 2 shows the relationship between the dose and the sheet resistance in a low dose range in the ion implantation into the polysilicon film. ◆ is the sheet resistance value at ion implantation, and Δ is the sheet resistance value at ion shower. As can be seen from the figure, the sheet resistance is very stable in the ion implantation, while the variation is somewhat noticeable in the ion shower. That is, in low dose ion implantation,
It can be seen that ion implantation of impurities is performed accurately and uniformly in ion implantation, but controllability is somewhat poor in ion showering.

FIG. 3 shows a TFT having an LDD structure.
Regarding the presence or absence of the LD region, transfer characteristics, that is, gate voltage (V)
-Shows a difference in drain current (Id) characteristics. The solid line in the figure is the characteristic curve of the TFT having the LD region, and the broken line is the characteristic curve of the TFT without the LD region. The drain current value I
d is indicated by the standardized unit. Usually p-SiTF
The LDD structure in the TLCD has a large purpose of suppressing a leak current in a pixel portion. That is, while the mobility of the p-Si layer is sufficiently high, the OFF current due to the p-type conduction poses a problem.
Reduce F current.

Such an LD region is formed by ion implantation of a low-dose impurity. However, when an ion shower is used, the amount of impurity implantation varies as shown in FIG. In some cases, the implantation of the region becomes excessive and the resistance of the LD region cannot be sufficiently obtained. When the doping amount of the LD region becomes excessive as described above, the resistance decreases, the suppression of the OFF current becomes ineffective, and the OFF current increases as shown by the broken line in FIG. When the OFF current increases, problems such as a decrease in the voltage holding ratio and a decrease in the contrast ratio occur.

For this reason, according to the present invention, a conventional ion implantation method is used for channel doping of an LD region or a driver portion which requires control of an implantation amount at a low dose amount, and other source and drain regions or silicon regions are used. An ion shower is used for a region formed by high-dose implantation such as reduction in resistance of a gate. FIG. 4 shows the dependence of sheet resistance on lamp power when recrystallizing a polysilicon film into which phosphorus ions have been implanted by an ion shower method using RTA (Rapid Thermal Annealing). In the figure, ☆ indicates that the dose is 7.0 × 10 {14 cm}.
In the case of -2, * indicates the case where the dose amount is 3.0 × 10 15 cm 2. The scanning speed at this time is 12 mm / s. In the drawing, the temperature of the film to be processed measured by a pyrometer for calculating the film temperature from the optical observation of the lattice state is entered. From this figure, the larger the dose, the more
It can be seen that the sheet resistance decreases and the sheet resistance decreases by increasing the lamp power.

When FIG. 4 is compared with FIG. 21, which is a similar measurement result when phosphorus ions are implanted into a polysilicon film using conventional ion implantation, the following can be understood. First,
Even at the same lamp power, the temperature of the polysilicon film itself is lower when the impurity is implanted by the ion shower than when the impurity is implanted by the ion implantation. This is because the polysilicon film into which impurities are implanted by the ion shower has a smaller amorphized region caused by implantation damage than the polysilicon film into which impurities are implanted by ion implantation. This also indicates that the amorphous layer has a lower light energy absorption. That is, even at the same lamp power, the film temperature varies depending on the degree of formation of the polycrystalline grains.

When the dose is 7.0.times.10.sup.14 cm.sup.-2, the sheet resistance of the polysilicon film into which impurities are implanted by the ion shower is larger than that of the ion implantation in the region where the lamp power is 20 kW or less. However, when the power exceeds 20 kW, the value obtained by the ion shower is lower and reaches 3.0 kΩ / □ or less. Furthermore, taking into account the temperature of the film itself as described above, the ion shower is more effective than the ion implantation at the same lamp power than the ion implantation.
It has dropped near 00 ° C. Thus, regarding the temperature of the film itself, which is directly related to the heat resistance of the substrate, the polysilicon film implanted with the impurity by the ion shower recrystallizes at a lower temperature than the polysilicon film implanted with the impurity by the ion implantation. It can be seen that the resistance is reduced.

Further, the dose amount is 3.0 × 10 ↑ 15 cm ↑ -2.
In comparison between the cases, the sheet resistance was lower than that of the ion implantation as a whole by using the ion shower. When the lamp power was 23 kW, the sheet resistance was 0.8 k.
Ω / □ has been achieved. Furthermore, considering that an implanted film by ion shower can be recrystallized at a lower film temperature than an implanted film by ion implantation, with respect to the temperature of the film itself, the larger the dose amount, the more the ion shower It can be seen that implant damage is recovered at lower temperatures than implant damage due to ion implantation.
This tendency is more remarkable as the dose is larger. In other words, in the ion shower, contrary to the ion implantation, the larger the dose, the smaller the amorphized region after implantation, and accordingly the lower the recrystallization temperature. From this, it is presumed that when doping impurities by an ion shower, ion implantation is performed while preventing or recovering damage to the silicon crystal.

Hereinafter, p-SiTF according to the gist of the present invention will be described.
An embodiment of a method for manufacturing T will be described. 5 to 14
FIG. 4 is a process cross-sectional view showing a manufacturing process. First, in FIG. 5, silane SiH4 is formed on a glass substrate (10).
Alternatively, 300 to 100 amorphous silicon (a-Si) is deposited by CVD using disilane Si2H6 as a material gas.
The a-Si is polycrystallized by excimer laser annealing at 400 ° C. with the substrate heated, and the polysilicon (p-Si) (1
1). This is called a reactive ion etch, ie, RI
Etch by TFT (reactive ion etch)
It is formed in an island shape to be an active layer of the portion.

Subsequently, as shown in FIG. 6, SiO 2 is laminated to a thickness of about 1000 ° by low pressure CVD at 400 ° C. to form a gate insulating film (12). Next, as shown in FIG. 7, a 2000- [mu] m thick poly-Si (1) was formed thereon by high-temperature CVD at 580 [deg.] C. using SiH4 as a material gas.
3a) is stacked and the resistance is reduced by performing an ion shower of phosphorus, and then tungsten silicide (WSi) (13
b) is sputtered to a thickness of 500-1500 °, preferably 1000 °. Continuously, normal pressure CV of 410 ° C
D to make the SiO2 1000-2000%, preferably 1
After laminating to a thickness of 500 mm, these SiO2 and p
The poly-silicide layer of poly-Si and WSi is etched in the same pattern by RIE, and the gate electrode (13) and a gate line connecting these to each other in a row in the pixel portion, and the gate electrode (13) and the gate line Form a coated injection stopper (14).

As shown in FIG. 8, normal pressure C at 410 ° C.
By depositing SiO2 by VD and etching it by RIE, side walls (1) are formed on the side walls of the gate electrode (13) and the injection stopper (14) thereon.
5) is formed. Next, as shown in FIG. 9, the gate electrode (13) and the side wall (15) are used as a mask to form phosphorus (P).
The first ion implantation of an n-type impurity such as is performed by ion implantation at an acceleration voltage of 80 keV and a dose of 3 × 10 °.
13 / cm ↑ 2 (3 × (1
0 to the power of 13). ). Thus, the source and drain regions (11S, 11S) have a self-aligned relationship using the gate electrode (13) and the side wall (15).
11D) and LD regions (11L) at low concentrations (n
-) Doping. At this time, immediately below the gate electrode (13) is a non-doped channel region (11N). In this step, the side wall (15) is used to secure a margin for lateral diffusion due to annealing after phosphorus ion implantation, reduce the impurity concentration at the end of the channel region, reduce the drain electric field, and reduce the breakdown voltage. Has the function of improving.

Subsequently, as shown in FIG. 10, a resist (R) having a size larger than that of the gate electrode (13) is coated, and a second ion implantation of phosphorus (P) is performed by ion shower using the resist as a mask. 90 keV, extraction voltage 10 keV, dose amount 1.0 × 10 ↑ 14 to 5.0 × 10
This is performed at {15 / cm} 2, for example, 7.0 × 10 ↑ 14 / cm ↑ 2. As a result, the region immediately below the resist (R) is formed as the LD region (11L) while being kept in the low concentration doping region (n−), and the outside of the LD region (11L) is heavily doped. Then, a source region (11S) and a drain region (11D) composed of the n + layer are formed. Here, in the doping by the ion shower, a throughput of 200 wafers / day was achieved, and the conventional 40 wafers / day was achieved.
It has risen significantly more than the day.

After the resist is stripped, the p-ch TFT similarly forms source and drain regions by a self-aligned structure, and then performs RTA in the state of FIG. 11 to form p-Si doped regions (11L, 11S, 11D). Activation and reduction of resistance by silicidation of the polycide layer (WSi / pSi) (13) are promoted. At this time, the resistance of the polycide and the p-type polysilicon is reduced by the conventional method of FIGS.
As can be seen from (2), the ion shower method achieves a sufficiently lower value. However, for the n-type polysilicon, both the heat resistant temperature of the substrate and the recrystallization of the polysilicon film are considered. It is necessary to set the lamp power supplied to the lamp and the temperature of the film to be processed and the scanning speed at that time. First, regarding the case where the dose amount is 7.0 × 10 {14 cm} −2, as shown in FIG. Although it is in the region between the dotted lines, the use of the ion shower method reduces the curve marked by a circle by about 200 ° C., thereby expanding the allowable range. In particular, as shown in FIG.
At m / s and a lamp power of 23 kW, a sheet resistance of 2.7 kΩ / □ was obtained at a film temperature of 780 ° C. to be processed. When this is applied to FIG. 22, the substrate is located far below the dotted line where the substrate may be curved, and it can be seen that both recrystallization and substrate protection have been achieved.
That is, the limit of the heat-resistant temperature of the soda glass substrate is 60.
Heat treatment at 0 ° C. or higher is possible, and further, processing at 780 ° C. or higher to obtain a sufficiently low sheet resistance value of 2.7 kΩ / □ is possible. Also, it can be seen that the scanning speed can be set to 12 mm / s or more, and at least 10 mm / s or more.

Further, the dose amount is 3.0 × 10 ↑ 15 cm ↑ -2.
4, a lower sheet resistance can be obtained from FIG. 4, and as in the case of the dose amount of 7.0 × 10 14 cm 2, recrystallization and low resistance are performed at a temperature lower by about 200 ° C. than by ion implantation. When this is applied to FIG. 22 in consideration of the fact that the recrystallization is achieved, it can be seen that recrystallization and low resistance are realized in a region below the dotted line. Therefore, a low-temperature process is possible at this dose.

Next, as shown in FIG.
After forming 2000 ° of SiO 2 by VD and annealing at 600 ° C., a further 3000 ° thick SiO 2 is formed by plasma CVD at 300 ° C. to form a first interlayer insulating film (16). Then, after performing H2 annealing at 450 ° C. for the purpose of terminating dangling bonds in silicon,
Drain and source regions (11D, 11D)
A contact hole (CT1, CT2) is formed in the gate insulating film (12) and the first interlayer insulating film (16) on S).

Then, as shown in FIG. 13, Ti / AlS
i is laminated by sputtering to a thickness of 7000 °, and is patterned by RIE to form a drain electrode (17) and a source electrode (18). The drain electrode and the source electrode are contact holes (CT1, CT2), respectively. It is connected to the areas (11D, 11S). Again, due to the dangling termination in silicon, 390 ° C. H
After performing the plasma treatment, as shown in FIG.
After stacking SiO 2 to a thickness of 2000 ° by CVD, the SOG film, that is, the SiO 2 film formed by spin coating and firing is coated and flattened.
The second interlayer insulating film (19) is completed by laminating SiO2 to a thickness of 1000 ° by CVD at 0 ° C. And
A contact hole (CT3) is formed in the second interlayer insulating film (19) by RIE.

Finally, as shown in FIG. 15, an ITO film is formed by sputtering, which is patterned by RIE to form a display electrode (20), and a source electrode (1).
8), the TFT substrate is completed.

[0053]

As is clear from the above description, according to the present invention, in the method of manufacturing the TFT having the LDD structure, the controllability is improved by using the ion implantation method for forming the low concentration region, and the decrease in the throughput is suppressed. In addition, by using the ion implantation method to form the high concentration region, the throughput could be greatly increased. This makes it possible to manufacture a TFT having good characteristics at low cost.

In activating the impurity-implanted region using the RTA method, the annealing temperature of the impurity-implanted region using the ion shower method can be lowered, and the scanning speed of the lamp can be increased. For this reason, the adverse effect on the substrate can be eliminated and the throughput can be increased by shortening the annealing time.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an ion shower device used in the present invention.

FIG. 2 is a diagram illustrating a relationship between a dose amount and a sheet resistance value by an ion implantation method and an ion shower method.

FIG. 3 shows transfer characteristics of a TFT with respect to the presence or absence of an LD region.

FIG. 4 is a graph showing the dependence of the sheet resistance of a polysilicon film whose resistance has been reduced by the ion shower method and RTA on the lamp power.

FIG. 5 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 9 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 10 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 15 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 16 is a configuration diagram of a liquid crystal display device.

FIG. 17 is a sectional view of a TFT.

FIG. 18 is a schematic view of an ion implantation apparatus.

FIG. 19 is a schematic diagram of an RTA apparatus.

FIG. 20 is a diagram showing the relationship between the sheet resistance of a tungsten polycide film formed by ion implantation and RTA and lamp power.

FIG. 21 is a graph showing the relationship between the sheet resistance of a polysilicon film whose resistance is reduced by ion implantation and RTA and lamp power.

FIG. 22 is a diagram showing a relationship between a film temperature and a scanning speed required for lowering the resistance of a polysilicon film subjected to ion implantation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Plasma source 2 Gas inlet 3 High frequency power supply 4 Leader electrode 5 Acceleration voltage 6 Suppression electrode 7 Ground electrode 8 Stage 10 Substrate 11 p-Si 12 Gate insulating film 13 Gate electrode 14 Injection stopper 15 Sidewall 16 First interlayer insulating film Reference Signs List 17 source electrode 18 drain electrode 19 second interlayer insulating film 20 display electrode CT1, CT2, CT3 contact hole R resist

──────────────────────────────────────────────────続 き Continued on the front page (72) Koji Suzuki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Masaru Takeuchi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka JP-A-4-320345 (JP, A) JP-A-59-39711 (JP, A) JP-A-62-299011 (JP, A) JP-A 8-320 124872 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 G02F 1/1368 H01L 21/265 H01L 21/336

Claims (9)

(57) [Claims] 1. A first step of forming a low-concentration region by implanting a first impurity having a predetermined conductivity type into a predetermined region of a semiconductor layer at a low dose, and a part of the low-concentration region. A second step of forming a high-concentration region in contact with a portion of the low-concentration region by implanting a second impurity having the same conductivity type as the first impurity at a high dose, In a method for manufacturing a semiconductor device having a third step of performing a heat treatment for activating impurities in the low-concentration region and the high-concentration region, the first step includes a step of forming a raw material containing a first impurity element. A step of extracting ions by discharge and a high electric field, extracting ions of a first impurity from these ions by mass spectrometry, and implanting the ions of the first impurity into the semiconductor layer. The second step is , The second impurity element A step of extracting ions by discharging and an electric field from the contained raw material and injecting all of these ions into the semiconductor layer; and a step of scanning at a predetermined speed with a heating source close to the heating source. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the raw material containing the second impurity element is a mixed gas of a hydrogen compound of the second impurity element and hydrogen. 3. The method according to claim 1, wherein the predetermined speed is 10 mm / sec or more. 4. The method according to claim 1, wherein the predetermined speed is equal to or greater than 12 mm / sec. 5. The method according to claim 1, wherein the implantation dose of the second impurity ions is 1 × 10 14 or more per unit square centimeter. . 6. The method according to claim 1, wherein an implantation dose of ions of the second impurity is 7 × 10 14 or more per unit square centimeter. A method for manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 1, wherein an implantation dose of the second impurity ions is 3 × 10 15 or more per unit square centimeter. . 8. The method according to claim 1, wherein the heating temperature in the third step is 600 ° C. or higher. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the heating temperature in the third step is 780 ° C. or higher.