JP3234470B2 - Lateral switching element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device such as a lateral type triac and thyristor.
The voltage dependence of the minimum trigger current I _FT or the minimum gate trigger current I _GT is reduced by suppressing the voltage dependence of _FE . Many phototriacs and photothyristors are of the lateral type, which is particularly effective. It is also particularly effective when the working voltage is high.

[0002]

2. Description of the Related Art FIG. 10 is a plan view of a conventional lateral phototriac, and FIG. 11 is a sectional view taken along the line BB 'of FIG. FIG. 10 shows FIG. 11 to prevent the drawing from becoming complicated.
Are omitted.

As shown in these figures, a P-type anode region 2 is formed on the surface of a silicon N-type substrate 1, for example.
2-1, gate region 3, 3-1; gate resistance 4, 4-1
Are formed symmetrically, for example, by diffusing impurities mainly containing boron. Further, in another step of diffusing impurities mainly containing phosphorus, the cathode regions 5, 5-1 and the channel stopper 6 around the N-type substrate 1 are formed inside the gate regions 3, 3-1.

A silicon thermal oxide film 7 is first formed on the surface of the N-type substrate 1 as a passivation film, and an oxygen-doped semi-insulating film 8 for adjusting initial withstand voltage and reducing leakage current is formed by, for example, polysilicon. Silicon nitride film 9 for improving the insulating property, non-doped C for improving the insulating property
A VD silicon oxide film 10 and the like are stacked. Since this is a photo triac, the gate regions 3, 3
On the surface of the silicon thermal oxide film 7 above -1, a passivation film above the surface is opened so that light can enter. Input / output metal wires 11, 11-1 are provided on the surface of the passivation film, and penetrate the passivation film and are connected to the anode region and the cathode region. The channel stopper 6 is connected to the metal wiring 11-2. The oxygen-doped semi-insulating film 8 on the surface of the silicon thermal oxide film 7 is connected to the terminal T via metal wirings 11 and 11-1.
₁ , T ₂ and metal wiring 11-2 of channel stopper 6
Is connected to

[0005] Terminal T₁And T_TwoAre metal wirings 11, 11
-1. Figure 15 shows the equivalent times of the triac
Road and terminal T₁And T_TwoBetween a pair of PNP
Thyristors of N structure are connected in parallel in the opposite direction.
Symbols for anode area, cathode area, gate area, etc.
10 or FIG. Terminal T ₁Is the anode area
Region 2 and the cathode region 5-1._TwoIs
Connected to the anode region 2-1 and the cathode region 5,
Light is incident on either the gate region 3 or 3-1.
Causes either the left or right thyristor to
The through current is switched in the opposite direction.

[0006]

FIG. 12 is a schematic sectional view of a portion from the gate region 3 to the anode region 2 in FIG. The terminal T ₁ plus, the terminal T ₂ is assumed that the negative voltage is applied. The two electrodes are connected to the oxygen-doped semi-insulating film 8. At this time, the depletion layer spreads from the reversely biased gate region 3. The oxygen-doped semi-insulating film 8 that are connected to the terminals T _1, T ₂ is a film having a large resistance, the potential distribution is present between both terminals of the terminals T ₁ and T _2. FIG. 13 is a graph showing the potential distribution, and the distribution is a straight line between the metal wirings 11 and 11-1 of the respective terminals as shown in FIG. In connection with this, between the potential existing on the N-type substrate 1 and FIG.
A potential difference as shown in FIG. When this potential difference exists, a P inversion layer 12 as shown in FIG. 12 is formed near the interface between the silicon thermal oxide film 7 and the N-type substrate 1 from the gate region 3 to which reverse bias is applied. It spreads to area 2.

As the P inversion layer spreads, the P region formed by the anode region 2, the N-type substrate 1, and the gate region 3
The effective base width of the NP transistor becomes shorter, and h _FE
And the minimum trigger current I _FT or the minimum gate trigger current I _GT decreases accordingly.

[0008] plus terminal T _2, when a negative voltage to T ₁ is applied, the same problems with the gate region 31 and anode region 2-1 is generated. Further, when the silicon substrate is a P-type, an N inversion layer is formed on the surface of the substrate, and an NPN transistor is a transistor in which h _FE becomes a problem.

The terminals T ₁ and T ₂ are in contact with a high resistance layer including a semi-insulating and insulating layer on the surface via metal wirings 11 and 11-1. Even an insulating layer does not have an infinite resistance value, and the above-described problem always occurs when the voltage increases.

An object of the present invention is to prevent the formation of an inversion layer on the substrate surface at a high voltage and stabilize the switching element in a lateral switching element having such a high-resistance passivation film. .

[0011]

According to one aspect of the present invention, a lateral switching element has a PNPN structure including an anode region, a cathode region, and a gate region on a surface of a substrate. is provided, above the surface of the base plate be those having a passivation film made of a plurality of high-resistance layer, the anti-inversion regions formed on the surface of the high resistance layer between the electrodes, inversion preventing regions Is
Connected to oxygen-doped semi-insulating film. Other lattes of the present invention
The Ral-type switching element is placed on the surface of the substrate
Region, a cathode region, and a gate region.
Electrodes are formed in the anode and cathode regions.
A plurality of high resistance layers are provided above the surface of the substrate.
With a passivation film consisting of
An inversion prevention area is provided on the surface of the high resistance layer between the poles to prevent inversion
The region is at the same potential as the substrate. Still another latte of the present invention
The Ral-type switching element is placed on the surface of the substrate
Region, a cathode region, and a gate region.
Electrodes are formed in the anode and cathode regions.
A plurality of high resistance layers are provided above the surface of the substrate.
With a passivation film consisting of
An inversion prevention area is provided on the surface of the high resistance layer between
Connect ET source and drain to P gate and cathode
And connect the gate of the MOSFET to the N-type substrate
Loss function is added.

[0012]

[0013]

The inversion prevention area is set to the same potential as the substrate. P
The conduction between the gate and the cathode is controlled by the MOSFET.

[0015]

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA 'of FIG.
10 and 11 are denoted by the same reference numerals. To prevent the drawing from becoming complicated,
1, the metal wiring of FIG. 2 is omitted.

The embodiment shown in FIGS. 1 and 2 and FIG.
The difference from the conventional example shown in FIGS. 0 and 11 is that the high voltage is applied between the anode region 2 and the gate region 3 (the cathode region 5 is provided inside the gate region 3), or the anode region 2 2-1 and gate region 3-1
(The cathode region 5-1 is provided inside the gate region 3-1.) The inversion prevention region 13 is provided in a high-resistance layer which is a passivation film on the surface between them.

[0017] In the example of FIG. 1 and FIG. 2, open at the top silicon nitride film 9 and the non-doped CVD silicon oxide film 10 of oxygen-doped semi-insulating film 8 between the electrode terminals T ₁ and T ₂ unit 14,14-1 , And metal wiring is provided therein to provide inversion prevention regions 13, 13. Since this embodiment is a triac, two inversion prevention regions are required, and the two can be joined to form a ring around the substrate. The inversion prevention region 13 is brought into contact with the N-type substrate 1 at an appropriate place on the N-type substrate 1, for example, at a peripheral portion thereof, and is set to the same potential as the N-type substrate 1. When the inversion prevention region 13 is brought into contact with the oxygen-doped semi-insulating film 8, the distance d between the contact portion and the connection portion of the metal wiring of the terminals T ₁ and T ₂ is at least a distance for obtaining a target breakdown voltage. .

FIG. 3 is a sectional view corresponding to FIG. 12 of the conventional example. Since the present invention has the above structure, the terminal T
Plus _1, when a high bias of minus terminal T ₂ is applied, a depletion layer from the gate area 3 with reverse bias (not shown) and P inversion layer 12 spreads.
At this time, since there is an inversion prevention region 13 connected to the oxygen-doped semi-insulating film 8 and having the same potential as the N-type substrate 1, the P inversion layer 12
Is prevented at the inversion prevention region 13. Therefore, the effective base width of the PNP transistor is prevented from being shortened, and _hFE is prevented from increasing.

FIGS. 4 and 5 correspond to FIGS. 12 and 13, respectively. As shown in FIG.
The potential in the oxygen-doped semi-insulating film 8 becomes the same potential as the terminal T _{1 on} the left side of the inversion prevention region 13. Further, as shown in FIG. 5, the potential difference between the oxygen-doped semi-insulating film 8 and the substrate becomes 0 on the right side of the inversion prevention region 13.

FIG. 6 is a graph showing the relationship between the distance d from the terminal T ₁ or T ₂ to the inversion prevention area 13 and h _FE (PNP). For a PNP transistor comprising an anode 2, an N-type substrate 1 and a gate region 3, the transistor has an I _B = 50 μA and a terminal T ₁ voltage of 280
V. As d increases, h _FE increases,
If d is constant, h _FE is also fixed to the corresponding value,
h _FE does not fluctuate. Therefore it is possible to reduce variation of the minimum trigger current I _FT or the minimum gate trigger current I _GT.

FIG. 7 is a graph showing the bias dependence of h _FE (PNP). Changing the bias voltage and I _B = 50 .mu.A similarly PNP transistor and FIG. The curve marked with a circle is according to the present invention, and d = 47.5 μm. The curve marked with a triangle is based on the conventional example,
There is no inversion prevention area, and the distance between terminals T ₁ and T ₂ is 395 μ
m. In the case of the conventional example, the voltage changes sharply around the voltage of 20 V, but according to the present invention, the voltage changes at a substantially constant rate.

FIG. 8 is a graph showing the bias dependence of the minimum trigger current _IFT . As in FIG. 7, the curve marked with a circle is d =
This is according to the present invention at 47.5 μm, and the curve marked with Δ is according to the conventional example. In the case of the conventional example, when the bias voltage exceeds 50 V, the I _GT sharply decreases.
According to the present invention, it decreases at a substantially constant rate up to around 400V. Even in the vicinity of over 500 V, the fluctuation is small as compared with the conventional example.

The above description has been made in the case of a lateral phototriac, but is also applicable to a photothyristor or a simple lateral triac or thyristor that is not triggered by light. Also, if the substrate is P
In the case of a mold, N inversion is prevented by providing an inversion prevention area.

FIG. 9 is an equivalent circuit diagram of the embodiment of the present invention as shown in FIGS. 1 and 2 in which a zero-cross function is added. It is almost the same as that shown in FIG. 15, but in FIG. 9, the P gate 3 or 3-1 of each PNPN structure and the cathode region 5 or 5-1 are shown.
So as to straddle the gate resistance 4 or 4-1 between
Source 21 or 21- of SFET 20 or 20-1
1 and the drain 22 or 22-1. The gate G ₁ or G ₂ of each MOSFET is connected to the N-type substrate 1. With the above structure, the terminal T
_{When an} AC voltage is applied between ₁ and T ₂ , assuming that the voltage of the terminal T ₁ is higher than the voltage of the terminal T ₂ , the potential of the connection portion 23 of the gate G ₁ of the N-type substrate 1 is the potential of the cathode region 5. Higher, a positive voltage is applied to the gate G ₁ , and when the AC voltage is higher than a predetermined threshold voltage V _TH,
The FET 20 operates, and the P gate 3 and the cathode 5 of the left thyristor are short-circuited. In this state, even if light enters, the phototriac does not operate. When the voltage of the terminal T ₂ is higher than the voltage of the terminal T ₁ occurs the same operation with respect to the right of the thyristor.

As described above, according to the embodiment of the present invention provided with the circuit of FIG. 9, when the AC voltage exceeds a predetermined value, each thyristor does not operate even if light enters, so that the switching element Can be further stabilized.

[0026]

As described above, according to the present invention, a high via
Due to the potential difference generated in the passivation film when applying
The inversion layer can be reduced, and the minimum trigger
Current I _FTFluctuations and stabilize operation.
Wear. By adding a zero-cross function, the
More stable operation of Irista or Phototriac
Can be

[Brief description of the drawings]

FIG. 1 is a schematic plan view of an embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a schematic sectional view showing the spread of an inversion layer according to the present invention.

FIG. 4 is a graph showing a potential distribution in an oxygen-doped semi-insulating film having a structure according to the present invention.

FIG. 5 is a graph showing a potential difference distribution between an oxygen-doped semi-insulating film having a structure of the present invention and a substrate.

FIG. 6 is a graph showing a relationship between a distance d from a terminal T ₁ or T ₂ to an inversion prevention area and h _FE .

FIG. 7 is a graph showing the relationship between h _FE and bias.

FIG. 8 is a graph showing a relationship between a minimum trigger current _IFT and a bias.

FIG. 9 is an equivalent circuit diagram of an embodiment of the present invention to which a zero cross function is added.

FIG. 10 is a schematic plan view of an example of a conventional switching element.

FIG. 11 is a schematic sectional view taken along the line BB ′ of FIG. 10;

FIG. 12 is a graph showing the spread of an inversion layer according to a conventional example.

FIG. 13 is a graph showing a potential distribution in a conventional oxygen-doped semi-insulating film.

FIG. 14 is a graph showing a potential difference distribution between a conventional oxygen-doped semi-insulating film and a substrate.

FIG. 15 is an equivalent circuit diagram of a triac.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-type substrate 2, 2-1 Anode diffusion region 3, 3-1 Gate diffusion region 4, 4-1 Gate resistance 5, 5-1 Cathode region 6 Channel stopper 7 Silicon thermal oxide film 8 Oxygen-doped semi-insulating film 9 Silicon nitride film 10 doped CVD silicon oxide film 11,11-1,11-2 metal wiring 12 P inversion layer 13 anti-inversion regions 14 opening T _1, T ₂ terminal d terminals T _1, T ₂ and a distance of the inversion prevention region

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-162570 (JP, A) JP-A-3-136248 (JP, A) JP-A-4-304675 (JP, A) JP-A-6-106 350077 (JP, A) JP 3-18355 (JP, B2) JP 1 16023 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/74 H01L 29 / 749

Claims (5)

(57) [Claims] 1. A PNPN structure is formed on a surface of a substrate, comprising an anode region, a cathode region and a gate region, electrodes are provided on the anode region and the cathode region, and a plurality of electrodes are provided above the surface of the substrate. In a lateral switching element provided with a passivation film made of a high resistance layer, an inversion prevention region is provided on the surface of the high resistance layer between both electrodes , and the inversion prevention region is connected to an oxygen-doped semi-insulating film. A lateral type switching element. 2. An anode region and a cathode on a surface of a substrate.
A PNPN structure is formed comprising a region and a gate region.
Electrodes are provided in the anode region and the cathode region.
Above the substrate surface.
Lateral switching element with a passivation film
Wherein an inversion prevention region is provided on the surface of the high resistance layer between the two electrodes, and the inversion prevention region has the same potential as the substrate.
A lateral switching element. 3. An anode region and a cathode on a surface of a substrate.
A PNPN structure is formed comprising a region and a gate region.
Electrodes are provided in the anode region and the cathode region.
Above the substrate surface.
Lateral switching element with a passivation film
In addition , an inversion prevention region is provided on the surface of the high resistance layer between both electrodes, and the source and drain of the MOSFET are connected to the P gate and the cathode.
And the gate of the MOSFET to the N-type substrate,
A lateral switching element characterized by adding a zero-cross function . 4. The reversal prevention area has the same potential as the substrate.
2. The lateral switching element according to claim 1, wherein: 5. A P-type source and a drain of a MOSFET.
Connected to the gate and cathode, and the gate of the MOSFET is N-type
It is connected to the board and features a zero cross function.
To, lateral type switching element according to claim 1, 2 or 4.