JP3234258B2 - Condition signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a condition signal generator,
In particular, the present invention relates to a condition signal generator for generating a condition signal used for controlling the operation sequence of a sequencer of an IC tester.

[0002]

2. Description of the Related Art An IC tester is provided with an address generator called a sequencer. This sequencer generates a sequence of addresses according to the test program and gives it to the word memory,
The generation order of a series of signals given to a test target (hereinafter, referred to as a DUT) is controlled.

One of the factors that determine the order of addresses generated by a sequencer is a condition code (hereinafter, referred to as CC). The sequencer uses a condition signal generator (condition code generator:
G), it is possible to change the address sequence generated based on various external conditions, the status of the DUT, and the like. This sequence change can take various aspects depending on the test object and purpose. For example, the DUT is determined to be defective and the generation of the address sequence is terminated, or another address sequence is generated based on the value of CC.

There are various signals such as a signal from a CPU and a timer signal as an input of a CCG, that is, a signal which is a source of determination of a conditional branch. In the following, for the sake of simplicity, the most important of them are shown in FIG.
A match / mismatch signal between the output of each pin of the DUT and the expected value data will be described.

A comparator prepared for each pin compares the output of that pin with the expected value stored in the word memory, and outputs a match signal MATCH if they match, and outputs a mismatch signal UNMATCH if they do not match, and outputs a CCG. Send to At this time, especially for pins for which it is not necessary to see the match / mismatch,
DON'T CARE status can be defined, MA regardless of match / mismatch
It can also output a TCH signal.

In the conventional CCG, as shown in FIG. 5, the match / mismatch signals given in this way are ANDed together and the unmatched signals are ORed together. By taking this into a single mismatch signal, a CC is generated from these combined results to control the address generation sequence. It should be noted that a set of matching signals is selected as CC,
Whether to select a group of unmatched signals as CC depends on the contents of the test program.

In order to increase the test throughput, there is a method called a multi-DUT test for simultaneously testing a plurality of DUTs. In addition, a multifunction test for functionally dividing the inside of an IC, which has been increasingly complicated these days, into a plurality of blocks and testing these blocks simultaneously or in association with each other has been required.

In performing this type of test, DU
MATCH independently for each T or each function block
/ UNMATCH to perform conditional branching, DUT
Needs to be changed.

However, such a complicated condition cannot be generated by a conventional CCG having only one system for collecting match / mismatch signals.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a CCG capable of supporting a multi-DUT test and a multi-function test.

[0011]

According to one embodiment of the present invention, a match / mismatch signal is allocated to a plurality of systems, and an AND for a match signal and an OR for a mismatch signal are assigned to each system, so that Put together. A match / mismatch signal grouped for each of these systems (hereinafter, an integrated match signal /
Further, the CC is generated by logically synthesizing the integrated mismatch signal.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention in which match / mismatch signals are assigned to four systems A to D. In FIG. 1, first, in stage I, the DUT
.., N (not shown) and the expected value data match when the comparison is true.
MATCH1, MATCH2,..., MATCHn, and a mismatch signal UNMATCH1, UNMATCH2,.
A selector is provided for each Hn, and the selectors are assigned to systems A, B, C, and D, respectively. That is, at this stage, pin i (i is
When the attribute of assigning the coincidence signal MATCHi to the system x (x is one or a plurality of A, B, C, and D) for 1 to n is given, the signal ixMEN
Is 1 and the others are 0. Similarly, the mismatch signal UNMATCHi
Is assigned to the system y, the signal iyUMEN is set to 1 and the others are set to 0. Note that this stage is actually placed near each comparator.

In stage II, the matching / mismatching signal thus distributed is converted into an analog signal for each system in the same manner as in the prior art.
D-gates and OR-gates are combined to obtain integrated match signals MATCH A, MATCH B, MATCH C, MATCH D and unmatched unmatched signals UNMATCH A, UNMATCH B, UNMATCH C, UNMATCH D for each system. The arrangement positions of the AND gates and OR gates in this stage can be determined according to the physical shape of the actual system and other various constraints.

In stage III, AND / OR logic synthesis is further performed on the integrated coincidence signal and integrated non-coincidence signal for each system given from stage II using a logic circuit.
In logic synthesis performed by a logic circuit, up to four arbitrary systems are selected from the four systems under the control of a test program, and AND and OR are taken, and AND
It can be output from the output and the OR output. The type of logic synthesis performed by the logic circuit can be freely changed by the test program during the operation of the CCG.

In stage IV, the result of the logic synthesis in stage III is selected by the multiplexer MUX under the control of the test program, and the final CC is output. This selection can also be changed during CCG operation. Stage I
The arrangement of the logic circuits II and IV and the multiplexer is determined in the same manner as in the stage II.

In the operation of the CCG shown in FIG.
Up to the above, the logical operation is performed between the coincidence signals and the non-coincidence signals, and the selection is performed from the results of these logical operations in the stage IV. However, the logical operation over the coincidence signal and the non-coincidence signal may be performed. For example, A of MATCH A and UNMATCH B
Signal distribution / combination such as taking ND is also possible.

For example, in stage III of FIG. 1, a logical operation is performed between UNMATCH A to UNMATCH D, and a logical operation is separately performed between MATCH A to MATCH D.
These results are provided to the multiplexer. In such a configuration, the final output CC is made from only the MATCH signal or only the UNMATCH signal.

In order to further increase the degree of freedom of CC generation,
For example, the stages III and IV in FIG. 1 may be configured as shown in FIG. In FIG. 3, UNMA
An AND or OR of a set of signals arbitrarily selected from TCHA to UNMATCH D and MATCH A to MATCH D (that is, a match signal and a mismatch signal may be mixed) can be obtained. Therefore, for example, taking the signal of FIG. 1 as an example, a signal such as UNMATCH A AND UNMATCH B AND MATCH C can be generated as CC.

Further, as described above, the signal serving as the CC source is not limited to the comparator output of each pin. In addition, there are signals from a CPU (controller of an IC tester) and signals from a timer and the like. Also, while the comparator output is a signal related to a digital pin,
In an IC tester for testing a mixed analog / digital DUT, an analog signal can also be a CC source. In digital systems, for example, the obtained DUT
If the tester has a function of performing digital processing such as digital signal processing on the output of the tester, the result of the signal processing (output of the signal processing hardware) can be used as a CC source. Furthermore, a CC can be generated by combining a match / mismatch signal with these various signals. These signals are optionally provided, for example, in stages I through I of FIG.
Can be given anywhere in Stage IV.

In the following, using the circuit shown in FIG.
Consider the generation of a CC in the case where the same signal is simultaneously supplied to two B-type DUTs to perform a test. In this case, a mismatch signal for A is assigned to UNMACTH A, and a mismatch signal for B is assigned to UNMATCH B, and AND of both is given as CC. When the CC becomes 1, the test program stops the test halfway and shifts to the next DUT, C and D tests. In this way, when both DUTs provide an output different from the expected value, the test is aborted, thereby improving the test throughput.

For a multi-function DUT,
If tests for each function block can be performed independently of each other, if each function block is considered as a separate DUT, a high test throughput can be obtained by the same method as the above-described test for a plurality of DUTs.

In a multi-function DUT such as that shown in a communication IC, which has two channels of input and synchronizes with each external signal and outputs a result obtained by performing some processing on the signal, as shown in FIG. The following tests can be performed using the circuit shown in FIG. First input, the input synchronization circuit A that are related respectively to the synchronization of the second input, input synchronization circuit
'Synchronous detection signal A from, synchronous detection signal A' A a, respectively
Allotment is performed so as to be output to MATCH A and MATCH B, and the OR of both signals is taken as CC. Further, the multiplexer MUX in Figure 2 with the synchronous detection signal A and the same <br/> life detection signal A '
Creates an external control signal, and inputs on the side where synchronization is detected first.
Select a synchronous circuit . Here, if the operation of the test program shifts to the test of the signal processing block of the DUT due to a change in CC, the signal processing block is used by using the channel that succeeded in synchronization earlier among the two channels A and A '. Test. Thereby, the test throughput can be improved.

[0023]

As described in detail above, according to the present invention, a CC can be generated under more flexible conditions than in the past, so that the present invention is applied to a multi-DUT test or a multi-function test. As a result, remarkable effects such as improvement of test throughput and facilitation of test program creation can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a condition signal generator according to an embodiment of the present invention.

FIG. 2 shows a DU that can be tested using the present invention.
The figure which shows the example of T.

FIG. 3 is a view for explaining a modification of the embodiment of the present invention in FIG. 1;

FIG. 4 is a diagram illustrating an IC tester according to the related art.

FIG. 5 is a diagram illustrating a conventional condition signal generator.

[Explanation of symbols]

 match1 to matchn: match signal unmatch1 to unmatchn: mismatch signal match A to match D: integrated match signal unmatch A to unmatch D: integrated mismatch signal MUX: multiplexer

Continuation of the front page (72) Inventor Takayuki Iidagu 9-1 Takakuracho, Hachioji-shi, Tokyo Yokogawa-Hewlett-Packard Co., Ltd. (56) References JP-A-59-228178 (JP, A) JP-A Sho 59-19873 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 31/28

Claims (4)

(57) [Claims] An output for each of a plurality of output terminals to be tested.
Compare the signal with the expected signal to determine the match and mismatch signals, respectively.
Generating means and selecting each of the coincidence signals to each of a plurality of systems.
First allocating means for allocating through a plurality of systems , and the first allocating operator grouped for each of the plurality of systems.
From the signal from the stage, an integrated coincidence signal is generated for each of the plurality of systems.
Means for outputting an integrated coincidence signal for each of the plurality of systems by program control.
AND and OR operations on any of the signals
From the first AND output and the first OR output.
First logic synthesizing means for respectively outputting a result, and transmitting each of the mismatch signals to each of the plurality of systems.
Second allocating means for allocating via a selector, and the second allocating means grouped for each of the plurality of systems.
From the signal from the stage, the integrated mismatch signal is
Integrated mismatch signal generation means for outputting to the plurality of systems the integrated mismatch
AND and OR for any of the plurality of signals
Performs an operation and calculates the second AND output and the second OR output.
Second logic synthesizing means for respectively outputting a result, and the first and second AND outputs
And a condition signal selected from the first and second OR outputs
And a multiplexer means for generating
Condition signal generator. 2. Each of the selectors of said first allocating means.
Has an OR operation circuit, and the selector of the second allocating means.
Characterized in that each of the elements has an AND operation circuit.
The condition signal generator according to claim 1. 3. The integrated coincidence signal generation means according to claim 1, wherein
And the integrated mismatch signal generating means has an OR operation circuit.
The article according to claim 1 or 2, wherein
Signal generator. 4. The operation of said first and second logic synthesizing means.
The selection of the multiplexer means depends on the condition signal generator.
Note that the program can change the settings while the
A condition signal according to any one of claims 1 to 3, characterized in that:
Generator.