JP3231696B2 - LCD drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal drive circuit for outputting a liquid crystal drive voltage to a liquid crystal display panel, and more particularly to a liquid crystal drive circuit using a capacitance array type analog / digital conversion circuit.

[0002]

2. Description of the Related Art In recent years, with the advance of downsizing of computers, a thin film transistor liquid crystal display panel characterized by low voltage, light weight and thinness has been attracting attention as a display device replacing a CRT. Referring to FIG. 26, display data via a data buffer circuit (hereinafter, referred to as DBF) 70 is provided to one of the liquid crystal driving circuits for driving the thin film transistor liquid crystal display panel having the above characteristics.
The digital signal is temporarily held by a latch circuit (hereinafter, referred to as LAT) 80 as it is, and is converted into a digital / analog conversion circuit (hereinafter, referred to as DAC) 9 immediately before the liquid crystal display panel 200.
There is a drive circuit 100 that performs digital processing to 0.

A DAC 90 has a resistor string type DAC (hereinafter referred to as an R-DAC) whose block diagram is shown in FIG.
) And a capacitance array type DAC (hereinafter, referred to as C-DAC) whose block diagram is shown in FIG. Referring to FIG. 27, R-DAC 90R includes a resistor 91 and a switch group 9
And one of the switch groups 92 is turned on by the input digital data,
Obtain a desired analog voltage value. In the liquid crystal drive circuit using the R-DAC, digital data sorted by the DBF is temporarily input to the latch group 81 once. After the data is input to all the LATs in the latch group 81, the data is transferred from the latch group 81 to the next R-DAC 90R. In the R-DAC 90R, one switch corresponding to the input digital data is selected from the switch group 92 and output via an operational amplifier 93 for the purpose of impedance conversion.

On the other hand, referring to FIG. 28, a C-DAC 90
C is configured using a weighted capacity group 94 and an operational amplifier 95. The C-DAC 90C obtains a desired voltage value by utilizing the redistribution of the electric charge stored in the capacitor group 94 and the characteristics of the operational amplifier 95. C- of the above configuration
In the DAC type liquid crystal drive circuit, the operation from the latch group 81 to the data transfer to the next stage is the same as the operation in the above-described R-DAC type liquid crystal drive circuit. Next, the data transferred from the latch group 81 to the next stage is divided into upper bit data and lower bit data, and the upper bit data is input to a multiplexer circuit (hereinafter, referred to as MUX) 96. In the MUX 96, two adjacent voltage values are selected from a plurality of externally input gamma (γ) correction voltage values 97 in accordance with the input upper bit data, and the selected voltage value is sent to the next-stage C-DAC 90C. Transfer data. Here, the two adjacent voltage values selected by the MUX 96 are, for example, V ₀ to V ₁ from the higher γ correction voltage value level.
When a ₉ means a voltage value, such as V ₃ and V ₄ or V ₅ and V _6. On the other hand, the lower bit data is
It is input to a control circuit (hereinafter referred to as CONT) 98 in the C-DAC. The CONT 98 is a circuit that operates a group of switches so that an analog voltage value corresponding to digital data can be generated in the C-DAC. CONT
In the C-DAC 90C including the 98, the two adjacent voltage values input from the MUX 96 are equally divided, and one of them is output. For example, a 5-bit C-DAC
Then, the two voltage values selected by the MUX 96 are equally divided into 32, and one of the 32 equally divided values is selected with reference to the 5-bit data input to the CONT 98, and the operational amplifier is selected. 95.

FIG. 29 is a detailed view of the C-DAC shown in FIG.
Shown in Referring to FIG. 29, the C-DAC shown in FIG. 29 is a 5-bit C-DAC of upper 2 bits + lower 3 bits. The switches in the figure are switched by signals from the CONT 98. The operation of the 5-bit C-DAC is
Perform data hold after data sampling. For example, in the case of a positive output, SW6, SW
7, SW8Bar turns on. The switches in the upper 2 bits and lower 3 bits are determined by the data input to the preceding CONT 98, and one of the switches is turned on.

Next, at the time of hold, SW6 and SW7 are turned off and SW8 is turned on. The switches in the upper 2 bits and lower 3 bits are determined by the data previously input to the previous CONT 98, and either switch is turned on.

In the case of negative polarity, SW6, S
W7 and SW8 are turned on. The switches in the upper 2 bits and lower 3 bits are determined by the data input to the preceding CONT 98, and one of the switches is turned on.

Next, at the time of hold, SW6 and SW7 are turned off, and SW8Bar is turned on. The switches in the upper 2 bits and lower 3 bits are determined by the data previously input to the previous CONT 98, and either switch is turned on.

By performing the above operation, the output voltage V _out becomes a voltage represented by the following equation. V _out = 2V _ref
−V _in2 − (V _in1 −V _in2 ) × α / 32
_Vout = _Vin2 + ( _Vin1 − _Vin2 ) × α
/ 32 (α = 0, 1, 2, 3, ‥‥, 31) α is determined by data input to the CONT 98. That is, if “00000”, α = 0 and “1111”
If it is 1 ', α = 31.

Here, in order to facilitate understanding of the present invention,
The characteristics of the liquid crystal will be described. Generally, the driving circuit of the liquid crystal display panel is used to prevent the ionization phenomenon of the liquid crystal.
It is necessary to perform AC driving (reverse polarity output driving) that changes the output polarity for each frame. That is, the AC driving is a driving method in which a pixel whose first frame has a positive polarity with respect to the reference voltage on the liquid crystal side has a negative polarity with respect to the reference voltage in the next frame. Therefore, even if the liquid crystal drive circuit expresses, for example, 256 gradations, it is actually necessary to be able to generate 512 gradations by combining the positive polarity component and the negative polarity component. In other words, an R-DAC liquid crystal driving circuit of 256 gradations requires 512 selection switches.

On the other hand, in the case of the C-DAC type liquid crystal driving circuit, as described above, the reverse polarity output can be easily performed by converting the switching operation of the switch group. There is no need to increase the unit capacity. That is, there is no circuit increase due to the necessity of reverse polarity output drive, which is a feature of liquid crystal drive. CD having such a configuration
An example of the AC is disclosed in Japanese Patent Application No. 8-027075 “Liquid crystal image signal control method and control circuit” or in Japanese Patent Application No. 9-168824 “Switched” by the same assignee of the present invention.
Capacitor DA conversion circuit, control method therefor, and LCD
Drive Control Circuit and LCD Drive Control Method ".

Another characteristic of the liquid crystal is that the light transmittance with respect to the applied voltage is not constant and has a special curve called a γ curve. Therefore, in the liquid crystal drive circuit, it is necessary to perform γ correction according to the γ curve. The characteristic of the γ curve is that the shape of the curve differs depending on the applied voltage applied to the liquid crystal, and the light transmittance changes abruptly when the applied voltage is higher and lower than the reference voltage on the liquid crystal side, and the intermediate voltage In the region, the transmittance changes relatively slowly.

[0013]

The R-DA shown in FIG.
A feature of the C-mode liquid crystal drive circuit is that more accurate color reproduction can be achieved by dividing the resistor 91 so as to match the γ curve of the liquid crystal display panel. However, selection switches for the number of gradations are necessary. For example, in an 8-bit liquid crystal driving circuit that reproduces 256 gradations, 512 selection switches including a switch for frame switching of polarity inversion are required. For this reason, an increase in the area of the circuit accompanying the increase in the number of gray scales becomes a serious problem.

On the other hand, a feature of the liquid crystal driving circuit using the C-DAC shown in FIG.
By further dividing C internally, the number of unit capacities normally required can be reduced. Figures 28 and 2
9 is a 5-bit C-DAC 90C.
It is. Normally, a 5-bit C-DAC requires 64 unit capacitors, but as shown in FIG.
By dividing AC into upper 2 bits + lower 3 bits,
The unit capacity can be reduced to 16 units. Further C-
Since the polarity inversion for each frame, which is a feature of the DAC, can be performed by changing the driving method, reverse polarity output without increasing the area is possible.

As described above, according to the liquid crystal driving circuit using the C-DAC, it is possible to suppress an increase in area due to an increase in the number of bits. However, in the conventional C-DAC, MUX
The external input γ correction voltage value 97 selected at 96 can be divided only by equal division with a certain fixed coefficient. For example, in a normal 8-bit liquid crystal driving circuit, a 5-bit C-DA
C is prepared and the two voltage values selected by the MUX 96 are equally divided into 32 by C-DAC. However, since the equal division is always performed according to a certain coefficient (in this case, 32 equally divided),
It is difficult to match the γ curve of the liquid crystal. Liquid crystal γ
In order to match the output voltage to the curve, it is necessary to output a straight line at the center of the applied voltage, but to make the output voltage high and low in a curve.

That is, in a drive circuit using an R-DAC, an increase in area due to the amplification of the number of bits becomes a problem, and the C-DA
In a drive circuit using C, it is difficult to perform γ correction, which is disadvantageous in color reproduction. Therefore, an object of the present invention is to provide a CD
An object of the present invention is to make it possible to make the output of a C-DAC closer to the γ curve of a liquid crystal display panel in a liquid crystal drive circuit using AC.

[0017]

A liquid crystal drive circuit according to the present invention includes a capacitance array type digital / analog conversion circuit, and is externally input based on upper P bits of N-bit input data to be displayed. Two voltages adjacent to each other are selected from the plurality of γ correction voltages, and a portion between the two selected γ correction voltages is converted into the remaining lower bits of the input data to be displayed by the digital / analog conversion circuit. Equally divided into the appropriate number, the maximum γ correction voltage and the minimum
By dividing between the γ correction voltage and the γ correction voltage by 2 ^N , the N
In a liquid crystal driving circuit that generates 2 ^N voltages from bit input data and outputs one of them as a liquid crystal driving voltage, the number of bits of the input data to be displayed is changed to F bits larger than N. Amplify and F
The plurality of γ corrections using upper P bits of bit data
Two adjacent gamma correction voltages selected from the voltages
And specify the remaining lower FP bits of the F-bit data.
And select the digital-to-analog conversion circuit
Between two γ correction voltages which are Shi was equally divided into up to 2 ^FP
Of the two adjacent gamma correction voltages.
The input data so that the total number of equal divisions between them is 2 ^N
Is provided with a bit conversion circuit for amplifying the
The total number of divisions between the correction voltage and the minimum of the γ correction voltage to 2 ^N
Maximum equality between two adjacent gamma correction voltages while maintaining
It is characterized in that the divisor can be set to 2 ^FP larger than 2 ^NP .

According to the present invention, the number of bits is increased internally in a C-DAC type liquid crystal driving circuit which can output only by equal division according to a certain coefficient. For example, when the data to be displayed is 8 bits, conventionally, the 8 bits are divided into upper 3 bits and lower 5 bits. And 5
Using the C-DAC of bits, the MUX 96 divides between two external gamma correction voltage values selected by referring to the upper three bits into 32 equal parts. That is, it could only be divided into 32 equal parts. The liquid crystal drive circuit of the present invention includes a bit conversion circuit for amplifying the number of bits of the display data from 8 bits to 9 bits. This bit conversion circuit makes it possible to increase the number of lower bits from 5 bits to 6 bits, such as upper 3 bits and lower 6 bits, and divide the display data into the maximum number of divisions of the γ correction voltage. 32
To 64. Then, according to the value of the γ correction voltage to be divided, the number of divisions is selected from among eight equal divisions, sixteen equal divisions, thirty-two equal divisions, and sixty-four divisions.
The output voltage of C is made closer to the ideal γ curve of the liquid crystal display panel.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a liquid crystal drive circuit according to the first embodiment of the present invention. Referring to FIG. 1, an N-bit data buffer circuit 1 has an N-bit input terminal and an N-bit output terminal, and transfers N-bit input data to a next-stage bit conversion circuit 2. .

The bit conversion circuit 2 has an N-bit input terminal and an F-bit output terminal (where F is larger than N), and is connected to the output terminal of the data buffer circuit 1.
The number of input bits of N bits is amplified to F bits as necessary.

The data latch circuit 3 has an F-bit input terminal and an F-bit output terminal, and is connected to the output terminal of the bit conversion circuit 2 to hold the input F-bit data.

The multiplexer circuit 4 outputs the upper P-bit data of the output data of the F-bit data latch circuit 3 and x
External input gamma correction power supply (not shown) that outputs voltage values
Connected to. Then, referring to the upper P-bit data transferred from the data latch circuit 3, two adjacent voltage values are selected from among the x voltage values of the external input γ correction power supply, and the selected analog voltage value is calculated. Transfer to the next stage.

The digital-to-analog conversion circuit 5 has a capacity array type of G bits, and includes two analog voltage signals output from the multiplexer circuit 4 and lower G-bit data (F bit output output from the data latch circuit 3). G =
FP) as input, divides two analog voltage signals output from the multiplexer circuit 4 into equal parts, and, based on the input data from the data latch circuit 3, converts the equal-divided voltage values according to the input data. The liquid crystal drive voltage value is output.

The operation of the embodiment will be described below. Generally, the output voltage V _out of an N-bit C-DAC is represented by the following two equations. The following two equations are output voltages at the time of polarity inversion. V _out = 2V _ref −V ₀ − (V ₁ −V ₀ ) × α / n V _out = V ₀ + (V ₁ −V ₀ ) × α / n (α = 0, 1, 2, 3, ‥‥ , N−1 n = 2 ^N ) where V _ref is a reference voltage input from the outside for performing an operation in the C-DAC, and V ₀ and V ₁ are γ corrections input from the external input. Voltage. For example, in the case of a 5-bit C-DAC, it is represented by the following equation. V _out = 2V _ref −V ₀ − (V ₁ −V ₀ ) × α / 32 V _out = V ₀ + (V ₁ −V ₀ ) × α / 32 (α = 0, 1, 2, ‥‥, 31 Therefore, from the above equation,
In the case of a 5-bit C-DAC, it can be seen that the voltage difference between V ₀ and V ₁ is divided into 32 equal parts using V _ref as a reference voltage.

Generally, in the case of a liquid crystal drive circuit of 256 gradations (8-bit precision), nine voltages V _{0 to} V ₈ are prepared as gamma correction voltages input from the outside. And
By the 5-bit C-DAC, 32 equal division between V ₀ ~V _1,
V ₁ ~V ₂ between the 32 equal division, V ₂ ~V ₃ between the 32 equal division, ‥‥, V ₇ ~V ₈ between split the 32 like, after all, gamma correction from external voltage V ₀ ~V ₉ The interval is 25 by 32 equal divisions x 8
256 gradations are realized by dividing the image into six equal parts.

[0026] In this embodiment, the C-DAC, by way of example, V ₀ ~V ₁ during the 16 equal division, V ₁ ~V ₂ between the 16 equal division, V ₂ ~V ₃ between the 32 equal division, V ₃ ~V ₄ between the 64 equal division, V ₄ ~V ₅ during the 64 equal division, V ₅ ~V ₆
The space is divided into 32 equal parts, the space between V _{6 and} V ₇ is divided into 16 equal parts, V ₇ -V
_The interval between ₈ is divided into 16 equal parts, for a total of 256 divisions. In other words, by changing the number of divisions between two adjacent voltages in the nine γ-correction voltages V ₀ , Ｖ, and V ₈ according to the magnitude of the divided voltage value, the output 256 Bring the gradation voltage closer to the γ curve of the liquid crystal.

In order to realize the above dividing method, N
Table 1 (FIG. 4) to Table 6
It is necessary to amplify the number of bits as shown in FIG.
For the sake of convenience of the following description, FIG. 2 shows a case where 256 bits are realized in the present embodiment, where 8 bits are converted to 9 bits and divided into upper 3 bits and lower 6 bits. A block diagram in which numerical values are specifically substituted is shown. With reference to FIG. 2 and Tables 1 to 6, Table 1 (FIG. 4) corresponds to FIG. 2 and shows a case where V ₀ -V ₁ is divided into 16 equal parts and V ₁ -V ₂ is divided into 16 equal parts. It is a table | surface which shows the conversion method of bit-> 9 bits. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. If the upper 4 bits are '0000',
'000' is input to the multiplexer circuit 4. Top 4
If the bit is '0001', the multiplexer circuit 4
To enter '001'.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 16 equal divisions, the lower 2 bits of the lower 6 bits may be '00'. Therefore, the lower 4 bits of the input 8 bits are used as they are as the upper 4 bits of the lower 6 bits, and “00” is added to the lower 2 bits and input to the digital / analog conversion circuit 5.

Table 2 (FIG. 5) shows V ₂ -V corresponding to FIG.
9 is a table showing a conversion method from 8 bits to 9 bits when dividing ₃ into 32 equal parts. First, the upper 3 bits to be input to the multiplexer circuit 4 are converted into the upper 4 bits of the input 8 bits.
Judge from bits. When the upper 4 bits are “0010” and “0011”, the multiplexer circuit 4
'010' is input to.

Next, a method of generating lower 6 bits for inputting to the digital / analog conversion circuit 5 will be described. In the case of 32 equal divisions, the lower 1 bit of the lower 6 bits may be '0'. Therefore, the lower 5 bits of the input 8 bits are used as they are as the upper 5 bits of the lower 6 bits, and the lower 1 bit is set to “0” and input to the digital / analog conversion circuit 5.

Table 3A (FIG. 6A) and Table 3B (FIG. 6A)
(B)) is a table showing a conversion method from 8 bits to 9 bits when dividing between V _{3 and} V ₄ into 64 equal parts corresponding to FIG. 2. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. Upper 4 bits are '0100', '0101', '0
Multiplexer circuit 4 for 110 'and' 0111 '
Enter '011' in the field.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 64 equal divisions, the lower 6 bits are directly input to the digital / analog conversion circuit 5.

Table 4A (FIG. 7A) and Table 4B (FIG. 7A)
(B)) is a table showing a conversion method from 8 bits to 9 bits when dividing between V _{4 and} V ₅ corresponding to FIG. 2 into 64 equal parts. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. Upper 4 bits are '1000', '1001', '1
In the case of 010 'and' 1011 ',' 100 'is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 64 equal divisions, the lower 6 bits are directly input to the digital / analog conversion circuit 5.

Table 5 (FIG. 8) shows V ₅ -V corresponding to FIG.
9 is a table showing a conversion method from 8 bits to 9 bits in a case where ₆ is divided into 32 equal parts. First, the upper 3 bits to be input to the multiplexer circuit 4 are converted into the upper 4 bits of the input 8 bits.
Judge from bits. When the upper 4 bits are “1100” and “1101”, the multiplexer circuit 4
To enter '101'.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 32 equal divisions, the lower 1 bit of the lower 6 bits may be '0'. Therefore, the lower 5 bits of the input 8 bits are used as they are for the upper 5 bits of the lower 6 bits, and
The bit is set to “0” and input to the digital / analog conversion circuit 5.

Table 6 (FIG. 9) shows V ₆ -V corresponding to FIG.
₇ is a table showing a conversion method from 8 bits to 9 bits in a case where the interval between _{7 is} equally divided into 16 and the interval between V _{7 and} V ₈ is equally divided into 16; First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When the upper 4 bits are “1110”, “110” is input to the multiplexer circuit 4. Upper 4 bits are '111'
In the case of “1”, “111” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 16 equal divisions, the lower 2 bits of the lower 6 bits may be '00'. Therefore, the lower 4 bits of the input 8 bits are used as they are as the upper 4 bits of the lower 6 bits, and “00” is added to the lower 2 bits and input to the digital / analog conversion circuit 5.

When performing the above-described division, V ₃ -V
_{Since the} interval between _{4 and the} interval between V _{4 and} V ₅ are equally divided into 64, a 6-bit C-DAC is required. That is, in the 8-bit liquid crystal driving circuit, a 5-bit C-DAC is conventionally used, but the present embodiment requires a C-DAC in which the number of bits is amplified up to 6 bits. The output voltage of the 6-bit C-DAC is represented by the following equation. V _out = 2V _ref -V
_m− (V _{m + 1} −V _m ) × α / 64 V
_{out = V m + (V m} + 1 -V m) × α / 64
(Α = 0, 1, 2, 3, ‥‥,
63 m = 0,1,2, ‥‥, 7) This expression means that the two voltages are equally divided by 64. In the present embodiment, since between V ₀ ~V ₁ is the 16 equal division, alpha
Are 0, 4, 8, and ‥‥. In the part where the division is made into 32 equal parts, α may be only 0, 2, 4, 6, ‥‥.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram of a liquid crystal drive circuit according to the second embodiment. In this embodiment, N bits · F
The configuration of the bit conversion circuit 20 is different from that of the first embodiment, and is the same as that of the first embodiment.
It has many F-bit conversion circuits (see FIG. 1). Then, they first bit conversion circuit 2 _1, second bit conversion circuit 2 _2, a third bit conversion circuit 2 _3, 4-bit conversion circuit 2 _4, the output data format of each bit conversion circuit ‥‥ like,
Each one is different. Next stage latch circuit 3
In response to a selection signal from the outside, a variety of N
One of the bit / F bit conversion circuits is selected and data is input. Thus, the data format input to the latch circuit 3 can be selected from various types of output data having different characteristics.

In the present embodiment, by providing various types of bit number conversion circuits, as an example, V _{0 to} V ₁ are divided into 32 equal parts and V _{1 to} V ₂ by a selection signal input from the outside.
Is divided into 32 equal parts, between V _{2 and} V ₃ is divided into 32 equal parts, and V ₃ -V
₄ During the 32 equal division, V ₄ ~V ₅ between the 32 equal division, V ₅ ~
During V ₆ 32 equal division between V ₆ ~V ₇ 32 equal division, V ₇
The case ~V ₈ during the to 256 gradations by dividing 32 etc., V
₀ ~V 16 equal division ₁ with C-DAC, the V ₁ ~V ₂ 16
Equally divided, V ₂ ~V ₃ to 32 equal division, V ₃ ~V ₄ 64 equal division, V ₄ ~V ₅ 64 equal division, V ₅ ~V ₆ to 32 equal division, V ₆ ~V ₇ to 16 Equal division, dividing V ₇ -V ₈ into 16 equal parts to 256 gradations, and C-DA between V ₀ -V ₁
16 equal division in C, 32 equal division between V ₁ -V _2, V ₂ -V
₃ during the 32 equal division, V ₃ -V ₄ between the 64 equal division, V ₄ -
V ₅ during the 32 equal division, 32 equal division between V ₅ -V _6, V ₆
It is characterized in that switching can be performed, for example, when the interval between −V ₇ is divided into 32 equal parts, and between V _{7 and} V ₈ is divided into 16 equal parts.

In order to realize the above dividing method, N
Table 1 (FIG. 4) and Table 2
It is necessary to amplify the number of bits as shown in FIG. 2 (FIG. 25).

First, the area between V _{0 and} V ₁ is divided into 32 equal parts, and V _1-
V ₂ between the 32 equal division, V ₂ -V ₃ between the 32 equal division, V ₃
-V ₄ During the 32 equal division, V ₄ -V ₅ between the 32 equal division, V
₅ -V ₆ between the 32 equal division between V ₆ -V ₇ 32 equal division,
Table 7 (FIG. 10) shows the case of dividing 32 equally between V _{7 and} V ₈ .
To Table 14 (FIG. 17).

Table 7 (FIG. 10) is a table showing a conversion method from 8 bits to 9 bits when dividing between V _{0 and} V ₁ into 32 equal parts. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 3 bits of the input 8 bits, and are used as they are for the upper 4 bits of the lower 6 bits.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. This 32
In the case of equal division, the lower 1 bit of the lower 6 bits may be '0'. Therefore, the lower 5 bits of the input 8 bits are used as they are as the upper 5 bits of the lower 6 bits, and
'0' is added to the bit and input to the digital / analog conversion circuit 5.

The same applies to Tables 8 to 14, where V ₁ -V
Between ₂ between, V ₂ -V _3, between V ₃ -V _4, V ₄ -V between _5, V
Between ₅ -V _6, between V ₆ -V _7, shows a method of 8 bits → 9 bit conversion when dividing between V ₇ -V ₈ 32 like.

Next, the interval between V _{0 and} V ₁ is divided into 16 equal parts, and V _1-
V ₂ between the 16 equal division, V ₂ -V ₃ between the 32 equal division, V ₃
-V ₄ During the 64 equal division, V ₄ -V ₅ between the 64 equal division, V
₅ -V ₆ between the 32 equal division between V ₆ -V ₇ 16 equal division,
The case of dividing into 16 equal parts between V _{7 and} V ₈ will be described.
In this case, as described above, conversion is performed as shown in Table 1 (FIG. 4) to Table 6 (FIG. 9).

Next, the interval between V _{0 and} V ₁ is divided into 16 equal parts, and V _1-
V ₂ between the 32 equal division, V ₂ -V ₃ between the 32 equal division, V ₃
-V ₄ During the 64 equal division, V ₄ -V ₅ between the 32 equal division, V
₅ -V ₆ between the 32 equal division between V ₆ -V ₇ 32 equal division,
The case of dividing into 16 equal parts between V _{7 and} V ₈ will be described.
Table 15 (FIG. 18) is a table showing a conversion method from 8 bits to 9 bits when dividing between V _{0 and} V ₁ into 16 equal parts.
First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When the upper 4 bits are “0000”, “000” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 16 equal divisions, the lower 2 bits of the lower 6 bits may be '00'. Therefore, the lower 4 bits of the input 8 bits are used as they are as the upper 4 bits of the lower 6 bits, and “00” is added to the lower 2 bits and input to the digital / analog conversion circuit 4.

Table 16 (FIG. 19) shows that 32 between V _{1 and} V ₂
9 is a table showing a conversion method from 8 bits to 9 bits in the case of equal division. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When the upper 4 bits are '0001' and '00'
In the case of “10”, “001” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In this case, the 32 equal divisions first refer to 8-bit data obtained by subtracting 16 from the input 8-bit data. For example, when the input data is “00100110” of the 38th gradation, 16 is subtracted from the data and converted to “00010110”. After conversion, the lower 5 bits are used as they are for the upper 5 bits of the lower 6 bits, and
0 ′ is added and input to the digital / analog conversion circuit 5.

Table 17 (FIG. 20) shows that the interval between V _{2 and} V ₃ is 32
9 is a table showing a conversion method from 8 bits to 9 bits in the case of equal division. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When upper 4 bits are '0011' and '01'
In the case of “00”, “010” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In this case, the equal division into 32 is similarly performed by dividing the input 8-bit data into 16 bits.
Refer to the 8-bit data obtained by subtracting. After the conversion, the lower 5 bits are used as they are for the upper 5 bits of the lower 6 bits, and “0” is added to the lower 1 bit, which is input to the digital / analog conversion circuit 5.

Tables 18A (FIG. 21 (a)) and 18B (FIG. 21 (b)) are tables showing the conversion method from 8 bits to 9 bits when dividing between V _{2 and} V ₃ into 64 equal parts. . First,
Upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. Top 4
Bit is' 0101 ',' 0110 ',' 011
1 ',' 1000 ', the multiplexer circuit 4
Enter '011' in the field.

Next, a method for generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In this case, the 64 equal divisions are similarly performed by dividing the input 8-bit data into 16
Refer to the 8-bit data obtained by subtracting. Then, after the conversion, the lower 6 bits are directly input to the digital / analog conversion circuit 5.

Table 19 (FIG. 22) shows that the interval between V _{4 and} V ₅ is 32
9 is a table showing a conversion method from 8 bits to 9 bits in the case of equal division. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When the upper 4 bits are '1001' and '10
In the case of “10”, “100” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits for input to the digital / analog conversion circuit 5 will be described. In this case, the equal division into 32 refers to 8-bit data obtained by subtracting 16 from the input 8-bit data, as before. Then, after the conversion, the lower 5 bits are used as they are as the upper 5 bits of the lower 6 bits, and “0” is added to the lower 1 bit, which is input to the digital / analog conversion circuit 5.

Table 20 (FIG. 23) shows that 32 between V _{5 and} V ₆
9 is a table showing a conversion method from 8 bits to 9 bits in the case of equal division. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When upper 4 bits are '1011' and '11
In the case of “00”, “101” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In this case, the equal division into 32 is similarly performed by dividing the input 8-bit data into 16 bits.
Refer to the 8-bit data obtained by subtracting. Then, after the conversion, the lower 5 bits are used as they are as the upper 5 bits of the lower 6 bits, and “0” is added to the lower 1 bit, which is input to the digital / analog conversion circuit 5.

Table 21 (FIG. 24) shows that 32 between V _{6 and} V ₇
9 is a table showing a conversion method from 8 bits to 9 bits in the case of equal division. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When upper 4 bits are '1101' and '11
In the case of "10", "110" is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In this case, the equal division into 32 is similarly performed by dividing the input 8-bit data into 16 bits.
Refer to the 8-bit data obtained by subtracting. Then, after the conversion, the lower 5 bits are used as they are as the upper 5 bits of the lower 6 bits, and “0” is added to the lower 1 bit, which is input to the digital / analog conversion circuit 5.

Table 22 (FIG. 25) shows that 16 between V _{7 and} V ₈
9 is a table showing a conversion method from 8 bits to 9 bits in the case of equal division. First, the upper 3 bits to be input to the multiplexer circuit 4 are determined from the upper 4 bits of the input 8 bits. When the upper 4 bits are “1111”, “111” is input to the multiplexer circuit 4.

Next, a method of generating the lower 6 bits to be input to the digital / analog conversion circuit 5 will be described. In the case of 16 equal divisions, the lower 2 bits of the lower 6 bits may be '00'. Therefore, the lower 4 bits of the input 8 bits are used as they are as the upper 4 bits of the lower 6 bits, and “00” is added to the lower 2 bits and input to the digital / analog conversion circuit 5.

This embodiment has the effect that the division method can be switched by using a plurality of N-bit / F-bit conversion circuits as described above.

[0065]

As described above, according to the present invention,
The maximum γ correction voltage is increased by increasing the number of bits internally for the C-DAC that could be equally divided into the same number regardless of the size of the γ correction voltage between the two γ correction voltages.
The total number of divisions between the voltage and the minimum γ correction voltage is the same as before.
The number of equal divisions between each gamma correction voltage,
For example, a certain two γ correction voltages are equally divided into eight, and another two
The gamma correction voltage is divided into 16 equal parts, and another two gamma corrections are performed.
As such the voltage between the splits 32 and the like, and variable in accordance with the magnitude of the γ correction voltage, yet the maximum equal number of divisions conventional
We can make it bigger. Thus, the present invention
According to this, the output voltage of the C-DAC can be made closer to the ideal γ curve of the liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal drive circuit according to a first embodiment.

FIG. 2 is a block diagram showing a case where display data is 8 bits in the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a liquid crystal drive circuit according to a second embodiment.

FIG. 4 is a diagram showing an equal division between V _{0 and} V _{1 in} FIG.
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when _1- V ₂ is divided into 16 equal parts.

FIG. 5 is a diagram showing a conversion table of 8 bits → 9 bits in a case where the area between V _{2 and} V ₃ is divided into 32 equal parts, corresponding to FIG. 2;

FIG. 6 is a diagram showing a conversion table of 8 bits → 9 bits in a case where the space between V _{3 and} V ₄ is divided into 64 equal parts, corresponding to FIG. 2;

FIG. 7 is a diagram showing an 8-bit → 9-bit conversion table in the case where the space between V _{4 and} V ₅ corresponding to FIG. 2 is divided into 64 equal parts.

8 is a diagram showing a conversion table from 8 bits to 9 bits in a case where the space between V _{5 and} V ₆ corresponding to FIG. 2 is divided into 32 equal parts.

FIG. 9 is a diagram showing an equal division between V _{6 and} V ₇ corresponding to FIG.
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 16 equal parts.

FIG. 10 is a diagram showing a conversion table from 8 bits to 9 bits when dividing between V _{0 and} V ₁ into 32 equal parts.

FIG. 11: V ₁ -V ₂ , V ₂ -V ₃ , V ₃ -V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 12: V ₁ -V ₂ , V ₂ -V ₃ , V ₃ -V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 13: V ₁ -V ₂ , V ₂ -V ₃ , V ₃ -V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 14: V ₁ -V ₂ , V ₂ -V ₃ , V ₃ -V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 15: V ₁ -V ₂ , V ₂ -V ₃ , V ₃ -V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 16: Between V _{1 and} V _2, between V _{2 and} V ₃ , V _{3 and} V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 17: V ₁ -V ₂ , V ₂ -V ₃ , V ₃ -V
Between _4, between V ₄ -V _5, between V ₅ -V _6, between V ₆ -V _7, V
FIG. 9 is a diagram showing a conversion table of 8 bits → 9 bits when dividing between _{7 and} V ₈ into 32 equal parts.

FIG. 18 is a diagram showing an 8-bit → 9-bit conversion table in the case of dividing 16 between V _{0 and} V ₁ equally.

FIG. 19 is a diagram showing a conversion table from 8 bits to 9 bits when dividing between V _{1 and} V ₂ into 32 equal parts.

FIG. 20 is a diagram showing an 8-bit → 9-bit conversion table in a case where the space between V _{2 and} V ₃ is divided into 32 equal parts.

FIG. 21 is a diagram showing an 8-bit → 9-bit conversion table in the case where the space between V _{2 and} V ₃ is divided into 64 equal parts.

FIG. 22 is a diagram showing a conversion table from 8 bits to 9 bits when dividing between V _{4 and} V ₅ into 32 equal parts.

FIG. 23 is a diagram showing a conversion table from 8 bits to 9 bits in a case where the space between V _{5 and} V ₆ is divided into 32 equal parts.

FIG. 24 is a diagram showing a conversion table from 8 bits to 9 bits in a case where the space between V _{6 and} V ₇ is divided into 32 equal parts.

FIG. 25 is a diagram showing an 8-bit → 9-bit conversion table in a case where the space between V _{7 and} V ₈ is divided into 16 equal parts.

FIG. 26 is a block diagram illustrating a general configuration of a liquid crystal drive circuit.

FIG. 27 is a block diagram illustrating a configuration of an R-DAC type liquid crystal driving circuit.

FIG. 28 is a block diagram showing a configuration of a conventional C-DAC type liquid crystal driving circuit.

FIG. 29 is a diagram showing a detailed circuit diagram of a C-DAC.

[Explanation of symbols]

 Reference Signs List 1 data buffer circuit 2 bit conversion circuit 3 latch circuit 4 multiplexer circuit 5 control circuit 6 digital / analog conversion circuit 10 liquid crystal drive circuit 20 bit conversion circuit 70 data buffer circuit 80 latch circuit 81 latch group 90 digital / analog conversion circuit 90C, 90R DAC 91 resistor 92 switch group 93,95 operational amplifier 94 capacitance group 96 multiplexer circuit 97 gamma correction voltage value 98 control circuit 100 liquid crystal drive circuit 200 liquid crystal display panel

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H03M 1/74 H03M 1/74

Claims (5)

(57) [Claims] 1. A high-order P of N-bit input data to be displayed, comprising a capacitance array type digital / analog conversion circuit.
Based on the bits, two voltages adjacent to each other are selected from a plurality of gamma correction voltages input from the outside, and the digital / gamma correction voltage is selected between the two selected gamma correction voltages.
The analog conversion circuit equally divides the input data to be displayed into a number corresponding to the remaining lower bits, thereby obtaining the maximum γ correction voltage.
And by dividing between the the 2 ^N of the minimum γ correction voltage to generate ^the 2 ^N of the voltage from the input data of the N bits, in the liquid crystal driving circuit for outputting one of them as the liquid crystal drive voltage The number of bits of the input data to be displayed is greater than N,
F bit after bit number amplification by bit number amplification
The plurality of γ correction voltages by the upper P bits of the data
Specify two adjacent gamma correction voltages selected from
And the remaining lower FP bits of the F bit data
Is selected by the digital-to-analog conversion circuit.
Between the two γ-correction voltages into 2 ^FP at most
Between the two adjacent gamma correction voltages
The input data is visualized so that the total number of equal divisions is 2 ^N.
Provided bit conversion circuit for Wattage amplification, total number of divisions between the maximum of γ correction voltage and the minimum of γ correction voltage
While maintaining 2 ^N , the maximum between two adjacent gamma correction voltages
Large equal number of partitions can be made to 2 ^FP larger than 2 ^NP
Liquid crystal drive circuit, characterized in that the. 2. An N-bit input terminal and an N-bit output terminal, wherein N-bit input data to be displayed input to the input terminal is transmitted to a next-stage circuit connected to the output terminal. An N-bit data buffer circuit to be transferred; an N-bit input terminal and an F-bit output terminal; connected to an output terminal of the data buffer circuit; A bit conversion circuit for amplifying the number of bits to F bits greater than N, an F-bit input terminal and an F-bit output terminal, and connected to an output terminal of the bit conversion circuit; A data latch circuit for holding F-bit data output from the conversion circuit, and an external gamma correction for outputting upper P-bit data of output bits of the data latch circuit and a plurality of gamma correction voltages A plurality of γ-correction voltages output from the γ-correction power supply device and having two voltage values adjacent to each other, with reference to the upper P-bit data transferred from the data latch circuit. A multiplexer circuit for selecting and transferring the selected analog voltage to the next stage; two analog voltage signals output from the multiplexer circuit; and lower-order G-bit data (F-bit output from the data latch circuit) G = FP), the two analog voltage signals output from the multiplexer circuit are equally divided, and the input data is calculated from the equally divided voltage values based on the input data from the data latch circuit. and it outputs the liquid crystal drive voltage value corresponding to, provided a digital-analog converter circuit G bit capacitance array, the configuration of the bit conversion circuit Is the F bit after amplification of the number of bits.
The multiplex based on the upper P bits of the
A plurality of adjacent gamma correction voltages from each other
Select two γ correction voltages, and select the F bit data
Based on the remaining lower FP bits of
The two γ correction voltages selected by the analog conversion circuit
Is divided equally into a maximum of 2 ^FP , and next to each
Equal division number of the sum between two γ correction voltages I and 2 ^N fit
So that the number of bits of the input data is amplified.
Te, total number of divisions between the maximum of γ correction voltage and the minimum of γ correction voltage
While maintaining 2 ^N , the maximum between two adjacent gamma correction voltages
As may make equal division number of large to atmospheric made 2 ^FP than 2 ^NP
The liquid crystal driver circuit which is to. 3. The liquid crystal drive circuit according to claim 1, wherein the number of divisions between the two selected γ correction voltages can be selected according to the value of the γ correction voltage to be divided. A liquid crystal driving circuit characterized by the above. 4. The liquid crystal drive circuit according to claim 2, wherein a plurality of bit conversion circuits having different output data formats are provided in parallel between the data buffer circuit and the latch circuit, and an external signal is provided. Means for selecting one of the plurality of bit conversion circuits and connecting the data conversion circuit to the data buffer circuit and the latch circuit, so that the data format input to the latch circuit can be selected from a plurality of types. Liquid crystal drive circuit. 5. The liquid crystal drive circuit according to claim 1, wherein output polarities are alternately variable.