JP3230106B2 - Gain fluctuation compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing a baseband delay detection circuit for a QPSK signal or the like, and more particularly to a circuit for compensating for a gain fluctuation occurring in an analog circuit.

[0002]

2. Description of the Related Art A demodulator for a QPSK or 16QAM signal is:
As shown in FIG. 1, the input signal 1 and a carrier 5 synchronized with the center frequency of the input signal are subjected to complex multiplication in a quadrature phase detector 4 and harmonic components and noise are removed by a low-pass filter 6 to obtain an amplitude level. The signal is input to the discriminator (A / D converter) 8 through the adjustment amplifier 7 to obtain discrimination reproduction signals 2, 2 '. However, since 4, 6, and 7 are generally constituted by analog active elements, gain fluctuations occur due to changes in ambient temperature and aging, and imbalance occurs in the levels of the I and Q channels, thereby deteriorating demodulation characteristics. .

In order to solve this problem, conventionally, as shown in FIG. 1 (Japanese Patent No. 1506432 "multi-value discriminator")
An exclusive OR 9 output of the identification signal 2 and the error signal 3 obtained from the / D converter is integrated by a low-pass filter of 10, and
Feedback was applied to the amplifier immediately before the A / D converter to keep the I and Q channel signals at a desired level. The basic principle of this circuit, if demodulation operation to take the exclusive OR of 2 is larger than 1 gain for any quadrant of the signal for the linear positive, and negative if than one small Utilize becoming.

However, the conventional method cannot be applied to the case where nonlinear calculation is performed after the occurrence of gain fluctuation as in baseband differential detection. As an example, π
Consider / 4-QPSK differential detection. FIG. 2 shows the configuration of the present invention. However, except for the hatched parts 13 and 14, it is a normal baseband differential detection circuit. The number assigned to each block is common to FIG. First, when there is no gain fluctuation, the sample value of the output of the A / D converter (x
_k , y _k ) and differential detection output U _k ( _{uk x} , u _ky )
When plotted on the Y plane, FIGS. 6A and 6B respectively show
The signal is as follows. Next, if the I, the gain of the Q channel becomes respectively 0.9,1.2 by the gain variation, (x _k, y _k) and _{U k (u kx, u ky} ) each view 7 (a) , (B). As is clear from FIG. 2B, the error signal does not show a fixed polarity for the signal demodulated in a certain quadrant, so that the conventional circuit configuration cannot compensate for the level fluctuation.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to correctly estimate gain fluctuation even when nonlinear operation by differential detection is present, and to reduce deterioration. It is an object of the present invention to obtain a demodulated signal that does not exist and to provide a means realized by digital signal processing in order to ensure the stability of operation.

[0006]

A feature of the present invention to achieve the above object is that a received signal is subjected to complex product detection by a local oscillator having a frequency substantially equal to its center frequency, and a harmonic component is detected by a low-pass filter. And A / D conversion of an in-phase (I) / quadrature (Q) component obtained by removing noise and a complex multiplication of a complex sample value of one symbol, the A / D converter It has a gain compensation circuit composed of a gain compensation circuit for independently weighting the I and Q components of the output by a predetermined amount, and a weight estimation circuit for estimating a predetermined amount to be weighted. Q For both channels, add the variation obtained from the weight estimation circuit to the normal gain 1 to obtain a new gain,
The first weight estimating circuit estimates an I-channel weighting coefficient, and outputs an I-channel error signal output from the differential detection circuit;
A signal obtained by multiplying an I-channel output signal of the gain compensation circuit and a signal obtained by delaying the I-channel output signal by one symbol and integrating a signal obtained by scaling the output by a small coefficient is used as an I-channel weighting coefficient estimation amount. The weight estimating circuit estimates a Q-channel weighting coefficient, multiplies the Q-channel output signal of the differential detection circuit by a Q-channel error signal, integrates a signal obtained by scaling the output by the small coefficient, and integrates the Q-channel output signal. It is in a gain fluctuation compensating circuit as a weight coefficient estimation amount.

Another feature of the present invention is that a received signal is subjected to complex product detection by a local oscillator having a frequency substantially equal to its center frequency, and the in-phase (I) obtained by removing a harmonic component and noise by a low-pass filter. A) A / D conversion of the quadrature (Q) component, followed by complex multiplication of a complex sample value for one symbol by a baseband differential detection circuit, in which the I and Q components of the A / D converter output are independently predetermined. A gain compensating circuit comprising a gain compensating circuit for weighting only the amount of
The gain compensating circuit adds a variation obtained from the weight estimating circuit to the normal gain 1 to obtain a new gain, and the weight estimating circuit is obtained from the I-channel output signal of the differential detection circuit and the identification result thereof. Using the error signal as a common input signal, a signal obtained by delaying the I and Q components of the output of the A / D converter by one symbol and a gain compensation circuit output signal corresponding to the I and Q channels is multiplied. Multiply by the signal
A signal obtained by integrating a signal obtained by scaling the output by a small coefficient is used as a gain fluctuation compensating circuit for estimating a gain fluctuation amount of each of the I and Q channels.

[0008]

[Embodiment 1] A complex envelope of a QPSK reception signal is shown.

[0009]

(Equation 1)

It is assumed that: Here, h (t) is the impulse response of the transmission path, φ _k is the phase angle differentially encoded,
φ _k = φ _k−1 + m _k π / 2 + θ (m _k = 0,1,2,2
3). Θ is 0 in the case of QPSK, π / 4-Q
In the case of PSK, it becomes π / 4. Assuming that the gains of the I and Q channels of the demodulator are dgx and dgy, respectively, time t = k
The demodulated signal R _{k at} T is given by:

[0011] _{R k = dgx · cosφ k +} jdgy · sinφ k = x k + jy k (2)

For example, when the π / 4-QPSK demodulated signal is
When expressed on the Y plane, there is no gain change and dgx = dgy =
In the case of 1, as shown in FIG. 6A, if there is a gain fluctuation, the result is as shown in FIG. 7A. Then, I, when performing differential detection after performing weighting of each _{1 + w x, 1 + w} y in the Q channel,

Z _k = (1 + w _x ) x _k + j (1 + w _y )
from _{y k, U k = Z k} · Z * k-1 = {(1 + w x) 2 x k x k-1 + (1 + w y) 2 y k y k-1} + j (1 + w x) (1 + w y) _{(y k x k-1 -x} k y k-1) (3)

Is obtained. The identification signal is _represented by D _k = d _k , _x + j
Let d _{k, y} be the error signals of the I and Q channels respectively e
_{If k, x} and e _{k, y} ,

E _{k, x} = d _{k, x} − (1 + w _x ) ² x _k x _k−1 − (1 + w _y ) ² y _k y _k−1 (4) e _{k, y} = d _{k, y} − ( _{1 + w x) (1 +} w y) (x k-1 y k -x k y k-1) and made (5).

In order to estimate the weight coefficient so as to minimize the root mean square of the error, w _x is calculated from the square of the instantaneous error in the equation (4).
What is necessary is just to obtain the inclination with respect to and sequentially control in the opposite direction. Therefore,

[0017]

(Equation 2)

## EQU1 ## Here, μ is a minute coefficient called a step size parameter. Also, the error e
_{k, x} and the weighting factor w _x does not affect the correction of w _x be multiplied right paragraph 2 a (1 + w _x) of formula (6) since it is uncorrelated. Therefore, the correction of w _x is performed by the following equation.

W _x ← w _x + μe _{k, x} (1 + w _x ) x _k (1 + w _x ) x _k−1 (6 ′)

Accordingly, w _x can be corrected from the I-channel output signal of the gain compensation circuit and the I-channel error signal of the delay detection output.

Next, from equation (5)

(Equation 3)

## EQU2 ## The weighting coefficient of the Q channel is modified by the following equation.

W _y ← w _y + μe _{k, y} (1 + w _x ) (y _k x _k−1 −x _k y _k−1 ) (7)

Here, as in the case of the I channel, e _{k, y}
And using the decorrelation of w _y

W _y ← w _y + μe _{k, y} (1 + w _x ) (1 + w _y ) (y _k x _k−1 −x _k y _k−1 ) (7 ′)

Is transformed. Therefore, w _y can be modified by the product of the Q channel output and the Q-channel error signal delay detection circuit.

Note that since the rate of change of the gain variation due to the ambient temperature or aging is small, μ may be as large as the quantization noise of the A / D converter.

FIG. 2 shows the configuration of the present invention by taking a π / 4-QPSK demodulator as an example, and becomes an ordinary baseband differential detection circuit except for the hatched portion. First, π /
The 4-QPSK input signal 1 is subjected to quadrature phase detection by an oscillator 5 having a frequency substantially equal to the center frequency (4). After passing through a low-pass filter 6 for removing harmonic components and noise, an amplifier 7 optimizes the amplitude level. The signal is adjusted and converted into a digital signal by the A / D converter 8. Next, based on the gain fluctuation values w _x and w _y estimated by the weight estimating circuit 14, the signals x _k and y _k of the I and Q channels are multiplied by (1 + w _x ) and (1 + w _y ) in the gain compensating circuit 13, respectively. Thus, the gain fluctuation is compensated. Reference numeral 15 denotes a four-phase delay detection circuit for demodulating a transmission signal. Identifier 16 may simply select the MSB signal of the signal U _k demodulated outputs as 2,2 '.

FIG. 3 shows a specific example of the gain compensating circuit 13. The gains w _x and w _y are added to the normal gain 1 (22), and the demodulated signals x _k and y of the I and Q channels are added.
Multiply _k by (21).

FIG. 4 shows a specific example of a four-phase differential detection circuit.
Complex conjugate signal Z delayed by one symbol from input complex signal Z _k
^* Multiplication with _k-1 is performed.

[0031] Figure 5 is a specific example of the weight estimation circuit, FIG. (A) is a circuit configuration for obtaining a weighting factor w _x. The input signal of this circuit is the I-channel output x 'of the gain compensation circuit 13.
_k and the I-channel error signal e obtained from the subtraction circuit 12
_{k, x} . The operation of the w _x estimating circuit is to multiply x _k and a signal obtained by delaying x _k by one symbol _, and multiply the result by e _{k, x} . The result is further multiplied by a step size parameter μ, and the result is added to the adder 22 and the one-symbol delay circuit 2.
3 and output.

[0032] FIG. (B) is a circuit configuration for obtaining a weighting factor w _y. The input signals of this circuit are the Q-channel output u _{k, y} of the delay detection circuit 15 and the Q-channel error signal e _{k, y} obtained from the subtraction circuit 12. The operation of the w _y estimation circuit is u
_{k, y} is multiplied by e _{k, y} and the step size parameter μ
, And the result is integrated and output by the adder 22 and the one-symbol delay circuit 23.

Here, it is clear that in the circuit for obtaining w _x , the I-channel error signal _{ek, x} obtained from the subtraction circuit 12 may be replaced by its polarity signal. Also, w
Obviously, u _{k, y} and e _{k, y} may be replaced by their polarity signals in the circuit for obtaining _{y, in} which case the multiplier can be replaced by an exclusive OR.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.

The complex envelope of the received QPSK signal is

(Equation 4)

It is assumed that Here, h (t) is the impulse response of the transmission path, φ _k is the phase angle differentially encoded,
φ _k = φ _k−1 + m _k π / 2 + θ (m _k = 0,1,2,2
3). Θ is 0 in the case of QPSK, π / 4-Q
In the case of PSK, it becomes π / 4. Assuming that the gains of the I and Q channels of the demodulator are dgx and dgy, respectively, time t = k
The demodulated signal R _{k at} T is given by:

[0037] _{R k = dgx · cosφ k +} jdgy · sinφ k = x k + jy k (12)

For example, the π / 4-QPSK demodulated signal is
When expressed on the Y plane, there is no gain change and dgx = dgy =
In the case of 1, as shown in FIG. 6A, when there is a gain fluctuation, the result becomes as shown in FIG. 6B. Then, I, when performing differential detection after performing weighting of each _{1 + w x, 1 + w} y in the Q channel,

Z _k = (1 + w _x ) x _k + j (1 + w _y )
from _{y k, U k = Z k} · Z * k-1 = {(1 + w x) 2 x k x k-1 + (1 + w y) 2 y k y k-1} + j (1 + w x) (1 + w y) _{(y k X k-1 -x} k y k-1) (13)

Is obtained. The identification signal is _represented by D _k = d _k , _x + j
Assuming that d _{k, y} and the error signal of the I channel is e _{k, x} ,

E _{k, x} = d _{k, x} − (1 + w _x ) ² x _k x _k−1 − (1 + w _y ) ² y _k y _k−1 (14)

In order to estimate the weight coefficient so as to minimize the mean square of the error, it is necessary to calculate w
_x, it may be sequentially controlled in the direction opposite to that seeking inclined about w _y. Therefore,

[0043]

(Equation 5)

Is obtained. Here, μ is a minute coefficient called a step size parameter, and is a minute value arbitrarily given.

From Equations (15) and (16), the estimated value of the weighting coefficient is given by the product of the demodulated signal having undergone gain fluctuation, the output of the gain compensation circuit, and the I-channel error signal. Further, since the rate of change of the gain variation due to the ambient temperature and the deterioration with time is small, μ may be as large as the quantization noise of the A / D converter.

FIG. 2 shows a configuration of the present invention by taking a π / 4-QPSK demodulator as an example, and becomes an ordinary baseband differential detection circuit except for hatched portions. First, π /
The 4-QPSK input signal 1 is subjected to quadrature phase detection by an oscillator 5 having a frequency substantially equal to the center frequency. After passing through a low-pass filter 6 for removing harmonic components and noise, the amplitude level is adjusted optimally by an amplifier 7 and A The signal is converted into a digital signal by the / D converter 8. Next, based on the gain fluctuation values w _x and w _y estimated by the weight estimating circuit 14, the signals x _k and y _k of the I and Q channels are multiplied by (1 + w _x ) and (1 + w _y ) in the gain compensating circuit 13, respectively. Thus, the gain fluctuation is compensated. Reference numeral 15 denotes a four-phase delay detection circuit for demodulating a transmission signal. Identifier 16 may simply select the MSB signal of the signal U _k demodulated outputs as 2,2 '.

As the gain compensation circuit and the four-phase delay detection circuit, the same circuits as those in the first embodiment are used.

FIG. 9 shows a specific example of the weight estimating circuit. The circuit configuration for obtaining the estimated values w _x and w _y is the same. The input signals of this circuit are the I-channel error signals _{ek, x} obtained from the subtraction circuit 12, and the output signals of 8 and 13. The operation of the w _x estimation circuit is as follows. First, after delaying x _k by one symbol, (1+
w _k ) x _k and the result is multiplied with e _{k, x} . Further, the result is multiplied by a step size parameter μ, and the result is integrated by an adder 22 and a one-symbol delay circuit 23 and output.

In the second embodiment, since the gain compensation circuit is connected to many circuits such as the output of the A / D converter and the output of the discriminator, a connection problem may occur. In the example there is no such problem.

[0050]

FIGS. 7 (b) and 7 (c) show demodulated signals with and without the gain fluctuation compensating circuit. It can be seen that the demodulated signal is obtained at the correct position by compensation.
The effect of the present invention is great in a situation where a mobile wireless terminal used outdoors such as mobile communication has a severe use environment such as an ambient temperature and the like, and the characteristic degradation due to the gain variation of the analog active circuit cannot be avoided.

[Brief description of the drawings]

FIG. 1 shows a gain fluctuation compensation circuit used in a linear demodulator.

FIG. 2 is a block diagram when applied to a π / 4-QPSK demodulator in an embodiment of the present invention.

FIG. 3 is a specific example of the gain compensation circuit shown in FIG. 2;

FIG. 4 is also a specific example of the differential detection circuit 15 shown in FIG.

5 is a specific example of the weight estimation circuit 14 shown in FIG. 2; FIG. 5A shows a circuit configuration for an I channel, and FIG. 5B shows a circuit configuration for a Q channel;

FIGS. 6A and 6B are signal space diagrams of a π / 4-QPSK demodulated signal when there is no gain fluctuation, wherein FIG. 6A shows an output of an A / D converter and FIG. 6B shows an output of a differential detector.

FIG. 7 shows an example in which a gain fluctuation (I channel is 0.9 times and Q channel is 1.2 times) is present.
The converter output, (b) shows the delay detection output, and (c) shows the delay detection output when a gain fluctuation compensation circuit is added.

FIG. 8 is a block diagram of another embodiment of the present invention.

9 shows a weight estimation circuit in the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal input terminal 2, 2 'I, Q channel identification signal output terminal 3, 3' I, Q channel error signal output terminal 4 Quadrature phase detector 5 Local oscillator 6 Low pass filter 7 Amplifier 8 A / D conversion 9 Exclusive OR circuit 10 Loop filter 12 Subtractor 13 Gain compensation circuit 14 Weight estimation circuit 15 4-phase delay detection circuit 16 Discriminator 21 Multiplier 22 Adder or subtractor 23 1-symbol delay element

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-77457 (JP, A) JP-A-55-110460 (JP, A) JP-A-63-42255 (JP, A) JP-A-5-110 14213 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (3)

(57) [Claims] An in-phase (I) / quadrature (Q) signal obtained by performing complex product detection on a received signal with a local oscillator having a frequency substantially equal to its center frequency and removing a harmonic component and noise by a low-pass filter. In a baseband differential detection circuit that A / D-converts the components and then multiplies the complex sample value of one symbol by complex, a gain for independently weighting the I and Q components of the A / D converter by a predetermined amount. A gain variation compensating circuit comprising a compensation circuit and a weight estimating circuit estimating a predetermined amount to be weighted, wherein the gain compensating circuit has a normal gain of 1 for both I and Q channels, and a variation obtained from the weight estimating circuit. Is added to obtain a new gain. The first weight estimating circuit estimates a channel weighting coefficient. The I-channel error signal output from the differential detection circuit and the I- A signal obtained by multiplying a channel output signal and a signal obtained by delaying the output signal by one symbol is integrated, and a signal obtained by scaling the output by a small coefficient is integrated to obtain an I-channel weight coefficient estimation amount. And a Q-channel output signal of the differential detection circuit is multiplied by a Q-channel error signal, and an output signal obtained by scaling the output with the small coefficient is integrated to obtain a Q-channel weight coefficient estimation amount. A gain fluctuation compensation circuit. 2. The configuration of the weight estimating circuit according to claim 1, wherein the first weight estimating circuit converts the I-channel error signal into its polarity signal and multiplies it, and the second weight estimating circuit comprises A gain fluctuation compensation circuit, characterized in that one or both of a Q-channel output signal and a Q-channel error signal of a differential detection circuit are converted into a polarity signal and multiplied. 3. An in-phase (I) / quadrature (Q) signal obtained by performing complex product detection on a received signal with a local oscillator having a frequency substantially equal to its center frequency and removing a harmonic component and noise by a low-pass filter. In a baseband differential detection circuit that A / D-converts the components and then multiplies the complex sample value of one symbol by complex, a gain for independently weighting the I and Q components of the A / D converter by a predetermined amount. A gain fluctuation compensating circuit comprising a compensation circuit and a weight estimating circuit estimating a predetermined amount to be weighted, wherein the gain compensating circuit adds a fluctuation obtained from the weight estimating circuit to a normal gain of 1 to obtain a new gain. The weight estimation circuit uses the I-channel output signal of the differential detection circuit and an error signal obtained from the identification result as a common input signal, and uses the I and Q components of the output of the A / D converter as a common input signal. A signal delayed by one symbol is multiplied by an output signal of a gain compensation circuit corresponding to the I and Q channels, the result is further multiplied by the error signal, and a signal obtained by scaling the output by a small coefficient is integrated to obtain I and Q signals. A gain variation compensation circuit, wherein an estimated amount of gain variation of each of the two channels is used.