JP3227964B2 - Adaptive delta modem - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive delta modulator / demodulator for modulating an analog signal into a digital signal and demodulating the modulated digital signal into an analog signal.

[0002]

2. Description of the Related Art In recent years, an adaptive delta modulation / demodulation system has been used as a communication system.

Hereinafter, a conventional adaptive delta modulator / demodulator will be described with reference to the drawings. FIG. 2 is a block diagram showing a configuration of a conventional adaptive delta modulator / demodulator.

In FIG. 2, reference numeral 21 denotes a modulator for modulating an analog signal into a digital signal. A demodulator 31 demodulates the modulated digital signal into an analog signal. Reference numeral 2 denotes a comparator for comparing the output of a digital / analog converter (hereinafter referred to as a D / A converter) 7 with an analog input signal. Reference numeral 23 denotes a delta value increase / decrease determiner which determines the increase / decrease of the delta value based on a predetermined criterion. Numeral 4 denotes an up / down counter which increases or decreases according to the output from the delta value increase / decrease determiner 23. 2
Reference numeral 5 denotes a storage device in which a delta value is written using the output of the up / down counter 4 as an address. Reference numeral 6 denotes a cumulative adder / subtracter for cumulatively adding / subtracting a delta value output from the storage device 25. Reference numeral 7 denotes a D / A converter, which converts a digital signal into an analog signal.

The modulator 21 includes a comparator 2, a delta value increase / decrease determiner 23a, an up / down counter 4, and a storage device 2.
5, a cumulative adder / subtracter 6, and a D / A converter 7 are sequentially connected in a loop. The demodulator 31 includes a delta value increase / decrease determiner 23b, an up / down counter 4, a storage device 25, an accumulative adder / subtractor 6, and a D / A converter 7, which are sequentially connected. The delta value increase / decrease determiners 23a and 23b are also connected to the accumulators 6a and 6b, respectively.

The operation of the adaptive delta modulator / demodulator configured as described above will be described below.

First, the operation of the modulator 21 will be described. The analog input signal is input to the comparator 2 every sampling period, and the comparator 2 compares the output of the D / A converter 7 one sample before and the size of the analog input signal. If the result of the comparison is that the analog input signal is larger than the output of the D / A converter 7, the comparator 2 outputs an H-level signal (hereinafter, referred to as "1"). On the other hand, when the analog input signal is smaller than the output of the D / A converter 7,
Comparator 2 outputs an L-level signal (hereinafter, referred to as “0”). The signal of “1” or “0” is output from the comparator 2 as 1
As a digital modulation signal of bits, the signal is transferred to the delta value increase / decrease determiner 23b constituting the demodulator 31 by radio waves. Also,
"1" or "0" is also input from the comparator 2 to the delta value increase / decrease determiner 23a constituting the modulator 21, and the delta value increase / decrease determiner 23a determines whether the delta value is increased by the signal from the comparator 2. Whether to decrease is determined based on a determined criterion. "1" when increasing the delta value
When the signal is decreased, the signal of "0" is output from the delta value increase / decrease determiner 23a to the up / down counter 4. And the up / down counter 4
When the signal of "1" is input, the count number is increased,
When a signal of "0" is input, the count is decreased.
Subsequently, the storage device 25 reads the delta value corresponding to the output of the up / down counter 4. The storage device 25 stores a delta value determined according to a constant delta value increase / decrease rate according to the count number.

Then, the delta value obtained in the storage device 25 is added / subtracted by the accumulator 6a. The judgment result of the delta value increase / decrease judgment unit 23a is input to the accumulation adder / subtractor 6a. When the judgment result is "1", the addition is performed, and when the judgment result is "0", the addition is performed.

Subsequently, the digital signal resulting from the addition and subtraction by the accumulator 6a is converted into an analog signal by the D / A converter 7. The output of the D / A converter 7 is input to the comparator 2 and compared with an analog signal obtained by the next sampling.

[0010] By repeating the above operation, a 1-bit digital modulation signal is obtained from the modulator 21 every fixed sampling period.

Next, the operation of the demodulator 31 will be described. The digitally modulated signal from the modulator 21 is input as a radio signal to the delta value increase / decrease determiner 23b constituting the demodulator 31. In the demodulator 31, as in the modulator 21, the delta value increase / decrease determiner 23b determines the increase / decrease of the delta value, the up / down counter 4 increases or decreases the count, and the storage device 25.
Then, the accumulator 6b accumulates and subtracts the delta value, and the D / A converter 7 converts the digital signal resulting from the addition and subtraction by the accumulator 6b into an analog signal.
Then, the analog demodulated signal is output from the D / A converter 7 to the outside, and the demodulation operation is completed.

By repeating the above operation, the digital modulation signal from the modulator 21 is demodulated into an analog demodulation signal.
An analog input signal that is an original signal can be reproduced.

As described above, in the conventional adaptive delta modulator / demodulator, both the modulator 21 and the demodulator 31 determine the increase / decrease of the delta value based on the criterion determined by the delta value increase / decrease determiner 23.

Both storage devices 25a and 25b store only the delta value determined by one type of delta value increase / decrease rate.

[0015]

However, in the above-mentioned conventional adaptive delta modulator, the digital modulation signal transferred from the comparator 2 of the modulator 21 to the delta value increase / decrease determiner 23b of the demodulator 31 generally includes radio waves. Because it uses signals,
The longer the distance between the modulator 21 and the demodulator 31, the lower the sensitivity of the digital modulation signal input to the demodulator or the more the obstacle between the modulator 21 and the demodulator 31 will cause the demodulator to fail . Noise is generated in the input digital modulation signal (hereinafter, the state in which the sensitivity of the digital modulation signal is reduced or the noise is generated in the digital modulation signal is collectively referred to as a reduction in the level of the digital modulation signal). .
Therefore, when the level of the digital modulation signal decreases, a data transfer error occurs, and the reproduction level of the analog demodulated signal is reduced as compared with the analog input signal.

Further, by repeating the modulation / demodulation operation, the reproduction level of the analog demodulated signal to the analog input signal which is the original signal increases, but it takes time for the analog demodulated signal to approach the original signal. there were.

The present invention solves the above-mentioned problems, and can suppress a decrease in the reproduction level of an analog demodulated signal due to a data transmission error when the level of a digital modulation signal decreases. It is another object of the present invention to provide an adaptive delta modulator / demodulator that can reduce the time for reproducing an analog demodulated signal into an original signal.

[0018]

In order to achieve this object, an adaptive delta modulator / demodulator according to the present invention has a delta value increase / decrease determiner constituting a demodulator having a plurality of types of determination criteria. The communication signal level determiner selects a criterion in accordance with the signal level from, and the increase / decrease of the delta value is determined based on the criterion selected by the communication signal level determinator.

Further, the adaptive delta modulator / demodulator according to the present invention comprises:
A storage device that constitutes a demodulator stores a plurality of delta values determined by a plurality of delta value increase / decrease rates for one output of the up / down counter, and a communication signal level determiner outputs a signal from the modulator. The delta value increase / decrease rate is selected according to the level, and the storage device reads out the delta value of the delta value increase / decrease rate selected by the communication signal level determiner.

[0020]

According to the present invention, since the criterion is changed in accordance with the signal level from the modulator according to the signal level from the modulator, the optimum criterion can be selected from a plurality of criterions.

Further, since the delta value increase / decrease rate of the delta value is changed according to the signal level from the modulator according to the signal level from the modulator, an appropriate delta value is selected from a plurality of delta values determined by the delta value increase / decrease rate. A delta value determined by the rate of change can be selected.

[0022]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an adaptive delta modulator / demodulator according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a modulator for modulating an analog input signal into a digital modulation signal. 11
Is a demodulator which demodulates the modulated digital modulated signal into an analog demodulated signal. Reference numeral 2 denotes a comparator for comparing the output of the D / A converter 7 with the analog input signal for each sampling frequency. Reference numerals 3a and 3b denote delta value increase / decrease determiners which determine the delta value increase / decrease based on a predetermined criterion. The delta value increase / decrease determiner 3b has a plurality of criteria. Reference numeral 4 denotes an up / down counter, which increases or decreases according to the output of the delta value increase / decrease determiner 3. Reference numerals 5a and 5b denote storage devices in which the output of the up / down counter 4 is used as an address and a delta value is written in advance. Note that a plurality of delta values determined by a plurality of delta value increase / decrease rates are written in the storage device 5b for one output value of the up / down counter 4. Numeral 6 denotes a cumulative adder / subtracter for cumulatively adding or subtracting the delta value output from the storage device 5, and the increase / decrease is controlled by the output of the delta value increase / decrease determiner 3. Reference numeral 7 denotes a D / A converter, which converts a digital signal output from the accumulator 6 into an analog signal. Reference numeral 8 denotes a communication signal level determiner for controlling the criterion of the delta value increase / decrease determiner 3b and the delta value increase / decrease rate of the storage device 5b according to the digital modulation signal output from the comparator 2.

The modulator 1 includes a comparator 2, a delta value increase / decrease determiner 3a, an up / down counter 4, a storage device 5a, a cumulative adder / subtractor 6a, and a D / A converter 7, which are sequentially connected in a loop. Have been. Further, the delta value increase / decrease determiner 3a is connected to the accumulator 6a.

The demodulator 11 has a delta value increase / decrease determiner 3b,
An up / down counter 4, a storage device 5b, a cumulative adder / subtractor 6b, and a D / A converter 7 are sequentially connected. Further, the delta value increase / decrease determiner 3b is connected to the cumulative adder / subtractor 6b, and the communication signal level determiner 8 is connected to the delta value increase / decrease determiner 3b and the storage device 5b.

The operation of the adaptive delta modulator / demodulator configured as described above will be described below.

The comparator 2 constituting the modulator 1 outputs a digitally modulated signal to the outside as a radio signal. The demodulator 11 takes in the digitally modulated signal output to the outside to the delta value increase / decrease determiner 3b. Then, the demodulator 11 demodulates the digital modulation signal captured by the digital radio signal into an analog demodulation signal. By repeating such an operation, an analog input signal input to the modulator 1 can be transferred to the demodulator 11.

First, the operation of the modulator 1 will be described in detail. An analog input signal is input to the comparator 2 every sampling period, and the D / A of the
The output of the converter 7 and the magnitude of the analog input signal are compared.
If the result of the comparison is that the analog input signal is larger than the output of the D / A converter 7, the comparator 2 outputs a signal of "1". On the other hand, the analog input signal is D / A
If it is smaller than the output of the converter 7, the comparator 2 outputs a signal of "0". From the comparator 2, the signal of “1” or “0” is converted into a 1-bit digital modulation signal,
The signal is output to the outside of the modulator 1 as a radio signal. The comparator 2 also outputs “1” or “0” to the delta value increase / decrease determiner 3a.
And the delta value increase / decrease determiner 3a outputs the comparator 2
It is determined whether to increase, decrease, or hold the delta value according to a signal from the designated criterion. When the delta value increase / decrease determiner 3a determines that the delta value is "increased", it outputs "1", and when it determines that the delta value is "decreased", it outputs "0", and the delta value is "held as it is". No output is made when the judgment is made.

There are various criteria for determination. For example, when the output of the comparator 2 is a signal of “1” three times or more such as “1,1,1”, the delta value is increased or decreased. The determiner 3a outputs “1”, and the output of the comparator 2 is “0,
If the signal of "0" continues three times or more, such as "0,0", "0" is output. And other "1,0,
0 "," 1,0,1 "," 0,0,1 "," 0,1,
In the case of "1", there is a case where nothing is output.

When a signal of "1" is input to the up / down counter 4, the count number is increased,
When the signal of “0” is input, the count number is reduced. If nothing is entered, the current state is maintained.

Subsequently, the storage device 5 reads the delta value from the storage device 5 in accordance with the output of the up / down counter 4. The storage device 5 uses the output of the up / down counter 4 as an address, and stores, in each address, a delta value determined in advance according to a constant delta value increase / decrease rate.

As an example of the delta value increase / decrease rate, when the output of the up / down counter 4 increases to "1", "2", "3",..., The delta value output from the storage device 5 also becomes "1". Some increase as “1”, “2”, “3”,....
As another example, when the output of the up / down counter 4 increases to “1”, “2”, “3”,..., The delta values output from the storage device 5 are “1”, “4”, " 9 ",
... And increases in proportion to the square of the output of the up / down counter 4.

Subsequently, as in the prior art, the storage device 5a
Is added or subtracted by the accumulator 6a. The result of the determination by the delta value increase / decrease determiner 3a is input to the cumulative adder / subtractor 6a. When the output of the delta value increase / decrease determiner 3a is “1”, the cumulative adder / subtractor 6a adds the delta value and sets “0”. , The accumulator 6a subtracts the delta value.

Then, the digital signal as a result of the addition / subtraction of the accumulator 6a is converted into an analog signal by the D / A converter 7.

By repeating the above operation, a 1-bit digital modulation signal is obtained from the modulator 1 every fixed sampling period.

Next, the operation of the demodulator 11 will be described. The digital modulation signal output from the comparator 2 forming the modulator 1 is input as a radio signal to the delta value increase / decrease determiner 3b and the communication signal level determiner 8 forming the demodulator 11. The communication signal level determiner 8 determines the signal level of the digital modulation signal, and determines the delta value increase / decrease determiner 3b.
Specifies which criterion to select from among a plurality of criteria. At the same time, the storage device 5b specifies which delta value is to be adopted from among the delta values determined by the plurality of delta value increase / decrease rates.

The delta value increase / decrease determiner 3b determines increase / decrease of the delta value in the same manner as the modulator 1 based on the criterion specified by the communication signal level determiner 8. Subsequently, the up / down counter 4 determines to increase, decrease, or maintain the count number based on the output of the delta value increase / decrease determiner 3b. Then, the storage device 5b reads the delta value of the address specified by the up / down counter 4. The delta value read from the storage device 5b is in accordance with the delta value increase / decrease rate specified by the communication signal level determiner 8.

Then, the delta value read from the storage device 5b is cumulatively added or subtracted by the cumulative adder / subtractor 6b. Whether to add or subtract is controlled by the delta value increase / decrease determiner 3b. The accumulator 6b has a delta value increase / decrease
The judgment result of the integrator 3b is input, and the delta value increase / decrease
When the output of the integrator 3b is "1", the accumulator 6b
Adds the delta value, and when it is "0", the accumulative adder / subtractor
6b subtracts the delta value. The D / A converter 7 converts the output of the accumulator 6b from a digital signal to an analog signal.

Next, the determination result of the communication signal level determiner 8
A method of controlling the delta value increase / decrease rate of the storage device 5b and the delta value increase / decrease determiner 3b that operates according to the following will be described in detail.

The communication signal level determiner 8 determines the level state of the digital modulation signal output from the comparator 2. Delta communication signal level determination unit 8, a digital modulated signal and sensitivity is poor state, If it is determined that the signal level reduction state is a state in which noise is generated, by strict criteria delta values decrease determination unit 3b Decrease value increase / decrease rate
I do. By doing so, a data transfer error can be reduced, and a decrease in the reproduction level of the analog demodulated signal can be suppressed.

When the communication signal level determiner 8 determines that the digitally modulated signal is in a low-level state, the storage device 5b can reduce the data transfer error by decreasing the delta value increase / decrease rate. .

On the other hand, when there is no noise or the like in the digital modulation signal and the communication signal voltage level is normal, it is not necessary to make the criterion of the delta value increase / decrease determiner 3b strict or reduce the delta value increase / decrease rate. If the criterion of the delta value increase / decrease determiner 3b is made stricter or the delta value increase / decrease rate is reduced, it takes time to demodulate the analog demodulated signal into the original analog input signal.
Then, when the communication signal level determiner 8 determines that the signal level of the digital modulation signal is in a good state, the communication signal level determiner 8 loosens the determination criterion of the delta value increase / decrease determiner 3b and the storage device 5b determines the delta determined by the large delta value increase / decrease rate. Control to select a value. By doing so, when the signal level of the digital modulation signal is in a good state, it is possible to shorten the time required for the analog demodulated signal to be demodulated into the original signal.

As described above, the signal level state of the digital modulation signal is determined by the communication signal level determiner 8, and based on the determination result, the delta value increase / decrease determiner 3b is set to an appropriate criterion, and the storage device 5b is set to an appropriate delta. Control the value increase / decrease rate.

Next, the criterion of the delta value increase / decrease determiner 3b will be described in detail. One example of the criterion of the delta value increase / decrease determiner 3b is, as described above, a determination using the three sampling outputs of the comparator 2.
When the output of the comparator 2 is "1,1,1" and "1" is output three or more times continuously, the output is "1", and the output of the comparator 2 is "0,0,0". "0" in the case of consecutive "0" is output more than once, in the case of the other and does not output anything
It is intended to refer. The delta value increase / decrease determiner 3b includes a comparator 2
Up cow which counts up when the output of "1" is
Counter when the output of comparator 2 is "0".
And a down counter that counts up.
Resets the down counter to count down
Reset the up counter. Therefore, continuously
Each counter is linked only when the same output is input.
Delta value increase / decrease judgment unit
3b output.

The adopted decision criteria that determine where using four sampling output. In this criterion,
When the output of the comparator 2 is "1,1,1,1" and "1" is output four or more times consecutively, the output is "1", and the output of the comparator 2 is "0,0,0,0". "Is output four times or more consecutively, and" 0 "is output. In other cases, no output is made. This is a criterion that is stricter than that using three sampling outputs. That is, greater the number of sampling outputs, criteria stricter Do Liddell
The rate of increase / decrease of the data value becomes smaller.

Next, the delta value increase / decrease rate for determining the delta value stored in the storage device 5b will be described in detail.

As described above, when the output of the up / down counter 4 increases to "1", "2", "3",... Similarly, the delta value output from 5b is "1", "2",
Some increase as “3”,. As a second example, the output of the up / down counter 4 is “1”,
When the number increases to "2", "3", ..., the delta value output from the storage device 5b is proportional to the square of the output of the up / down counter 4 as "1", "4", " 9 ", ... Some increase. In the above two examples, the increase rate of the delta value with respect to the increase of the up / down counter 4 is larger in the second example, so that the delta value change rate is larger.

As described above, according to the above-described embodiment, the delta value increase / decrease rate, the delta value increase / decrease determination criterion, and the delta value increase / decrease rate can be optimally changed according to the communication signal voltage level of the digital modulation signal. In addition, it is possible to reduce a data transmission error when the received signal level is lowered, and to shorten a demodulation time to an original signal.

The adaptive delta modulator / demodulator of the above embodiment is merely an example. In a modulator / demodulator that converts an analog input signal into a digital signal and demodulates the digital signal into an analog signal using the delta value, the delta value is increased or decreased. if a decision unit or storage device, it is apparent that the same effect can be obtained.

The criterion described in the above embodiment is merely an example, and is not limited thereto. It is apparent that the same effect can be obtained by employing other criterion. The same applies to the delta value change rate.

Further, in the above embodiment, the radio signal is used for transmitting the digital modulation signal from the modulator 1 to the demodulator 11, but the present invention is not limited to this, and the signal is transmitted by a method such as using a signal line. The same effect can be obtained by performing transmission.

In the above embodiment, the modulator 1 to the demodulator 11
Although only one-way transmission to the telephone has been described, for example, each of the modulator 1 and the demodulator 11 is configured in the base unit of the telephone, and another modulator 1 and the demodulator 11
It is apparent that the effect can be obtained in both the transmission from the parent device to the child device and the transmission from the child device to the parent device. At this time, a delta value increase / decrease determiner, which is a common configuration of the modulator and the demodulator in the master unit, may be shared.

[0054]

According to the present invention, an optimum criterion can be selected from a plurality of criteria in a demodulator according to a signal level from a modulator, and a delta value determined by a plurality of delta value increase / decrease rates can be selected. Since the delta value determined by the optimum delta value increase / decrease rate can be selected from among the above, it is possible to reduce data transmission errors due to a decrease in the level of the output signal from the modulator, and further, to reduce the signal of the demodulator. Demodulation time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an adaptive delta modulator / demodulator according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional adaptive delta modem.

[Explanation of symbols]

 Reference Signs List 1 modulator 2 comparator 3 delta value increase / decrease determiner 4 up / down counter 5 storage device 6 accumulative adder / subtractor 7 D / A converter 8 communication signal level determiner 11 demodulator 21 modulator 23 delta value increase / decrease determiner 31 demodulation vessel

Claims (3)

(57) [Claims] 1. A communication signal level judging device comprising a modulator and a demodulator, wherein the demodulator judges a signal level from the modulator, and an up / down signal increasing / decreasing according to an output of a delta value increasing / decreasing judging device. A down counter; and a storage device having an output value of the up / down counter as an address, wherein the storage device has a plurality of outputs determined by a plurality of delta value increase / decrease rates with respect to an output of one up / down counter. An adaptive delta modulator / demodulator that stores a delta value of the communication signal level and outputs a delta value determined by the communication signal level determiner from a plurality of delta values. 2. A communication signal level determiner comprising a modulator and a demodulator, wherein the demodulator determines an output signal level from the modulator, and the modulator according to a determination result of the communication signal level determiner. delta value change determining unit determines the increase or decrease of the detected frequency to be the same level delta value output signal level is on continuously, the output of the delta values decrease determination unit
Up / down counter that increases or decreases according to
/ The delta value is recorded using the output value of the down counter as an address.
Storage device and the communication signal level judgment unit
Delta value read from the storage device according to the fixed result
According to the output of the delta value increase / decrease determiner.
Adaptive delta modulator / demodulator having an accumulative adder / subtractor . 3. A communication signal level judging device comprising a modulator and a demodulator, wherein the demodulator judges a signal level from the modulator, and a communication signal level judging device according to a predetermined judgment criterion. A delta value increase / decrease determiner for determining increase / decrease of the delta value; an up / down counter which increases / decreases in accordance with the output of the delta value increase / decrease determiner; and a storage device using the output value of the up / down counter as an address. The delta value increase / decrease determiner determines the increase / decrease of the delta value by a criterion determined according to the output of the communication signal level determiner from among a plurality of criterions, and the storage device includes one of the up / down values. And a plurality of delta values determined by a plurality of delta value increase / decrease rates with respect to the output of the down counter, and a delta value determined by the communication signal level determiner from the plurality of delta values. Adaptive delta modulator / demodulator that outputs values.