JP3225676B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3225676B2
JP3225676B2 JP07987093A JP7987093A JP3225676B2 JP 3225676 B2 JP3225676 B2 JP 3225676B2 JP 07987093 A JP07987093 A JP 07987093A JP 7987093 A JP7987093 A JP 7987093A JP 3225676 B2 JP3225676 B2 JP 3225676B2
Authority
JP
Japan
Prior art keywords
interlayer insulating
insulating film
etching
photoresist
dry etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP07987093A
Other languages
Japanese (ja)
Other versions
JPH06291097A (en
Inventor
純理 下根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP07987093A priority Critical patent/JP3225676B2/en
Publication of JPH06291097A publication Critical patent/JPH06291097A/en
Application granted granted Critical
Publication of JP3225676B2 publication Critical patent/JP3225676B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は表示装置や半導体装置
(本明細書においては、これらを合わせて単に「半導体
装置」という。)の製造方法、特にポリイミド樹脂膜等
の有機樹脂膜からなる層間絶縁膜のドライエッチング
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a semiconductor device.
(In this specification, these are collectively referred to simply as “semiconductor
Device. " The present invention particularly relates to a method for dry etching an interlayer insulating film made of an organic resin film such as a polyimide resin film.

【0002】[0002]

【従来の技術】ポリイミド樹脂膜の微細加工方法として
はポリイミド樹脂膜の完全硬化後にヒドラジン系エッチ
ャントを用いるもの、半硬化時に上層のフォトレジスト
現像と同時にウエットエッチングを行うもの、完全硬化
後にドライエッチングを行うもの、さらにはポリイミド
樹脂に感光性を持たせ通常のフォトレジストの如くパタ
ーニングを行うものの4種類がある。しかし2〜3μm
以下のパターン寸法を得るためにはドライエッチングが
精度上望ましい。ドライエッチングの場合使用ガスの主
成分は酸素であるが、この場合ポリイミド樹脂上のエッ
チングマスクには酸素プラズマに対し耐性を持たせる方
がパターニング上有利なので、電子材料1988年12
月号46頁記載の如く、ポリイミド樹脂のエッチングマ
スクにはMo薄膜などの金属薄膜を用いたりする。
2. Description of the Related Art As a fine processing method of a polyimide resin film, a method using a hydrazine-based etchant after the polyimide resin film is completely cured, a method in which wet etching is performed simultaneously with the development of an upper-layer photoresist during semi-curing, and a method in which dry etching is performed after complete curing. There are four types, one that performs the patterning, and a method that imparts photosensitivity to the polyimide resin and performs patterning like a normal photoresist. But 2-3 μm
In order to obtain the following pattern dimensions, dry etching is desirable in terms of accuracy. In the case of dry etching, the main component of the gas used is oxygen. In this case, it is more advantageous for the etching mask on the polyimide resin to have resistance to oxygen plasma in terms of patterning.
As described in the monthly publication on page 46, a metal thin film such as a Mo thin film is used as an etching mask of a polyimide resin.

【0003】[0003]

【発明が解決しようとする課題】ポリイミド樹脂に開口
したコンタクトホールのアスペクト比が大きい場合、コ
ンタクトホール断面に順テーパーが付いている方が上層
配線は断線を起こしにくい。しかしながらドライエッチ
ングで、なおかつ金属薄膜の如く非後退マスクを用いる
と断面形状は垂直あるいはオーバーハング形状を呈す
る。従って上層配線は断線を起こし易くなる。
When the aspect ratio of the contact hole opened in the polyimide resin is large, the upper layer wiring is less likely to be disconnected if the contact hole has a forward taper. However, when dry etching is performed and a non-receding mask such as a metal thin film is used, the cross-sectional shape exhibits a vertical or overhang shape. Therefore, the upper layer wiring is easily broken.

【0004】従ってドライエッチングを行いながらもコ
ンタクト形状に順テーパーを与えることが望ましいが、
そのためにはフォトレジストの様にエッチング中に後退
する材質をエッチングマスクに選択せねばならない。と
ころでポリイミド樹脂のような有機薄膜のエッチング終
点検出は通常COプラズマ発光の強度変化を用いるが、
フォトレジストのように同じく有機薄膜をエッチングマ
スクに用いるとこの検出方法は使用困難である。
Accordingly, it is desirable to give a forward taper to the contact shape while performing dry etching.
For this purpose, a material that recedes during etching, such as a photoresist, must be selected as an etching mask. By the way, the detection of the etching end point of an organic thin film such as a polyimide resin usually uses the intensity change of CO plasma emission,
If an organic thin film is used as an etching mask like a photoresist, this detection method is difficult to use.

【0005】[0005]

【課題を解決するための手段】本発明は、シリコンまた
は酸化シリコン膜を有する基板上に有機樹脂からなる層
間絶縁膜を有する半導体装置の製造方法において、前記
基板上に層間絶縁膜を形成して硬化させる工程と、前記
層間絶縁膜上にフォトレジストによりエッチングマスク
を形成する工程と、前記層間絶縁膜のドライエッチング
をフロン系ガスと酸素の混合ガスによるプラズマで行
い、その際前記層間絶縁膜のドライエッチングの終点検
出をSiF 4 またはSiFのプラズマ発光でモニターす
る工程と、前記SiF 4 またはSiFのプラズマ発光強
度の増加検知によるドライエッチングの終点検出に基づ
前記フロン系ガスの供給を停止して酸素ガスにより前
記層間絶縁膜をエッチングする工程を有することを特徴
とする。
SUMMARY OF THE INVENTION The present invention provides a method for producing silicon or silicon.
Is a method of manufacturing a semiconductor device having an interlayer insulating film made of an organic resin on a substrate having a silicon oxide film , wherein a step of forming an interlayer insulating film on the substrate and curing the substrate; The step of forming an etching mask and the dry etching of the interlayer insulating film are performed by plasma using a mixed gas of a chlorofluorocarbon-based gas and oxygen, and the end point of the dry etching of the interlayer insulating film is detected by plasma emission of SiF 4 or SiF. Monitoring and plasma emission intensity of the SiF 4 or SiF.
Based on the end point detection of dry etching
It characterized by having a step of etching the interlayer insulating film by oxygen gas by stopping the supply of the feeder the flon gas.

【0006】本発明は、基板にポリイミド樹脂等の窒素
を含む有機樹脂からなる層間絶縁膜を有する半導体装置
の製造方法において、前記基板上に前記層間絶縁膜を形
成して硬化させる工程と、前記層間絶縁膜のエッチング
マスクとしてオルソジアゾナフトキノン−ノボラック樹
脂系フォトレジストを用い、前記フォトレジストの塗
布、プレベーク、露光、現像を順に行う工程と、前記フ
ォトレジストを全面露光した上でポストベークを行う工
程と、前記層間絶縁膜を酸素ガスを用いてドライエッチ
ングを行い、その際前記層間絶縁膜のドライエッチング
の終点検出をNOのプラズマ発光でモニターする工程を
有することを特徴とする。
According to the present invention, there is provided a method of manufacturing a semiconductor device having an interlayer insulating film made of an organic resin containing nitrogen such as a polyimide resin on a substrate, comprising the steps of: forming the interlayer insulating film on the substrate; Using an orthodiazonaphthoquinone-novolak resin-based photoresist as an etching mask for an interlayer insulating film, a step of sequentially applying, prebaking, exposing, and developing the photoresist, and a step of performing postbaking after exposing the photoresist entirely. And dry etching the interlayer insulating film using oxygen gas, and monitoring the end point of the dry etching of the interlayer insulating film by plasma emission of NO.

【0007】[0007]

【0008】[0008]

【0009】[0009]

【実施例】(実施例1) ガラス基板101上に多結晶
シリコンを1000Å堆積し、所定の形状にパターニン
グを行って下層配線102を得る。この後層間絶縁膜1
03として、例えば日産化学社製RN812のようなポ
リイミド樹脂を2μm程度の膜厚となるよう塗布し、オ
ーブンを用いて300℃の窒素雰囲気中で樹脂の焼成を
行う。次に3μm程度の膜厚のフォトレジスト104を
形成し、層間絶縁膜103のエッチングマスクとする。
層間絶縁膜103のエッチングにはドライエッチングと
して反応性イオンエッチング(以下RIE)法を用い
た。エッチングは50mTorr、RF入力193mW/c
m 2 、CHF 3 ガス流量1sccm、O 2 ガス流量20sccmで
行った。このエッチングの際にSiF 4 プラズマ発光の
強度変化を観測することにより、層間絶縁膜103のエ
ッチング終点検出を行った。層間絶縁膜103の被エッ
チング部分下の下層配線102が露出した段階でSiF
4 プラズマ発光強度は増加するが、この時点からCHF 3
ガスの供給を停止し、O 2 ガスのみでオーバーエッチン
グを行った。エッチング終了後剥離液にてフォトレジス
ト104を剥離し、層間絶縁膜103の加工工程を終了
する。
EXAMPLES (Example 1) Polycrystalline silicon is deposited on a glass substrate 101 at a thickness of 1000 Å, and is patterned into a predetermined shape to obtain a lower wiring 102. After this, the interlayer insulating film 1
As 03, for example, a polyimide resin such as RN812 manufactured by Nissan Chemical Co., Ltd. is applied so as to have a thickness of about 2 μm, and the resin is fired in a nitrogen atmosphere at 300 ° C. using an oven. Next, a photoresist 104 having a thickness of about 3 μm is formed and used as an etching mask for the interlayer insulating film 103.
Reactive ion etching (hereinafter referred to as RIE) was used as dry etching for etching the interlayer insulating film 103. Etching is 50mTorr, RF input is 193mW / c
m 2 , CHF 3 gas flow rate 1 sccm, O 2 gas flow rate 20 sccm. The end point of the etching of the interlayer insulating film 103 was detected by observing a change in the intensity of SiF 4 plasma emission during this etching. When the lower wiring 102 under the portion to be etched of the interlayer insulating film 103 is exposed, the SiF
4 Although the plasma emission intensity increases, CHF 3
The supply of gas was stopped, and overetching was performed using only O 2 gas. After the etching is completed, the photoresist 104 is stripped with a stripping solution, and the process of processing the interlayer insulating film 103 is completed.

【0010】以上の実施例により層間絶縁膜103をF
元素添加による増速エッチングができるのみならず、層
間絶縁膜103の被エッチング部分の下層膜が多結晶シ
リコンや酸化シリコンの様なシリコン含有膜である時
に、SiF 4 プラズマ発光の観測によりエッチング終点
検出が可能となった。従って下層配線が露出したと同時
にフロン系ガスの供給を停止でき、下層配線がCHF 3
などのフロン系ガスでエッチングされる材質であっても
該下層配線のエッチング進行を防ぐ亊ができる。
According to the above embodiment, the interlayer insulating film 103 is
In addition to being able to perform accelerated etching by adding elements, when the underlying film of the portion to be etched of the interlayer insulating film 103 is a silicon-containing film such as polycrystalline silicon or silicon oxide, the etching end point is detected by observing the emission of SiF 4 plasma. Became possible. Therefore, the supply of the CFC-based gas can be stopped at the same time as the lower wiring is exposed, and the lower wiring becomes CHF 3.
Even if the material is etched by a chlorofluorocarbon gas, the progress of etching of the lower wiring can be prevented.

【0011】同時にフォトレジストをエッチングマスク
として使用可能になったので、コンタクトホール形状に
順テーパーを与える事が可能になった。
At the same time, since the photoresist can be used as an etching mask, it is possible to give a forward taper to the shape of the contact hole.

【0012】また本実施例ではエッチング終点検出にS
iF 4 プラズマ発光を用いた例を示したが、SiFプラ
ズマ発光を用いる事もできた。
In this embodiment, S is used for detecting the etching end point.
Although the example using iF 4 plasma light emission was shown, SiF plasma light emission could also be used.

【0013】(実施例2) ガラス基板201上に多結
晶シリコンを1000Å堆積し、所定の形状にパターニ
ングを行って下層配線202を得る。この後層間絶縁膜
203として、例えば日産化学社製RN812のような
ポリイミド樹脂を2μm程度の膜厚となるよう塗布し、
オーブンを用いて300℃の窒素雰囲気中で樹脂の焼成
を行う。次に例えば東京応化社製TSMR8700の様
な感光基にオルソジアゾナフトキノンを用いてあるノボ
ラック樹脂系フォトレジスト204を3μm程度の膜厚
になるよう塗布、プレベーク、露光、現像を順に行う。
この後フォトレジスト204に全面露光を行い、150
℃1時間空気雰囲気中でポストベークを行ってエッチン
グマスクを得る。層間絶縁膜203のエッチングにはR
IE法を用いた。エッチングは50mTorr、RF入
力193mW/cm 2 、O 2 ガス流量20sccmで行った。この
エッチングの際に波長2560ÅのNOプラズマ発光の
強度変化を観測することにより、層間絶縁膜203のエ
ッチング終点検出を行った。エッチング終了後残存して
いるフォトレジスト204を剥離液にて剥離し、層間絶
縁膜203の加工工程を終了した。
(Example 2) Polycrystalline silicon is deposited on a glass substrate 201 at a thickness of 1000 、, and is patterned into a predetermined shape to obtain a lower wiring 202. Thereafter, as the interlayer insulating film 203, for example, a polyimide resin such as RN812 manufactured by Nissan Chemical Co. is applied so as to have a thickness of about 2 μm,
The resin is fired in a nitrogen atmosphere at 300 ° C. using an oven. Next, a novolak resin-based photoresist 204 using orthodiazonaphthoquinone as a photosensitive group such as TSMR8700 manufactured by Tokyo Ohka Co., Ltd. is sequentially coated, prebaked, exposed, and developed to a thickness of about 3 μm.
Thereafter, the entire surface of the photoresist 204 is exposed,
Post-baking is performed in an air atmosphere at 1 ° C. for 1 hour to obtain an etching mask. R is used for etching the interlayer insulating film 203.
The IE method was used. Etching was performed at 50 mTorr, RF input of 193 mW / cm 2 , and O 2 gas flow rate of 20 sccm. The end point of the etching of the interlayer insulating film 203 was detected by observing the change in the intensity of the NO plasma emission at a wavelength of 2560 ° during this etching. After the etching was completed, the remaining photoresist 204 was stripped with a stripping solution, and the processing step of the interlayer insulating film 203 was completed.

【0014】実施例中でフォトレジストに全面露光をか
けたのは、フォトレジスト中の感光基であるオルソジア
ゾナフトキノンから光照射によりN 2 を離脱せしめん為
である。エッチングマスクであるフォトレジスト204
からN元素が離脱すると、層間絶縁膜中のN元素による
NOプラズマ発光信号が明瞭に現れるので、故に層間絶
縁膜203の終点検出が容易になった。同時にフォトレ
ジストをエッチングマスクとして使用可能になったた
め、層間絶縁膜203のコンタクトホール形状に順テー
パー角を与える事ができた。
The reason why the entire surface of the photoresist is exposed in the examples is that N 2 is released from the photosensitive group orthodiazonaphthoquinone in the photoresist by light irradiation. Photoresist 204 as an etching mask
When the N element is released from the substrate, a NO plasma emission signal due to the N element in the interlayer insulating film clearly appears, so that the end point of the interlayer insulating film 203 can be easily detected. At the same time, since the photoresist can be used as an etching mask, a forward taper angle can be given to the contact hole shape of the interlayer insulating film 203.

【0015】[0015]

【発明の効果】本発明を用いれば、ポリイミド樹脂等の
有機樹脂を用いた層間絶縁膜のエッチングマスクとし
て、エッチング中に後退するフォトレジストの使用が可
能になり、故に層間絶縁膜のコンタクトホール形状に順
テーパー角を設けることが可能である。また、本発明に
より、ポリイミド樹脂等の有機樹脂を用いた層間絶縁膜
の下層のシリコンあるいは酸化シリコンをエッチングす
ることなく、ポリイミド樹脂等の有機樹脂を用いた層間
絶縁膜のエッチングを迅速且つ完全、確実に行うことが
できる。
According to the present invention, it is possible to use a photoresist that recedes during etching as an etching mask for an interlayer insulating film using an organic resin such as a polyimide resin. Can be provided with a forward taper angle. In addition, the present invention
More interlayer insulating film using organic resin such as polyimide resin
The underlying silicon or silicon oxide
Without using an organic resin such as polyimide resin
Quick, complete and reliable etching of insulating films
it can.

【0016】また、従来必要であった、層間絶縁膜上に
エッチングマスクとなる金属薄膜を設ける工程と、該金
属薄膜をパターニングする工程と、層間絶縁膜のエッチ
ング終了後該金属薄膜を剥離する工程が省略できるの
で、工程の簡略化及び低コスト化が可能になった。
Further, a step of providing a metal thin film serving as an etching mask on the interlayer insulating film, a step of patterning the metal thin film, and a step of peeling the metal thin film after the etching of the interlayer insulating film, which have been conventionally required. Can be omitted, so that the process can be simplified and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 実施例1記載の工程を表す断面図。FIG. 1 is a cross-sectional view illustrating a process described in a first embodiment.

【図2】 実施例2記載の工程を表す断面図。FIG. 2 is a cross-sectional view illustrating a process described in a second embodiment.

【図3】 従来例の工程を表す断面図。FIG. 3 is a cross-sectional view illustrating a process of a conventional example.

【符号の説明】[Explanation of symbols]

101、201、301 ガラス基板 102、202、302 下層配線 103、203、303 層間絶縁膜 104、204、304 フォトレジスト 305 金属薄膜 101, 201, 301 Glass substrate 102, 202, 302 Lower wiring 103, 203, 303 Interlayer insulating film 104, 204, 304 Photoresist 305 Metal thin film

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/3065 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/3065 H01L 21/768

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 シリコンまたは酸化シリコン膜を有する
基板上に有機樹脂からなる層間絶縁膜を有する半導体装
置の製造方法において、 前記基板上に層間絶縁膜を形成して硬化させる工程と、
前記層間絶縁膜上にフォトレジストによりエッチングマ
スクを形成する工程と、前記層間絶縁膜のドライエッチ
ングをフロン系ガスと酸素の混合ガスによるプラズマで
行い、その際前記層間絶縁膜のドライエッチングの終点
検出をSiF 4 またはSiFのプラズマ発光でモニター
する工程と、前記SiF 4 またはSiFのプラズマ発光
強度の増加検知によるドライエッチングの終点検出に基
づき前記フロン系ガスの供給を停止して酸素ガスにより
前記層間絶縁膜をエッチングする工程を有することを特
徴とする半導体装置の製造方法。
1. It has a silicon or silicon oxide film.
In a method of manufacturing a semiconductor device having an interlayer insulating film made of an organic resin on a substrate, a step of forming and curing an interlayer insulating film on the substrate,
Forming an etching mask with a photoresist on the interlayer insulating film, and performing dry etching of the interlayer insulating film by plasma using a mixed gas of a chlorofluorocarbon-based gas and oxygen, and detecting an end point of the dry etching of the interlayer insulating film. Monitoring by plasma emission of SiF 4 or SiF, and plasma emission of SiF 4 or SiF
Based on end point detection of dry etching by detecting increase in intensity
The method of manufacturing a semiconductor device characterized by comprising the step of Hazuki etching the interlayer insulating film by oxygen gas by stopping the supply of the flon gas.
【請求項2】基板にポリイミド樹脂等の窒素を含む有機
樹脂からなる層間絶縁膜を有する半導体装置の製造方法
において、 前記基板上に前記層間絶縁膜を形成して硬化させる工程
と、前記層間絶縁膜のエッチングマスクとしてオルソジ
アゾナフトキノン−ノボラック樹脂系フォトレジストを
用い、前記フォトレジストの塗布、プレベーク、露光、
現像を順に行う工程と、前記フォトレジストを全面露光
した上でポストベークを行う工程と、前記層間絶縁膜を
酸素ガスを用いてドライエッチングを行い、その際前記
層間絶縁膜のドライエッチングの終点検出をNOのプラ
ズマ発光でモニターする工程を有することを特徴とする
半導体装置の製造方法。
2. A method of manufacturing a semiconductor device having an interlayer insulating film made of an organic resin containing nitrogen such as a polyimide resin on a substrate, comprising: forming the interlayer insulating film on the substrate and curing the film; Using an orthodiazonaphthoquinone-novolak resin-based photoresist as an etching mask for the film, coating the photoresist, pre-baking, exposing,
A step of sequentially performing development, a step of performing post-baking after exposing the entire surface of the photoresist, and a step of performing dry etching on the interlayer insulating film using oxygen gas, and detecting an end point of the dry etching of the interlayer insulating film at that time. Monitoring the semiconductor device with plasma emission of NO.
JP07987093A 1993-04-06 1993-04-06 Method for manufacturing semiconductor device Expired - Lifetime JP3225676B2 (en)

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JP07987093A JP3225676B2 (en) 1993-04-06 1993-04-06 Method for manufacturing semiconductor device

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JPH06291097A JPH06291097A (en) 1994-10-18
JP3225676B2 true JP3225676B2 (en) 2001-11-05

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129727A (en) * 1995-10-30 1997-05-16 Nec Corp Semiconductor device and manufacturing method thereof
KR20160116121A (en) 2015-03-25 2016-10-07 삼성디스플레이 주식회사 Thin film trnasistor array panel and display device including the same

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