JP3219816B2 - Decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit for a semiconductor memory, for example.

[0002]

2. Description of the Related Art FIG. 1 shows a part of a conventional memory circuit. Memory cells 11 arranged in a matrix
Are N-channel MOS transistors (NMOS
Transistor) 12 and bit lines B0, B1 to B3
It is connected to the. The gates of these NMOS transistors 12 are connected to word lines W0, W1 to W3. A row decoder 13 is connected to the word lines W0 and W1 to W3, and a column decoder 14 is connected to the bit lines B0 and B1 to B3. The row decoder 1
3 are supplied with address data A0, A1 to A4 and their inverted data / A0, / A1 to / A4, and the column decoder 14 is supplied with address data A5, A6 and their inverted data / A5, / A6 is supplied. According to these address data, the row decoder 13,
The memory cell 11 is accessed by selecting one word line and one bit line from a plurality of word lines and bit lines by the column decoder 14.

The row decoder 13 comprises AND circuits 15, 16, 17, 18 for selecting a word line according to address data A0, A1 to A4, / A0, / A1 to / A4. Are AND circuits 19, 20, 21, and 22 to which address data A5, A6, / A5, and / A6 are supplied, and NM that selects a bit line according to output signals of these AND circuits 19 to 22
It is composed of OS transistors 23, 24, 25 and 26. FIGS. 2A and 2B show the row decoder 1.
3 shows AND circuits 15 and 16 which constitute 3.

An AND circuit 16 shown in FIG. 2A is a PMOS transistor connected in parallel between a power supply _VDD and a node 31 and controlled by address data / A4, / A3, / A2, / A1, A0. 32, 33, 34, 3
5,36, connected in series between each other of the node 31 and the power supply V _SS, the address data / A4, / A3, / A2 , / A
1. NMOS transistor 3 controlled by A0
7, 38, 39, 40, 41, and an inverter circuit 42 connected between the node 31 and the word line W1.
It is constituted by.

The AND circuit 15 shown in FIG.
Are connected in parallel between the power supply V _DD and the node 51, and address data / A4, / A3, / A2, / A1, / A0
PMOS transistors 52, 53 controlled by
54, 55 and 56, connected in series between each other of the node 51 and the power supply V _SS, the address data / A4, / A3, / A
2, NMOS transistors 57, 58, 59, 60, 61 controlled by / A1, / A0, and an inverter circuit 62 connected between the node 51 and the word line W0.

[0006]

FIG. 3 shows the patterns of the AND circuits 15 and 16 described above. in this way,
The AND circuit constituting the row decoder is composed of two adjacent circuits.
Each one is designed as one circuit pattern.

However, in the above-mentioned conventional row decoder, an AND circuit composed of 12 transistors is connected to each word line. For this reason, the area occupied by the row decoder in the semiconductor memory is increasing. Recently, since the pattern size of the memory cell has been reduced, the pattern size of the row decoder also needs to be reduced. However, when the AND circuit having the above configuration is used, the number of circuit elements is large. It was difficult to miniaturize the material.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. It is an object of the present invention to provide a decoding device capable of reducing the number of circuit elements and miniaturizing a pattern size. It is intended to provide a circuit.

[0009]

In order to solve the above-mentioned problems, the present invention is connected between a first power supply and a second power supply, and has n bits of address data and one of the n bits. A gate circuit for selectively outputting an output signal to first and second output terminals in accordance with the inverted signal of the bit, the gate circuit being provided between the first power supply and the first node; Connected to each other in accordance with n-1 bit address data of the n bit address data.
A first logic circuit for connecting the first power supply to the second power supply node, and a second logic circuit connected between the second power supply and the second node. A second logic circuit connecting the second power supply to the second node, between the first node and the first and second output terminals, and between the second node and the first and second nodes. And outputs the signals of the first and second nodes to the first and second output terminals in accordance with one bit of the n-bit address data and its inverted signal. A third logic circuit for selectively outputting, and a third logic circuit provided between the first power supply and the first and second output terminals, for outputting one bit of the n-bit address data and its inverted signal; A fourth logic circuit for selectively outputting a signal to the first and second output terminals. It is provided with a door. Further, the gate circuit is constituted by an AND circuit. Further, the gate circuit is constituted by an OR circuit.

Further, according to the present invention, the first conductivity type is connected in parallel between the first power supply and the first node and controlled by n-1 bit address data out of n bit address data. A plurality of first transistors are connected between the first power supply and a second node as an output node, and one of the n-bit address data is connected.
A second transistor of a first conductivity type controlled by a bit, connected between the first node and a third node as an output node, controlled by one bit of the n-bit address data And a third transistor of a first conductivity type connected between the first node and the second node, the third transistor being controlled by the inverted one bit of the n-bit address data. A fourth transistor of one conductivity type and a first conductivity type connected between the first power supply and a third node and controlled by the inverted one bit of the n-bit address data; And a plurality of sixth transistors of a second conductivity type connected in series between a fourth node and a second power supply and controlled by the (n-1) -bit address data. And register, the second node and the fourth
And a seventh transistor of the second conductivity type, which is controlled by one bit of the n-bit address data, and is connected between the third node and the fourth node. And an eighth transistor of a second conductivity type controlled by the inverted one bit of the n-bit address data.

[0011]

That is, according to the present invention, the first to fourth logic circuits constituting the gate circuit provide a pair of complementary data in response to n-bit address data and a signal obtained by inverting one of the n bits. And the selected signal is selected according to one of the n address data and the inverted signal of the address data.
The signal is output from the second output terminal. Therefore, when this decode circuit is applied to a memory circuit, adjacent word lines can be selected by one gate circuit, so that the number of elements constituting the gate circuit can be reduced and the size of the pattern can be reduced. Can be reduced.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows an AND circuit which constitutes the decoding circuit of the present invention. The AND circuit 71 selects adjacent word lines W0 and W1.

[0014] In the AND circuit 71, between the mutual power supply V _DD and the node A, PMOS transistors 72 and 73,
74 and 75 are connected in parallel. The gates of the PMOS transistors 72 to 75 are provided with / addresses out of n address data / A0, / A1, / A2, / A3, / A4.
A4, / A3, / A2, / A1 are supplied respectively. A PMOS is provided between the power supply V _DD and the node B.
The transistor 76 is connected, and the node A and the node C are connected.
Are connected to each other with a PMOS transistor 77. Address data / A0 is supplied to the gates of the PMOS transistors 76 and 77, respectively. Further, P is set between the nodes A and B.
A MOS transistor 78 is connected, and a PMOS transistor 79 is connected between the power supply _VDD and the node C. Address data A0 is supplied to the gates of the PMOS transistors 78 and 79, respectively.

On the other hand, between the node D and the power supply V _SS (ground potential), NMOS transistors 80, 81, 82,
83 are connected in series. The gates of these NMOS transistors 80, 81, 82 and 83 are supplied with the address data / A4, / A3, / A2 and / A1. An NMO is provided between the node B and the node D.
An S transistor 84 is connected, and address data / A0 is supplied to a gate of the NMOS transistor 84. Further, an NMOS transistor 85 is connected between the nodes C and D, and the gate of the NMOS transistor 85 is supplied with address data A0. The node B is connected to a word line W0 via an inverter circuit 86, and the node C is connected to a word line W1 via an inverter circuit 87. The operation of the above configuration will be described.

The n address data A0, A1, A2,
A3, A4 = “0, 0, 0, 0, 0”, that is, / A
0, / A1, / A2, / A3, / A4 = “1, 1, 1,.
If it is 1, 1 ", the NMOSFET transistor 8
0, 81, 82, 83, 84 are all in ON state, NMOS
FET transistor 85 is off, PMOS transistors 72, 73, 74, 75, 76, 77 are off,
The PMOS transistors 78 and 79 are turned on. Therefore, node B is at "0" level, and node C is at "1".
Level, the output terminal of the inverter circuit 86 becomes "1" level, the output terminal of the inverter circuit 87 becomes "0" level, and the word line W0 is selected.

Address data A0, A1, A2,
A3, A4 = “1, 0, 0, 0, 0”, that is, / A
0, / A1, / A2, / A3, / A4 = “0, 1, 1,.
If it is 1, 1 ", the NMOSFET transistor 8
0, 81, 82, 83, 85 are all on, NMOS
FET transistor 84 is off, PMOS transistors 72, 73, 74, 75, 78, 79 are off,
The PMOS transistors 76 and 77 are turned on. Therefore, node B is at "1" level and node C is at "0".
Level, the output terminal of the inverter circuit 86 becomes "0" level, the output terminal of the inverter circuit 87 becomes "1" level, and the word line W1 is selected.

FIG. 5 is a pattern plan view of the AND circuit 71 shown in FIG. 4, and the same parts as those in FIG. In the case of this embodiment, since the prime number can be reduced as compared with the related art, the pattern size can be reduced as compared with the pattern shown in FIG.

According to the above embodiment, the output level of the AND circuit to which the n address data is input is selectively output by one of the n address data and the inverted signal thereof. I have. Therefore, since the adjacent word lines W0 and W1 can be selected by one AND circuit 71, the number of elements of the AND circuit 71 can be reduced, and the size of the pattern can be reduced.

In the above embodiment, the row decoder is used for the CM.
Although an AND circuit having an OS structure is used, the present invention is not limited to this. For example, the row decoder may be configured using a gate circuit such as a NAND circuit, an OR circuit, and a NOR circuit having a CMOS structure. Also in this case, by selecting the output level of each gate circuit by the least significant bit of the address data and its inverted signal, the same effect as in the above embodiment can be obtained. Of course, various modifications can be made without departing from the scope of the present invention.

[0021]

As described above, according to the present invention, n-bit address data and one bit of the n bits are inverted by the first to fourth logic circuits forming the gate circuit. A pair of complementary signals are generated in accordance with the selected signal, and this signal is selected by one of n address data and its inverted signal, and the first and second output terminals of the gate circuit are selected. , The number of circuit elements can be reduced, and a decoding circuit capable of miniaturizing the pattern size can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an example of a semiconductor memory.

FIGS. 2A and 2B are circuit diagrams each showing a part of a conventional decoding circuit.

FIG. 3 is a pattern plan view of the decoding circuit shown in FIGS. 2 (a) and 2 (b).

FIG. 4 is a circuit diagram showing one embodiment of the present invention and showing a part of a decoding circuit.

FIG. 5 is a pattern plan view of the decoding circuit shown in FIG. 4;

[Explanation of symbols]

71 AND circuit, 72 to 79 PMOS transistor, 80 to 85 NMOS transistor, / A0 to / A
4 ... Address data, 86, 87 ... Inverter circuit.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yumiko Takano 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture In-house Toshiba Microelectronics Corporation (56) References JP-A-63-292488 (JP, A) 2-162838 (JP, A) JP-A-63-285793 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/419

Claims (4)

(57) [Claims] A first power supply connected between a first power supply and a second power supply and outputting first and second outputs in response to n-bit address data and a signal obtained by inverting one of the n bits; A gate circuit for selectively outputting an output signal at an end, the gate circuit being connected between the first power supply and the first node;
A first logic circuit for connecting the first power supply to the first node in accordance with n-1 bit address data of the bit address data; A second logic circuit that is connected to each other and connects the second power supply to the second node in accordance with the (n−1) -bit address data; Between the two output ends,
And the first and second nodes are provided between the second node and the first and second output terminals according to one bit of the n-bit address data and its inverted signal. A third logic circuit for selectively outputting a signal to the first and second output terminals; and a n-bit circuit provided between the first power supply and the first and second output terminals. And a fourth logic circuit for selectively outputting a signal to the first and second output terminals in accordance with one bit of the address data and an inverted signal thereof. . 2. The decoding circuit according to claim 1, wherein said gate circuit comprises an AND circuit. 3. The decoding circuit according to claim 1, wherein said gate circuit comprises an OR circuit. 4. An n-bit address data which is connected in parallel between a first power supply and a first node, and wherein n-1
A plurality of first transistors of a first conductivity type controlled by bit address data; connected between the first power supply and a second node as an output node; A second transistor of a first conductivity type controlled by one bit of the first node and a third node connected as an output node between the first node and one bit of the n-bit address data A third transistor of a first conductivity type controlled by the first node and a third node connected between the first node and the second node;
A fourth transistor of a first conductivity type controlled by the inverted one bit of the n-bit address data; a fourth transistor connected between the first power supply and a third node; The inverted one of the address data of
A fifth transistor of a first conductivity type controlled by a bit, a second transistor of a second conductivity type connected in series between a fourth node and a second power supply, and controlled by the (n-1) -bit address data. A plurality of sixth transistors, connected between the second node and the fourth node,
A seventh transistor of a second conductivity type controlled by one bit of the n-bit address data, connected between the third node and a fourth node;
And an eighth transistor of a second conductivity type controlled by the inverted one bit of the n-bit address data.