JP3204792B2 - Semiconductor device - Google Patents

Semiconductor device

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JP3204792B2
JP3204792B2 JP10097193A JP10097193A JP3204792B2 JP 3204792 B2 JP3204792 B2 JP 3204792B2 JP 10097193 A JP10097193 A JP 10097193A JP 10097193 A JP10097193 A JP 10097193A JP 3204792 B2 JP3204792 B2 JP 3204792B2
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formed
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semiconductor
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JPH06310727A (en
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昇 松田
諭 柳谷
裕 越野
嘉朗 馬場
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株式会社東芝
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】この発明は、エミッタ層中に高濃度不純物層が形成された縦型MOS FET等の半導体装置に関する。 BACKGROUND OF THE INVENTION This invention relates to a semiconductor device such as a vertical type MOS FET of the high concentration impurity layer is formed in the emitter layer.

【0002】 [0002]

【従来の技術】従来、縦型MOS FETは、例えば図5及び図6に示すように構成されている。 Conventionally, vertical type MOS FET is configured as shown for example in FIGS. 図5は縦型M Figure 5 is a vertical M
OS FETにおけるベース高濃度不純物層を形成した後の状態を示しており、図6はソース電極を形成した後の図5のA−A´線に沿った断面図である。 It shows the state after forming the base high concentration impurity layer in the OS FET, FIG. 6 is a sectional view taken along the A-A'line in Figure 5 after forming a source electrode. 図5において、11はN型のシリコン基板で、このシリコン基板1 5, 11 is an N-type silicon substrate, the silicon substrate 1
1の主表面にはP型のベース層12が形成されている。 Base layer 12 of P-type is formed in the first major surface.
このベース層12中には、N型のエミッタ層13が形成される。 During this base layer 12, emitter layer 13 of N-type is formed. エミッタ層13における中央のエミッタコンタクト部には、ベース層12に達する深さにストライプ状のP +型ベース高濃度不純物層14が形成される。 The emitter contact portion of the center of the emitter layer 13, stripe-shaped P + -type base high concentration impurity layer 14 to a depth reaching the base layer 12 is formed. エミッタ層13の一部上及び上記高濃度不純物層14上を除くシリコン基板11上にはゲート酸化膜15が形成され、このゲート酸化膜15上にポリシリコン層等から成るゲート電極16が形成されている。 A gate oxide film 15 is formed on the silicon substrate 11 except a portion on and the high concentration impurity layer 14 above the emitter layer 13, a gate electrode 16 made of polysilicon layer or the like is formed on the gate oxide film 15 ing.

【0003】縦型MOS FETを形成する際には、まず、シリコン基板11上に酸化膜及びポリシリコン層を順次形成した後、パターニングを行ってゲート酸化膜1 [0003] In forming a vertical MOS FET, first, after the oxide film and a polysilicon layer are sequentially formed on the silicon substrate 11, a gate oxide film 1 by patterning
5及びゲート電極16を形成する。 5 and gate electrode 16 are formed. 次に、上記ゲート電極16をマスクにしてシリコン基板11中に不純物をイオン注入することによりベース層12を形成し、このベース層12の表面にエミッタ層13を形成する。 Then the gate electrode 16 as a mask base layer 12 is formed by ion-implanting an impurity into the silicon substrate 11 to form an emitter layer 13 on the surface of the base layer 12. その後、ゲート電極16上及び露出された基板11の一部の領域上にマスクを形成し、エミッタコンタクト部にベース層12と同タイプの不純物をイオン注入してP +型ベース高濃度不純物層14を形成する。 Thereafter, a mask is formed over part of the area of the gate electrode 16 and on the exposed substrate 11, a base layer 12 on the emitter contact portion of the same type of impurity is ion-implanted P + -type base high concentration impurity layer 14 to form. この高濃度不純物層14は、MOS FETの閾値電圧の安定化、ベース電位の固定、及びコンタクト性を良くするためのものである。 The high concentration impurity layer 14, the stabilization of the threshold voltage of the MOS FET, the base potential fixed, and is intended to improve the contact resistance.

【0004】次に、図6に示すように、上記ゲート電極16及び基板11上にCVD SiO 2等からなるパッシベーション膜17を形成した後、上記高濃度不純物層14上にコンタクトホール17Aを形成し、このパッシベーション膜17上にソース電極18を形成する。 [0004] Next, as shown in FIG. 6, after forming the passivation film 17 made of CVD SiO 2 or the like on the gate electrode 16 and the substrate 11, a contact hole 17A is formed on the high concentration impurity layer 14 to form the source electrode 18 on the passivation film 17. これによって、ソース電極18がコンタクトホール17Aを介して高濃度不純物層14に電気的に接続される。 Thus, the source electrode 18 is electrically connected to the high concentration impurity layer 14 through the contact hole 17A. また、上記基板11の裏面には図示しないドレイン電極が形成される。 The drain electrode (not shown) on the back surface of the substrate 11 is formed.

【0005】ところで、上記コンタクトホール17Aは通常RIEで形成されるが、確実なコンタクトを得ようとすると基板11の表面がエッチングされ、オーバーエッチング部Qが形成される。 Meanwhile, the above contact holes 17A are formed in a conventional RIE, is to be obtained reliable contact surface of the substrate 11 is etched, overetching portion Q is formed. 高不純物濃度層14を形成したことによって、このオーバーエッチング部Qではエミッタ層13の不純物濃度が低下する。 By forming the high impurity concentration layer 14, the impurity concentration of the over-etching portion Q in the emitter layer 13 decreases. この不純物濃度の低下は、破線で示す電流Rに対して抵抗値の増大を招くため、縦型MOSFETのオン抵抗が高くなる。 This reduction in the impurity concentration, because it causes an increase in the resistance value with respect to the current R shown by the broken line, the on-resistance of the vertical MOSFET is increased.

【0006】 [0006]

【発明が解決しようとする課題】上記のようにベース高濃度不純物層を形成した従来の縦型MOS FETは、 THE INVENTION Problems to be Solved] prior to forming the base high concentration impurity layer as described above the vertical MOS FET is
ソース電極取り出しのためのパッシベーション膜へのコンタクトホールの形成時に、エミッタ層の表面がオーバーエッチングされると、エミッタ層の不純物濃度が低下し、電流経路の抵抗値が高くなり、オン抵抗が高くなるという問題があった。 During the formation of the contact hole in the passivation film for the extraction source electrode, the surface of the emitter layer is over-etched, reduced impurity concentration of the emitter layer, the higher the resistance of the current path, the on-resistance becomes high there is a problem in that.

【0007】この発明は上記のような事情に鑑みてなされたもので、その目的とするところは、電流経路の抵抗値を低くでき、オン抵抗を下げることができる半導体装置を提供することにある。 [0007] The present invention has been made in view of the above circumstances, and has as its object, can reduce the resistance value of the current path is to provide a semiconductor device capable of lowering the on-resistance .

【0008】 [0008]

【課題を解決するための手段】請求項1の半導体装置は、第1導電型の半導体基体と、この半導体基体の主表面に形成される第2導電型の第1半導体領域と、上記第1半導体領域中に形成される第1導電型の第2半導体領域と、 単一の第2半導体領域中に上記第1半導体領域に達する深さに各々が離隔して形成される第2導電型で高不純物濃度の複数の第3半導体領域と、上記第1半導体領域に絶縁膜を介在して当接する第1電極と、 上記第3 The semiconductor device according to claim 1 Means for Solving the Problems] includes a first conductive type semiconductor substrate, a first semiconductor region of a second conductivity type formed on the main surface of the semiconductor body, the first a second semiconductor region of the first conductivity type formed in a semiconductor region, the second conductivity type, each of which is spaced apart from a depth in a single second semiconductor region reaches said first semiconductor region a plurality of third semiconductor regions of high impurity concentration, a first electrode in contact with an insulating film interposed in the first semiconductor region, the third
の半導体領域に電気的に接続される第1のコンタクト領 First contact territory to be electrically connected to the semiconductor region
域、及び隣接する上記第3の半導体領域間の上記第2の Frequency, and adjacent between said third semiconductor region to the second
半導体領域に電気的に接続される第2のコンタクト領域 Second contact region electrically connected to the semiconductor region
を有する第2電極と、上記半導体基体の裏面に形成される第3電極とを具備することを特徴とする。 A second electrode having, characterized by comprising a third electrode formed on the back surface of the semiconductor body.

【0009】請求項2に記載した半導体装置は、第1導電型の半導体基板と、この半導体基板の主表面に形成される第2導電型のベース層と、上記ベース層中に形成される第1導電型のエミッタ層と、 単一のエミッタ層中に上記ベース層に達する深さで各々が離隔して形成される第2導電型の複数の高濃度不純物層と、上記ベース層上に形成されるゲート絶縁膜と、このゲート絶縁膜上に形成されるゲート電極と、 上記高濃度不純物層に電気的に [0009] The semiconductor device according to claim 2, a semiconductor substrate of a first conductivity type, a base layer of a second conductivity type formed on the main surface of the semiconductor substrate, the first being formed in said base layer a first conductivity type emitter layer, a second conductivity type more heavily doped impurity layer of each of which is spaced apart from a depth reaching the base layer in a single emitter layer, formed on the base layer a gate insulating film, a gate electrode formed on the gate insulating film, electrically to the high concentration impurity layer
接続される第1のコンタクト領域、及び隣接する上記高 First contact region connected, and adjacent the high
濃度不純物層間のエミッタ領域に電気的に接続される第 The are electrically connected to the emitter region of the doped layers
2のコンタクト領域を有するソース電極と、上記半導体基板の裏面に形成されるドレイン電極とを具備することを特徴としている。 A source electrode having a second contact region, is characterized by having a drain electrode formed on the back surface of the semiconductor substrate.

【0010】また、請求項3の半導体装置は、第1導電型の半導体基板と、この半導体基板の主表面に形成される第2導電型のベース層と、上記ベース層上に形成される第1導電型のエミッタ層と、 単一のエミッタ層中に上記ベース層に達する深さで各々が離隔して形成される第2導電型の複数の高濃度不純物層と、上記半導体基板に形成された溝内にゲート絶縁膜を介在して埋め込み形成され、上記溝の側壁部において上記ベース層に上記ゲート絶縁膜を介して対向するゲート電極と、 上記高濃度不 Further, the semiconductor device according to claim 3, a semiconductor substrate of a first conductivity type, a second conductivity type base layer formed on the main surface of the semiconductor substrate, the first being formed in said base layer a first conductivity type emitter layer, a second conductivity type more heavily doped impurity layer of each of which is spaced apart from a depth reaching the base layer in a single emitter layer, formed on the semiconductor substrate is embedded with a gate insulating film formed in the groove, a gate electrode opposed to each other via the gate insulating film to the base layer in the side wall of the groove, the high concentration not
純物層に電気的に接続される第1のコンタクト領域、及 First contact region electrically connected to a pure object layer,及
び隣接する上記高濃度不純物層間のエミッタ領域に電気 Electrical the emitter region of the high concentration impurity layers to fine adjacent
的に接続される第2のコンタクト領域を有するソース電極と、上記半導体基板の裏面に形成されるドレイン電極とを具備することを特徴とする。 A source electrode having a second contact region being connected, characterized by comprising a drain electrode formed on the back surface of the semiconductor substrate.

【0011】 [0011]

【作用】エミッタ層(第2半導体領域)中に複数の高濃度不純物層(第3半導体領域)を離隔して設けているので、高濃度不純物層とソース電極(第2電極)とが接触する部分は閾値電圧の安定化、ベース電位の固定及びコンタクト性の向上のために働き、ソース電極とエミッタ層とが接触する部分はオーバーエッチング部が形成された時にエミッタ層の不純物濃度の低下を防止してコンタクト抵抗を低減するために働くので、高濃度不純物層を設けることによる利点を損なうことなく縦型MOS F [Action] Since eccentrically disposed with a plurality of high concentration impurity layer (third semiconductor region) in the emitter layer (second semiconductor region), are in contact with the high concentration impurity layer and the source electrode (second electrode) stabilizing portions threshold voltage serves for fixation and improvement of the contact of the base potential, to prevent the reduction of the impurity concentration of the emitter layer when the portion of contact between the source electrode and the emitter layer is over-etched portion is formed since it serves to reduce the contact resistance and, vertical MOS F without impairing the advantages of providing a high concentration impurity layer
ET(半導体装置)における電流経路の抵抗値を低くでき、オン抵抗を下げることができる。 The resistance of the current path in the ET (semiconductor device) can be lowered, it is possible to reduce the on-resistance.

【0012】 [0012]

【実施例】以下、この発明の一実施例について図面を参照して説明する。 EXAMPLES The following will be described with reference to the accompanying drawings, an embodiment of the present invention. 図1及び図2はそれぞれ、この発明の第1の実施例に係る半導体装置について説明するためのもので、図1は縦型MOS FETにおけるベース高濃度不純物層を形成した後の状態を示している。 Figures 1 and 2 is for explaining a semiconductor device according to a first embodiment of the present invention, FIG. 1 shows a state after forming the base high concentration impurity layer in the vertical MOS FET there. 図2は、 Figure 2,
この図1の縦型MOS FETにおけるソース電極を形成した後のB−B´線に沿った断面を示している。 It shows a cross section taken along the B-B'line after forming a source electrode in the vertical MOS FET of FIG. 図1 Figure 1
のA−A´線に沿った断面は図6と同様である。 The cross-section along the A-A'line is the same as that shown in FIG.

【0013】N型シリコン基板21の主表面にはP型のベース層22が形成され、このベース層22中にN型のエミッタ層23が形成されている。 [0013] The main surface of the N-type silicon substrate 21 is formed a P-type base layer 22, emitter layer 23 of N-type is formed in the base layer 22. 上記エミッタ層23 The emitter layer 23
における中央のエミッタコンタクト部には、ベース層2 The emitter contact portion of the center of the base layer 2
2に達する深さで各々が離隔したP +型ベース高濃度不純物層24−1,24−2,24−3,…が形成される。 P + -type base height each spaced at a depth reaching the 2 concentration impurity layer 24-1, 24-2, 24-3, ... are formed. 上記不純物層24−1,24−2,24−3,…の表面濃度は、1×10 18 cm -3以上であることが好ましい。 It said impurity layer 24-1, 24-2, 24-3, ... surface concentration of is preferably 1 × 10 18 cm -3 or higher. 上記エミッタ層23及び上記高濃度不純物層24− The emitter layer 23 and the high concentration impurity layer 24
1,24−2,24−3,…上を除くシリコン基板21 1,24-2,24-3, the silicon substrate 21 except for the above ...
上には、ゲート酸化膜25が形成され、このゲート酸化膜25上にポリシリコン等から成るゲート電極26が形成される。 The upper, gate oxide film 25 is formed, a gate electrode 26 made of polysilicon or the like is formed on the gate oxide film 25.

【0014】上記縦型MOS FETは、次のように形成される。 [0014] The vertical type MOS FET is formed as follows. まず、シリコン基板21上に酸化膜及びポリシリコン層を順次形成した後、パターニングを行ってゲート酸化膜25及びゲート電極26を形成する。 First, after the oxide film and a polysilicon layer are sequentially formed on the silicon substrate 21, to form a gate oxide film 25 and the gate electrode 26 by patterning. 次に、 next,
上記ゲート電極26をマスクにしてシリコン基板21中に不純物をイオン注入することによりベース層22を形成し、このベース層22の表面にエミッタ層23を形成する。 And the gate electrode 26 as a mask base layer 22 is formed by ion-implanting an impurity into the silicon substrate 21 to form an emitter layer 23 on the surface of the base layer 22. その後、ゲート電極26及び露出された基板21 Thereafter, the gate electrode 26 and exposed substrate 21
上に、エミッタコンタクト部に各々が離隔した複数の開口を有するマスクを形成する。 Above, to form a mask having a plurality of openings, each spaced to the emitter contact portion. そして、このマスクを介してエミッタ層23中にベース層22と同タイプの不純物をベース層22に達する深さまで高濃度にイオン注入し、P +型ベース高濃度不純物層24−1,24−2, Then, ion implantation at a high concentration of the same type of impurity and the base layer 22 to a depth reaching the base layer 22 in the emitter layer 23 through the mask, P + -type base high concentration impurity layers 24-1 and 24-2 ,
24−3,…を形成する。 24-3, to form a .... この高濃度不純物層24− This high concentration impurity layer 24
1,24−2,24−3,…は、閾値電圧の安定化、ベース電位の固定、及びコンタクト性の向上を図るためのものである。 1,24-2,24-3, ... it is stabilized threshold voltage, the base potential fixed, and is intended to improve the contact resistance.

【0015】次に、図2に示すように上記ゲート電極2 [0015] Next, the gate electrode 2 as shown in FIG. 2
6及び基板21上にCVD SiO 2等からなるパッシベーション膜27を形成した後、RIEにより上記高濃度不純物層24−1,24−2,24−3,…上に跨がるコンタクトホール27Aを形成する。 6 and forming a passivation film 27 made of CVD SiO 2 or the like on the substrate 21, formed extending over the contact hole 27A in the high concentration impurity layers 24-1, 24-2, 24-3, ... on the RIE to. そして、上記パッシベーション膜27上にアルミニウム等の金属層を蒸着形成し、パターニングを行ってソース電極28を形成する。 Then, the passivation film 27 a metal layer such as aluminum vapor deposited on to form the source electrode 28 by patterning. これによって、ソース電極28がコンタクトホール27Aを介して高濃度不純物層24−1,24−2, Thus, the high concentration impurity layer source electrode 28 via the contact hole 27A 24-1 and 24-2,
24−3,…及びこれらの不純物層間のエミッタ層23 24-3, ... and the emitter layer 23 of these impurities layers
と電気的に接続される。 It is electrically connected to. また、ソース電極28と同様にして、半導体基板21の裏面にドレイン電極(図示せず)を形成する。 In the same manner as the source electrode 28, a drain electrode (not shown) on the back surface of the semiconductor substrate 21.

【0016】このような構成によれば、エミッタ層23 [0016] According to such a configuration, the emitter layer 23
中に複数の高濃度不純物層24−1,24−2,24− A plurality of high-concentration impurity layer in 24-1,24-2,24-
3,…を離隔して設けているので、図6に示した構造と同様に、高濃度不純物層24−1,24−2,24− 3, since the eccentrically disposed with a ..., as with the structure shown in FIG. 6, the high concentration impurity layer 24-1,24-2,24-
3,…とソース電極28とが接触する部分は閾値電圧の安定化、ベース電位の固定及びコンタクト性の向上のために働く。 3, ... and a portion where the source electrode 28 are in contact acts stabilization threshold voltage, for fixation and improvement of the contact of the base potential. また、図2に示すようにソース電極28とエミッタ層23とが接触する部分は、エミッタ層23の表面がエッチングされた場合(オーバーエッチング部が形成された時)に、このエミッタ層23の不純物濃度の低下によるコンタクト抵抗の増大を低減するために働く。 The portion where the source electrode 28 and the emitter layer 23 is in contact as shown in FIG. 2, when the surface of the emitter layer 23 is etched (when over-etched portion is formed), an impurity of the emitter layer 23 It serves to reduce the increase in contact resistance due to decrease in the concentration.
すなわち、図2の領域Sには、P +型の不純物が導入されないので、エミッタ層23の不純物濃度の低下は起こらない。 That is, the area S in FIG. 2, since the P + -type impurity is not introduced, lowering the impurity concentration of the emitter layer 23 does not occur. 従って、高濃度不純物層24−1,24−2, Therefore, the high concentration impurity layers 24-1 and 24-2,
24−3,…を設けることによる利点を損なうことなく縦型MOS FETにおける電流経路の抵抗値を低くでき、オン抵抗を下げることができる。 24-3, ... can reduce the resistance value of the current path in the vertical MOS FET without impairing the advantages of providing a can reduce the on-resistance.

【0017】なお、この発明は上記実施例に限定されるものではなく、図3及び図4に示すようなトレンチ構造の縦型MOS FETにも適用可能である。 [0017] The present invention is not limited to the above embodiment is also applicable to a vertical type MOS FET having a trench structure as shown in FIGS. 図3において、31はN型シリコン基板、32はP型のベース層、 3, the N-type silicon substrate 31, 32 is P-type base layer,
33はN型のエミッタ層、34A−1,34A−2,3 33 denotes an emitter layer of N-type, 34A-1,34A-2,3
4A−3,…及び34B−1,34B−2,34B− 4A-3, ... and 34B-1,34B-2,34B-
3,…はそれぞれ表面濃度が1×10 18 cm -3以上のP 3, ... surface concentration each 1 × is 10 18 cm -3 or more P
+型ベース高濃度不純物層、35はゲート酸化膜、36 + -Type base high concentration impurity layer, 35 denotes a gate oxide film, 36
はゲート電極であり、このゲート電極36は基板31に形成された溝40内にゲート絶縁膜35を介在して埋め込まれている。 Is a gate electrode, the gate electrode 36 is buried in a gate insulating film 35 in the groove 40 formed in the substrate 31. これによって、ゲート電極36は、溝4 Thereby, the gate electrode 36, the groove 4
0の側壁部においてベース層32にゲート絶縁膜35を介して対向して配置される。 The base layer 32 at the sidewall portion of 0 is arranged oppositely through a gate insulating film 35. また、図4において、37 Further, in FIG. 4, 37
はCVD SiO 2等からなるパッシベーション膜、3 Passivation film made of CVD SiO 2 mag, 3
7A,37Bはコンタクトホール、38はソース電極である。 7A, 37B contact hole, 38 is a source electrode. なお、図示しないが基板31の裏面にはドレイン電極が形成される。 Although not shown on the back surface of the substrate 31 is the drain electrode are formed.

【0018】上記図3及び図4に示したようなトレンチ構造の縦型MOS FETであっても上記第1の実施例と同様に、高濃度不純物層34A−1,34A−2,3 [0018] FIG 3 and as with vertical even MOS FET of the first embodiment of a trench structure as shown in FIG. 4, the high concentration impurity layer 34A-1,34A-2,3
4A−3,…及び34B−1,34B−2,34B− 4A-3, ... and 34B-1,34B-2,34B-
3,…とソース電極38とが接触する部分は閾値電圧の安定化、ベース電位の固定及びコンタクト性の向上のために働き、ソース電極38とエミッタ層33とが接触する部分は、エミッタ層33の不純物濃度の低下が少ないので、オーバーエッチングによりエミッタ層33の表面がエッチングされた場合にコンタクト抵抗の増大を防止するために働く。 3, ... and a portion where the source electrode 38 is in contact stabilization threshold voltage serves for fixation of the base potential and the increase of the contact resistance, the portion of contact between the source electrode 38 and the emitter layer 33, emitter layer 33 since lowering of the impurity concentration is small, it serves to prevent an increase in contact resistance when the surface of the emitter layer 33 is etched by over-etching. 従って、高濃度不純物層34A−1, Therefore, the high concentration impurity layer 34A-1,
34A−2,34A−3,…及び34B−1,34B− 34A-2,34A-3, ... and 34B-1,34B-
2,34B−3,…を設けることによる利点を損なうことなく、トレンチ構造の縦型MOS FETにおける電流経路の抵抗値を低くでき、オン抵抗を下げることができる。 2,34B-3, without impairing the advantage of providing a ..., can reduce the resistance value of the current path in the vertical MOS FET having a trench structure, it is possible to reduce the on-resistance.

【0019】 [0019]

【発明の効果】以上説明したようにこの発明によれば、 According to the present invention as described above, according to the present invention,
電流経路の抵抗を低くでき、素子のオン抵抗を下げることができる半導体装置が得られる。 The resistance of the current path can be lowered, it is possible to obtain a semiconductor device that can reduce the on-resistance of the device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】この発明の第1の実施例に係る半導体装置について説明するためのもので、縦型MOS FETにおけるベース高濃度不純物層を形成した後の状態を示す斜視図。 [1] first semiconductor device according to an embodiment of the present invention for illustrating a perspective view showing a state after forming the base high concentration impurity layer in the vertical MOS FET of the present invention.

【図2】この発明の第1の実施例に係る半導体装置について説明するためのもので、図1に示した縦型MOS [2] for the purpose of explaining a semiconductor device according to a first embodiment of the present invention, a vertical type MOS shown in FIG. 1
FETにおけるソース電極を形成した後のB−B´線に沿った断面図。 Sectional view taken along the B-B'line after forming a source electrode in FET.

【図3】この発明の第2の実施例に係る半導体装置について説明するためのもので、トレンチ構造の縦型MOS [3] for the purpose of explaining a semiconductor device according to a second embodiment of the present invention, a vertical MOS trench structure
FETにおけるベース高濃度不純物層を形成した後の状態を示す斜視図。 Perspective view showing a state after the formation of the base high concentration impurity layer in the FET.

【図4】この発明の第2の実施例に係る半導体装置について説明するためのもので、図3に示したトレンチ構造の縦型MOS FETにおけるソース電極を形成した後のC−C´線に沿った断面図。 [4] for the purpose of explaining a semiconductor device according to a second embodiment of the present invention, the C-C'line after forming a source electrode in the vertical MOS FET trench structure shown in FIG. 3 along the sectional view.

【図5】従来の半導体装置について説明するためのもので、縦型MOS FETにおけるベース高濃度不純物層を形成した後の状態を示す斜視図。 [5] intended for explaining the conventional semiconductor device, perspective view showing a state after forming the base high concentration impurity layer in the vertical MOS FET.

【図6】従来の半導体装置について説明するためのもので、図5に示した縦型MOSFETにおけるソース電極を形成した後のA−A´線に沿った断面図。 [6] for the purpose of explaining a conventional semiconductor device, cross-sectional view taken along the A-A'line after forming a source electrode in the vertical MOSFET shown in FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

21,31…シリコン基板、22,32…ベース層、2 21, 31 ... silicon substrate, 22, 32 ... base layer, 2
3,33…エミッタ層、24,34A−1,34A− 3, 33 ... emitter layer, 24,34A-1,34A-
2,34A−3,…,34B−1,34B−2,34B 2,34A-3, ..., 34B-1,34B-2,34B
−3,… …ベース高濃度不純物層、25,35…ゲート酸化膜、26,36…ゲート電極、27,37…パッシベーション膜、28,38…ソース電極、40…溝。 -3, ... base high concentration impurity layers, 25 and 35 ... gate oxide film, 26, 36 ... gate electrode, 27, 37 ... passivation film, 28, 38 ... Source electrode, 40 ... groove.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 越野 裕 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝多摩川工場内 (56)参考文献 特開 平4−180238(JP,A) 特開 昭64−89465(JP,A) 特開 昭59−231860(JP,A) 特開 平2−60169(JP,A) 特開 平1−198076(JP,A) (58)調査した分野(Int.Cl. 7 ,DB名) H01L 29/78 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Hiroshi Koshino Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho, address 1 Toshiba Corporation Tamagawa in the factory (56) reference Patent flat 4-180238 (JP, a) JP Akira 64-89465 (JP, a) JP Akira 59-231860 (JP, a) JP flat 2-60169 (JP, a) JP flat 1-198076 (JP, a) (58) investigated the field (Int .Cl. 7, DB name) H01L 29/78

Claims (4)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】 第1導電型の半導体基体と、この半導体基体の主表面に形成される第2導電型の第1半導体領域と、上記第1半導体領域中に形成される第1導電型の第2半導体領域と、 単一の第2半導体領域中に上記第1半導体領域に達する深さに各々が離隔して形成される第2 And 1. A first conductivity type semiconductor substrate, a first semiconductor region of a second conductivity type formed on the main surface of the semiconductor substrate of a first conductivity type formed in said first semiconductor region a second semiconductor region, a second, each to a depth in a single second semiconductor region reaches said first semiconductor region is spaced apart from
    導電型で高不純物濃度の複数の第3半導体領域と、上記第1半導体領域に絶縁膜を介在して当接する第1電極と、 上記第3の半導体領域に電気的に接続される第1の In conductivity type and a plurality of third semiconductor regions of high impurity concentration, a first electrode in contact with an insulating film interposed in the first semiconductor region, a first electrically connected to the third semiconductor region
    コンタクト領域、及び隣接する上記第3の半導体領域間 Contact region, and adjacent between said third semiconductor region
    の上記第2の半導体領域に電気的に接続される第2のコ Second co is the electrically connected to the second semiconductor region
    ンタクト領域を有する第2電極と、上記半導体基体の裏面に形成される第3電極とを具備することを特徴とする半導体装置。 A semiconductor device comprising: the second electrode having a Ntakuto area, by comprising a third electrode formed on the back surface of the semiconductor body.
  2. 【請求項2】 第1導電型の半導体基板と、この半導体基板の主表面に形成される第2導電型のベース層と、上記ベース層中に形成される第1導電型のエミッタ層と、 2. A semiconductor substrate of a first conductivity type, a second conductivity type base layer formed on the main surface of the semiconductor substrate, the emitter layer of the first conductivity type formed in said base layer,
    単一のエミッタ層中に上記ベース層に達する深さで各々が離隔して形成される第2導電型の複数の高濃度不純物層と、上記ベース層上に形成されるゲート絶縁膜と、このゲート絶縁膜上に形成されるゲート電極と、 上記高濃 A second conductivity type more heavily doped impurity layer of each of which is spaced apart from a depth reaching the base layer in a single emitter layer, a gate insulating film formed on the base layer, this a gate electrode formed on the gate insulating film, the high concentrated
    度不純物層に電気的に接続される第1のコンタクト領 First contact territory that is electrically connected to degrees impurity layer
    域、及び隣接する上記高濃度不純物層間のエミッタ領域 Band, and the emitter region adjacent the high concentration impurity layers
    に電気的に接続される第2のコンタクト領域を有するソ<br/>ース電極と、上記半導体基板の裏面に形成されるドレイン電極とを具備することを特徴とする半導体装置。 A semiconductor device comprising: the source <br/> over the source electrode having a second contact region electrically connected, by including a drain electrode formed on the back surface of the semiconductor substrate.
  3. 【請求項3】 第1導電型の半導体基板と、この半導体基板の主表面に形成される第2導電型のベース層と、上記ベース層上に形成される第1導電型のエミッタ層と、 3. A semiconductor substrate of a first conductivity type, a second conductivity type base layer formed on the main surface of the semiconductor substrate, the emitter layer of the first conductivity type formed in said base layer,
    単一のエミッタ層中に上記ベース層に達する深さで各々が離隔して形成される第2導電型の複数の高濃度不純物層と、上記半導体基板に形成された溝内にゲート絶縁膜を介在して埋め込み形成され、上記溝の側壁部において上記ベース層に上記ゲート絶縁膜を介して対向するゲート電極と、 上記高濃度不純物層に電気的に接続される第 Single and second conductivity type more heavily doped impurity layer of each of which is spaced apart in the base layer to reach the depth in the emitter layer, the gate insulating film in a trench formed in the semiconductor substrate is interposed to buried, a gate electrode opposed through the gate insulating film to the base layer at the sidewall portion of the trench, the electrically connected to the high concentration impurity layer
    1のコンタクト領域、及び隣接する上記高濃度不純物層 1 of the contact area, and adjacent the high concentration impurity layer
    間のエミッタ領域に電気的に接続される第2のコンタク Second contactor electrically connected to the emitter region between
    ト領域を有するソース電極と、上記半導体基板の裏面に形成されるドレイン電極とを具備することを特徴とする半導体装置。 The semiconductor device according to a source electrode having a preparative area, characterized by comprising a drain electrode formed on the back surface of the semiconductor substrate.
  4. 【請求項4】 前記高濃度不純物層の表面濃度は、1× The surface concentration of claim 4 wherein said high concentration impurity layer, 1 ×
    10 18 cm −3以上であることを特徴とする請求項2 10 18 claim, characterized in that at cm -3 or more 2
    または3記載の半導体装置。 Or third semiconductor device as claimed.
JP10097193A 1993-04-27 1993-04-27 Semiconductor device Expired - Lifetime JP3204792B2 (en)

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JP3384198B2 (en) * 1995-07-21 2003-03-10 三菱電機株式会社 An insulated gate semiconductor device and a manufacturing method thereof
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JP4928753B2 (en) * 2005-07-14 2012-05-09 株式会社東芝 Trench gate type semiconductor device
JP5465837B2 (en) * 2008-03-31 2014-04-09 ローム株式会社 Semiconductor device
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