JP3203731B2 - Semiconductor element substrate and mounting method, substrate with columnar terminals and method of manufacturing the same - Google Patents
Semiconductor element substrate and mounting method, substrate with columnar terminals and method of manufacturing the sameInfo
- Publication number
- JP3203731B2 JP3203731B2 JP01976692A JP1976692A JP3203731B2 JP 3203731 B2 JP3203731 B2 JP 3203731B2 JP 01976692 A JP01976692 A JP 01976692A JP 1976692 A JP1976692 A JP 1976692A JP 3203731 B2 JP3203731 B2 JP 3203731B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- columnar
- forming
- sheet
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子をセラミック
基板にバンプ接合する、耐熱衝撃性の半導体素子実装基
板および実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat-resistant and shock-resistant semiconductor element mounting board and method for bonding a semiconductor element to a ceramic substrate by bump bonding.
【0002】[0002]
【従来の技術】従来、裸の半導体素子を導体パターンが
形成された基板に電気的に接続する方法としては、半導
体素子の電極パッド上に、メッキ法により突出接点を形
成し、この突出接点に基板を接続するのが一般的であっ
た。2. Description of the Related Art Conventionally, as a method of electrically connecting a bare semiconductor element to a substrate on which a conductor pattern is formed, a projecting contact is formed on an electrode pad of the semiconductor element by a plating method, and this projecting contact is formed. It was common to connect substrates.
【0003】また、米国特許第4661192号明細書
においては、導電性接着剤を用いてフェースダウンによ
り半導体素子を基板に簡易的に接続する方法が述べられ
ている。Also, US Pat. No. 4,661,192 describes a method for simply connecting a semiconductor element to a substrate by face-down using a conductive adhesive.
【0004】以下に従来の半導体素子の接続方法を図面
を参照しながら説明する。図6(a)〜(d)に従来の
半導体素子の接続工程を示す。図6(a)は半導体素子
に突出接点を形成する工程を示す。図に示すように、半
導体素子15上に形成された電極パッド上に、金属ボー
ル21を溶融して接続する。金属ボール21の作成は、
キャピラリを通って支持されている金属ワイヤ19を水
素炎トーチで加熱溶融してボール18を形成し、キャピ
ラリ17を電極パッド16に押接してボール18を電極
パッド16にボール18を固着する。その後、金属ワイ
ヤ19を引張って切断し、電極パッド16上に金属ボー
ル21と残存金属ワイヤ22からなる突出接点を形成す
る。[0004] A conventional method for connecting semiconductor devices will be described below with reference to the drawings. FIGS. 6A to 6D show a connection process of a conventional semiconductor element. FIG. 6A shows a step of forming a projecting contact on the semiconductor element. As shown in the figure, a metal ball 21 is melted and connected to an electrode pad formed on a semiconductor element 15. The preparation of the metal ball 21
The metal wire 19 supported through the capillary is heated and melted by a hydrogen flame torch to form a ball 18, and the capillary 17 is pressed against the electrode pad 16 to fix the ball 18 to the electrode pad 16. After that, the metal wire 19 is pulled and cut to form a projecting contact made of the metal ball 21 and the remaining metal wire 22 on the electrode pad 16.
【0005】つぎに、図6(b)に示すように、金属ボ
ール22を固着した半導体素子15を、平坦面が形成さ
れた基材24に押しつけることにより、平坦化したボー
ル23を得る。Next, as shown in FIG. 6B, a flattened ball 23 is obtained by pressing the semiconductor element 15 having the metal ball 22 fixed thereon against a base material 24 having a flat surface formed thereon.
【0006】さらに、図6(c)に示すように、平坦化
したボール23を接続した半導体素子15を、支持基材
26上に塗布した導電性接着剤25に当接することによ
り、平坦化したボール23上にのみ導電性接着剤を転写
する。Further, as shown in FIG. 6C, the semiconductor element 15 to which the flattened balls 23 are connected is brought into contact with a conductive adhesive 25 applied on a supporting base material 26 to be flattened. The conductive adhesive is transferred only on the ball 23.
【0007】上記のようにして、電極パッド16上の平
坦化したボール23上に導電性接着剤25を形成した半
導体素子15を、図6(a)に示すように、基板28の
導体パターン27に位置合せして固着することによっ
て、電気的な接続を行うものである。As described above, the semiconductor element 15 in which the conductive adhesive 25 is formed on the flattened ball 23 on the electrode pad 16 is connected to the conductor pattern 27 on the substrate 28 as shown in FIG. The electrical connection is made by positioning and fixing in position.
【0008】[0008]
【発明が解決しようとする課題】しかし、上記のような
従来の半導体素子と基板との電気的接続方法では熱膨張
係数の異なる半導体素子と基板を非常に接近して接続す
るため、熱膨張により発生する応力により接続部が破断
するという課題があった。However, in the conventional method for electrically connecting a semiconductor element to a substrate as described above, a semiconductor element having a different coefficient of thermal expansion is very closely connected to a substrate. There is a problem that the connection part is broken by the generated stress.
【0009】また、半導体素子の接合ピッチ幅は、電極
パッドに固着するボールの形状とキャピラリの寸法によ
り規制されるため、半導体素子の基板への微細接合が困
難であるという課題があった。In addition, since the bonding pitch width of the semiconductor element is regulated by the shape of the ball fixed to the electrode pad and the dimensions of the capillary, there is a problem that it is difficult to finely join the semiconductor element to the substrate.
【0010】本発明は上記の課題を解決するもので、基
板上に柱状バンプを形成し、その柱状バンプに半導体素
子を信頼性良く電気的に接続することのできる半導体素
子の実装基板および実装方法を提供することを目的とす
るものである。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and a semiconductor device mounting substrate and a mounting method capable of forming a columnar bump on a substrate and electrically connecting the semiconductor device to the columnar bump with high reliability. The purpose is to provide.
【0011】[0011]
【課題を解決するための手段】本発明は上記の課題を解
決するため、半導体素子を実装する基板と、基板面に対
して上方に突出する柱状導体バンプとを備え、前記柱状
導体バンプが前記基板内部の内層導体パターンと直結し
ており、前記柱状導体バンプ上に半導体素子の電極パッ
ドを接合するようにしたものである。In order to solve the above-mentioned problems, the present invention comprises a substrate on which a semiconductor element is mounted, and a column-shaped conductor bump protruding upward with respect to the substrate surface, wherein the column-shaped conductor bump is provided at the front. An electrode pad of a semiconductor element is directly connected to an inner conductor pattern inside the substrate, and is bonded to the columnar conductor bump.
【0012】また、基板構成シートとバンプ形成用シー
トを形成する工程と、前記両シートを孔開けし、その孔
を導体ペーストで埋める工程と、2種類のシートのうち
バンプ形成用シートを最上層とし、複数の基板構成シー
トを下層として順次積層する工程と、積層した多層シー
トを焼成し、最上層を除去する工程と、そのときに形成
した柱状バンプ上に半導体素子をフェースダウンボンデ
ィング法により実装する工程とを経て半導体素子を実装
するようにしたものである。A step of forming a board-constituting sheet and a sheet for forming a bump; a step of forming a hole in each of the sheets and a step of filling the holes with a conductive paste; A step of sequentially laminating a plurality of substrate constituent sheets as a lower layer, a step of firing the laminated multilayer sheet and removing the uppermost layer, and mounting a semiconductor element on the pillar-shaped bump formed at that time by a face-down bonding method And a step of mounting the semiconductor element.
【0013】また、バンプ形成用シートが、基板構成シ
ートより高い焼結温度を有し、バンプ形成用シートの焼
結温度と基板構成シートの焼結温度の中間の温度で焼結
し、未焼結のバンプ形成用シートを除去するようにした
ものである。また、半導体素子を実装する基板と、前記
基板面に対して上方に突出する柱状端子とを備え、前記
柱状導体バンプが前記基板内部の内層導体パターンと直
結された柱状端子付き基板である。また、前記柱状端子
が多端子のピングリッドアレイであることを特徴とする
ものである。また、前記柱状端子を設けた面の反対面に
半導体素子が実装され、前記半導体素子の電極パッドと
前記柱状端子とが電気的に接続されているものである。
また、基板構成シートと柱状端子形成用シートを形成す
る工程と、前記両シートを孔開けし、前記孔を導体ペー
ストで埋める工程と、前記2種類のシートのうち柱状端
子形成用シートを最上層とし、複数の基板構成シートを
下層として順次積層する工程と、積層した多層シートを
焼成し、最上層を除去する工程を含む柱状端子付き基板
の製造方法である。また、柱状端子形成用シートが、基
板構成シートより高い焼結温度を有し、柱状端子形成用
シートの焼結温度と基板構成シートの焼結温度の中間の
温度で焼結し、未焼結の柱状端子形成用シートを除去す
るものである。The bump forming sheet has a higher sintering temperature than the substrate forming sheet, and is sintered at a temperature intermediate between the sintering temperature of the bump forming sheet and the sintering temperature of the substrate forming sheet. In this case, the sheet for forming the bump is removed. Further, a substrate for mounting a semiconductor device, wherein a pole terminals protruding upward with respect to the substrate surface, the columnar conductor bump is columnar terminal-provided substrate which is directly connected to the pre-Symbol substrate inside of the inner layer conductor pattern. Further, the columnar terminal is a multi-terminal pin grid array. Further, a semiconductor element is mounted on a surface opposite to a surface on which the columnar terminals are provided, and an electrode pad of the semiconductor element and the columnar terminals are electrically connected.
A step of forming a board-constituting sheet and a sheet for forming a pillar-shaped terminal; a step of perforating both sheets and filling the hole with a conductive paste; And a step of sequentially laminating a plurality of substrate constituent sheets as lower layers, and a step of firing the laminated multilayer sheet to remove the uppermost layer. In addition, the columnar terminal forming sheet has a higher sintering temperature than the substrate forming sheet, and is sintered at a temperature intermediate between the sintering temperature of the columnar terminal forming sheet and the sintering temperature of the substrate forming sheet. Is removed.
【0014】[0014]
【作用】本発明は上記の構成と方法によって、バンプを
柱状にすることにより、熱膨張係数の異なる半導体素子
とセラミック基板を接続しても熱によって発生するせん
断応力を柱状バンプ部で緩衝するため、周囲の温度変化
に対して非常に安定で、信頼性の高い半導体素子の実装
基板および実装方法が実現できることとなる。According to the present invention, the columnar bumps are used to buffer the shear stress generated by heat even when the semiconductor element having a different coefficient of thermal expansion is connected to the ceramic substrate by forming the bumps into a columnar shape. Thus, a semiconductor device mounting board and a mounting method which are very stable against ambient temperature changes and have high reliability can be realized.
【0015】[0015]
【実施例】以下に本発明の一実施例の半導体素子の実装
基板および実装方法について、図面を参照しながら説明
する。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention;
【0016】図1(a)〜(g)は第1の実施例の柱状
バンプ形成工程を示す。図1(a),(b)に示すよう
に基板構成シート1とバンプ形成用シート2はシート成
形工程により高分子シート3上に形成される。基板構成
シート1の材料はアルミナにガラスを含ませた低温焼結
材料であり、バンプ形成用シート2の材料は基板構成シ
ート1より高い焼結温度をもつ材料、例えば、純アルミ
ナ,窒化ボロン,酸化マグネシウムなどを使用する。こ
のようにして形成した両シートを図1(c),(d)に
示すように孔開けを行い、その孔を導体ペースト4で充
填する。この導体ペースト4の主材料としては一般に酸
化銅を使用するが、他の材料、たとえば金,銀などを使
用してもよい。つぎに図1(e)に示すように、バンプ
形成用シート2を最上層とし、複数の基板構成シート1
を下層として順次積層する。このとき、基板シートの間
に内層導体パターン5が形成される。この積層シートを
低温焼結材料からなる基板構成シート1のみが焼結する
温度で焼成し、この温度で焼結し得なかったバンプ形成
用シート2からなる最上層のみを除去する。以上の工程
により、図1(f)に示すように柱状バンプ7が形成さ
れる。FIGS. 1A to 1G show a columnar bump forming step of the first embodiment. As shown in FIGS. 1A and 1B, a substrate forming sheet 1 and a bump forming sheet 2 are formed on a polymer sheet 3 by a sheet forming process. The material of the substrate forming sheet 1 is a low-temperature sintering material in which glass is contained in alumina, and the material of the bump forming sheet 2 is a material having a sintering temperature higher than that of the substrate forming sheet 1, for example, pure alumina, boron nitride, Use magnesium oxide or the like. The sheets thus formed are perforated as shown in FIGS. 1C and 1D, and the holes are filled with the conductive paste 4. Copper oxide is generally used as the main material of the conductor paste 4, but other materials such as gold and silver may be used. Next, as shown in FIG. 1E, the bump forming sheet 2 is the uppermost layer, and a plurality of substrate constituent sheets 1 are formed.
Are sequentially laminated as a lower layer. At this time, the inner layer conductor pattern 5 is formed between the substrate sheets. This laminated sheet is fired at a temperature at which only the substrate forming sheet 1 made of a low-temperature sintering material is sintered, and only the uppermost layer made of the bump forming sheet 2 that cannot be sintered at this temperature is removed. Through the above steps, the columnar bumps 7 are formed as shown in FIG.
【0017】さらに、図1(g)に示すように、電極パ
ッド8上に半田バンプ9をつけた半導体素子6を柱状バ
ンプ上にフェースダウンし加熱炉に通すことにより半田
付けを行い電気的な接続を行う。Further, as shown in FIG. 1 (g), the semiconductor element 6 having the solder bumps 9 on the electrode pads 8 is face-down on the columnar bumps and soldered by passing through a heating furnace to perform electrical connection. Make a connection.
【0018】図2に半導体素子の実装基板形成工程での
柱状バンプ構成を示す。図に示すように、基板10の上
面よりも上方に高く柱状にバンプ7を形成しているのが
特徴である。また、図3に柱状バンプ上に半導体素子を
実装した構成を示す。図に示すように、半導体素子6と
基板1を柱状バンプ7を介して接合しているのを特徴と
している。FIG. 2 shows a columnar bump configuration in a process of forming a mounting board for a semiconductor element. As shown in the figure, the feature is that the bumps 7 are formed in a column shape higher than the upper surface of the substrate 10. FIG. 3 shows a configuration in which a semiconductor element is mounted on a columnar bump. As shown in the drawing, the semiconductor element 6 and the substrate 1 are joined via a columnar bump 7.
【0019】第2の実施例として、以下にピングリッド
アレイの端子形成方法を図面を参照しながら説明する。As a second embodiment, a method of forming terminals of a pin grid array will be described below with reference to the drawings.
【0020】図4(a)〜(g)にピングリッドアレイ
端子形成工程を示す。図に示すように柱状端子11は第
1の実施例の柱状バンプ形成工程と同様に形成する。こ
の場合、柱状端子11は長方形の基板の四辺に形成し、
そのそれぞれの柱状端子11と導通のある電極12を柱
状端子11を有する面の反対面に形成しておく。その
後、図4(g)に示すように、柱状端子11を設けた面
の反対面に半導体素子6を実装し、その半導体素子6の
電極パッド8と基板上の導体電極12をワイヤボンディ
ング法により金ワイヤ13で電気的に接続する。図5
(a)〜(c)にピングリッドアレイ本体の構成を示
す。半導体素子7と導通のある柱状端子11がピングリ
ッドアレイ本体14の内部より直結していることが特徴
である。図5(b)は4端子のピングリッドアレイを、
図5(c)は多端子のピングリッドアレイの構成を示
す。FIGS. 4A to 4G show a step of forming a pin grid array terminal. As shown in the figure, the columnar terminals 11 are formed in the same manner as in the columnar bump forming step of the first embodiment. In this case, the columnar terminals 11 are formed on four sides of a rectangular substrate,
An electrode 12 that is electrically connected to each of the columnar terminals 11 is formed on a surface opposite to the surface having the columnar terminals 11. Thereafter, as shown in FIG. 4 (g), the semiconductor element 6 is mounted on the surface opposite to the surface on which the columnar terminals 11 are provided, and the electrode pads 8 of the semiconductor element 6 and the conductor electrodes 12 on the substrate are bonded by wire bonding. It is electrically connected by the gold wire 13. FIG.
(A) to (c) show the configuration of the pin grid array main body. It is characterized in that the columnar terminals 11 electrically connected to the semiconductor element 7 are directly connected from the inside of the pin grid array main body 14. FIG. 5B shows a 4-terminal pin grid array.
FIG. 5C shows the configuration of a multi-terminal pin grid array.
【0021】上記の構成により、熱衝撃に強く、バンプ
のピッチ精度の高い実装が可能となる。According to the above configuration, mounting with high resistance to thermal shock and high bump pitch accuracy is possible.
【0022】[0022]
【発明の効果】以上の実施例の説明から明らかなように
本発明の半導体素子の実装基板および実装方法によれ
ば、バンプを柱状に形成することにより、熱膨張係数の
異なる半導体素子と基板を接続しても柱状バンプが歪を
吸収し、熱によるせん断応力に対して非常に安定にな
る。また、従来の半導体素子側形成のボール状バンプか
ら基板側形成の柱状バンプにしたことにより、バンプの
ピッチ精度が向上し、半導体素子の実装基板への微細接
合が可能となる。As is apparent from the above description of the embodiments, according to the semiconductor device mounting board and the mounting method of the present invention, the bumps are formed in a columnar shape so that the semiconductor elements and the boards having different thermal expansion coefficients can be separated. Even when connected, the columnar bumps absorb the strain and become very stable against shear stress due to heat. In addition, by changing the conventional ball-shaped bumps formed on the semiconductor element side to the columnar bumps formed on the substrate side, the pitch accuracy of the bumps is improved, and the fine bonding of the semiconductor element to the mounting substrate becomes possible.
【0023】さらに、本発明のピングリッドアレイの柱
状端子においても、そのピンピッチ精度は工程上の孔開
け位置精度と孔径によって決まるため、ピンをピングリ
ッドアレイの電極にロウ付けする従来の工程より微細ピ
ッチピンの形成が可能である。Further, in the columnar terminal of the pin grid array according to the present invention, the pin pitch accuracy is determined by the accuracy of the hole forming position and the hole diameter in the process. A pitch pin can be formed.
【0024】このような半導体素子の実装基板およびピ
ングリッドアレイの柱状端子は、従来のセラミック多層
基板製造用の設備で容易に実現でき、新たな設備を必要
としないので、極めて実用価値の高いものである。Such a mounting substrate for a semiconductor element and a columnar terminal of a pin grid array can be easily realized with conventional equipment for manufacturing a ceramic multilayer substrate, and require no new equipment. It is.
【図1】(a)〜(g)本発明の第1の実施例の柱状バ
ンプ形成工程および半導体実装工程を示す断面図FIGS. 1A to 1G are cross-sectional views showing a columnar bump forming step and a semiconductor mounting step according to a first embodiment of the present invention.
【図2】同基板上での柱状バンプの構成を示す断面図FIG. 2 is a sectional view showing a configuration of a columnar bump on the substrate.
【図3】同半導体素子を基板に実装した状態の構成を示
す断面図FIG. 3 is a cross-sectional view illustrating a configuration in which the semiconductor element is mounted on a substrate.
【図4】(a)〜(g)第2の実施例のピングリッドア
レイの柱状端子形成工程を示す断面図FIGS. 4A to 4G are cross-sectional views illustrating a step of forming a columnar terminal of the pin grid array according to the second embodiment.
【図5】(a)同4端子ピングリッドアレイの柱状端子
の構成を示す断面図 (b)同4端子ピングリッドアレイの側面図 (c)同多端子ピングリッドアレイの斜視図5A is a cross-sectional view showing the configuration of the columnar terminals of the four-terminal pin grid array. FIG. 5B is a side view of the four-terminal pin grid array. FIG. 5C is a perspective view of the multi-terminal pin grid array.
【図6】(a)〜(d)従来の半導体素子の実装工程を
示す断面図6 (a) to 6 (d) are cross-sectional views showing steps of mounting a conventional semiconductor device.
1 基板構成シート 2 バンプ形成用シート 3 高分子シート 4,5 導体ペースト 6 半導体素子 7 柱状バンプ 8 電極パッド 9 半田バンプ 10 基板 11 柱状端子 12 導体電極 13 金ワイヤ 14 ピングリッドアレイ本体 DESCRIPTION OF SYMBOLS 1 Substrate constitution sheet 2 Bump forming sheet 3 Polymer sheet 4, 5 Conductive paste 6 Semiconductor element 7 Columnar bump 8 Electrode pad 9 Solder bump 10 Substrate 11 Columnar terminal 12 Conductor electrode 13 Gold wire 14 Pin grid array main body
Claims (8)
対して上方に突出する柱状導体バンプとを備え、前記柱
状導体バンプが前記基板内部の内層導体パターンと直結
しており、前記柱状導体バンプ上に半導体素子の電極パ
ッドを接合してなる半導体素子実装基板。A substrate for mounting the claim 1 a semiconductor device, and a columnar conductor bumps projecting upward with respect to the substrate surface, the columnar conductor bump is directly connected to the previous SL substrate inside of the inner layer conductor pattern, the columnar A semiconductor element mounting substrate formed by bonding electrode pads of a semiconductor element on conductive bumps.
形成する工程と、前記両シートを孔開けし、前記孔を導
体ペーストで埋める工程と、前記2種類のシートのうち
バンプ形成用シートを最上層とし、複数の基板構成シー
トを下層として順次積層する工程と、積層した多層シー
トを焼成し、最上層を除去する工程と、最上層を除去す
ることにより形成した柱状バンプ上に半導体素子をフェ
ースダウンボンディング法により実装する工程を含む半
導体素子実装方法。2. A step of forming a substrate forming sheet and a sheet for forming a bump, a step of forming holes in both sheets and filling the holes with a conductive paste, and a step of forming a sheet for forming a bump among the two types of sheets. A step of sequentially laminating a plurality of substrate constituent sheets as an upper layer and a lower layer, a step of firing the laminated multilayer sheet and removing an uppermost layer, and a step of mounting a semiconductor element on a columnar bump formed by removing the uppermost layer. A semiconductor element mounting method including a step of mounting by a down bonding method.
より高い焼結温度を有し、バンプ形成用シートの燒結温
度と基板構成シートの燒結温度の中間の温度で焼結し、
未焼結のバンプ形成用シートを除去する請求項2記載の
半導体素子実装方法。3. The bump forming sheet has a higher sintering temperature than the substrate forming sheet, and is sintered at a temperature intermediate between the sintering temperature of the bump forming sheet and the sintering temperature of the substrate forming sheet.
3. The method according to claim 2, wherein the unsintered bump forming sheet is removed.
面に対して上方に突出する柱状端子とを備え、前記柱状
導体バンプが前記基板内部の内層導体パターンと直結さ
れた柱状端子付き基板。4. A substrate for mounting a semiconductor element, and a columnar pin that protrudes upwardly with respect to the substrate surface, the columnar conductor bump before Symbol pole terminals attached substrate directly connected with the inner layer conductor pattern in the substrate .
イであることを特徴とする請求項4記載の柱状端子付き
基板。5. The substrate with columnar terminals according to claim 4, wherein the columnar terminals are a multi-terminal pin grid array.
子が実装され、前記半導体素子の電極パッドと前記柱状
端子とが電気的に接続されている請求項5記載の柱状端
子付き基板。6. The substrate with columnar terminals according to claim 5, wherein a semiconductor element is mounted on a surface opposite to a surface on which the columnar terminals are provided, and an electrode pad of the semiconductor element is electrically connected to the columnar terminals.
を形成する工程と、前記両シートを孔開けし、前記孔を
導体ペーストで埋める工程と、前記2種類のシートのう
ち柱状端子形成用シートを最上層とし、複数の基板構成
シートを下層として順次積層する工程と、積層した多層
シートを焼成し、最上層を除去する工程を含む柱状端子
付き基板の製造方法。7. A step of forming a board-constituting sheet and a sheet for forming a pillar-shaped terminal, a step of making holes in both sheets and filling the hole with a conductive paste, and a sheet for forming a pillar-shaped terminal among the two types of sheets. A step of sequentially laminating a plurality of substrate constituent sheets as a lower layer and a step of firing the laminated multilayer sheet to remove the uppermost layer, and a step of removing the uppermost layer.
トより高い焼結温度を有し、柱状端子形成用シートの焼
結温度と基板構成シートの焼結温度の中間の温度で焼結
し、未焼結の柱状端子形成用シートを除去する請求項7
記載の柱状端子付き基板の製造方法。8. The columnar terminal forming sheet has a higher sintering temperature than the substrate forming sheet, and is sintered at a temperature intermediate between the sintering temperature of the columnar terminal forming sheet and the sintering temperature of the substrate forming sheet; The unsintered columnar terminal forming sheet is removed.
A method for producing a substrate with columnar terminals according to the above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01976692A JP3203731B2 (en) | 1992-02-05 | 1992-02-05 | Semiconductor element substrate and mounting method, substrate with columnar terminals and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01976692A JP3203731B2 (en) | 1992-02-05 | 1992-02-05 | Semiconductor element substrate and mounting method, substrate with columnar terminals and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05218133A JPH05218133A (en) | 1993-08-27 |
JP3203731B2 true JP3203731B2 (en) | 2001-08-27 |
Family
ID=12008464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP01976692A Expired - Lifetime JP3203731B2 (en) | 1992-02-05 | 1992-02-05 | Semiconductor element substrate and mounting method, substrate with columnar terminals and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3203731B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009031588A1 (en) | 2007-09-06 | 2009-03-12 | Murata Manufacturing Co., Ltd. | Circuit board, circuit module and circuit board manufacturing method |
WO2009031586A1 (en) | 2007-09-06 | 2009-03-12 | Murata Manufacturing Co., Ltd. | Circuit board and method for manufacturing circuit board |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0179404B1 (en) * | 1993-02-02 | 1999-05-15 | 모리시타 요이찌 | Ceramic substrate and manufacturing method thereof |
JPH1126631A (en) | 1997-07-02 | 1999-01-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JP4946225B2 (en) * | 2006-07-13 | 2012-06-06 | 株式会社村田製作所 | Multilayer ceramic electronic component, multilayer ceramic substrate, and method of manufacturing multilayer ceramic electronic component |
JP2008153359A (en) * | 2006-12-15 | 2008-07-03 | Sharp Corp | Semiconductor device and method of manufacturing semiconductor device |
WO2012023236A1 (en) | 2010-08-20 | 2012-02-23 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
WO2016194925A1 (en) * | 2015-06-03 | 2016-12-08 | 株式会社村田製作所 | Component-mounted substrate |
-
1992
- 1992-02-05 JP JP01976692A patent/JP3203731B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009031588A1 (en) | 2007-09-06 | 2009-03-12 | Murata Manufacturing Co., Ltd. | Circuit board, circuit module and circuit board manufacturing method |
WO2009031586A1 (en) | 2007-09-06 | 2009-03-12 | Murata Manufacturing Co., Ltd. | Circuit board and method for manufacturing circuit board |
US8279618B2 (en) | 2007-09-06 | 2012-10-02 | Murata Manufacturing Co., Ltd. | Circuit substrate and circuit substrate manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
JPH05218133A (en) | 1993-08-27 |
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