JP3199596B2 - Multilayer wiring board and package for housing semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board provided with a capacitor portion comprising a high dielectric layer and a pair of electrodes and a package for accommodating a semiconductor element. The present invention relates to a multilayer wiring board and a package having improved sealing performance and mechanical strength.

[0002]

2. Description of the Related Art In a semiconductor element storage package, a semiconductor element (integrated circuit) is liable to malfunction due to external noise or unnecessary radiation. Therefore, a capacitor section having a capacitance of about 30 to 100 .mu.F is conventionally provided between a power supply side and a ground side. Interposed between them to absorb noise and prevent malfunction. This capacitor generally consists of a ceramic dielectric sandwiched between a pair of electrodes. Conventionally, the connection of this capacitor was externally provided separately from the package, so that the mounting density could not be improved. .

As a method for solving such a defect, a capacitor section in which a dielectric layer such as alumina is sandwiched between a pair of electrode layers made of W or Mo between insulating layers mainly composed of alumina is used. A package for accommodating a semiconductor element mounted thereon is known (see Japanese Patent Application Laid-Open No. 62-169461).

Further, as a multilayer alumina wiring board,
For example, as disclosed in Japanese Patent Application Laid-Open No. 3-87091, a pair of electrode layers is formed on both sides by applying or printing a paste containing a high melting point metal such as W or Mo as a main component. 2. Description of the Related Art A multi-layer alumina wiring board is known in which a high dielectric layer containing a high dielectric constant imparting agent made of W or Mo is interposed between insulating layers containing alumina as a main component.

[0005]

However, the high dielectric layer provided in the conventional wiring board or the package for accommodating the semiconductor element has an unstable electric characteristic, and the electrode for sandwiching the high dielectric layer has a problem. The insulation resistance between the electrodes was reduced, and if the insulation resistance was significant, there was a risk of short-circuiting between the electrodes. Also,
The sealing property (airtightness) of the multilayer structure is also insufficient, and moisture permeates and changes the surface resistance of the electrode layer, or sufficient bonding between the electrode layer and the high dielectric layer or insulating layer There were drawbacks such as a lack of strength.

Further, components in the high dielectric layer, especially W and M
Components such as o easily diffuse into adjacent electrode layers and insulating layers, and conversely, high-melting metals such as W and Mo, which constitute the electrode layers, diffuse into the high dielectric layer, and the composition of the high dielectric layer As a result, the electrical characteristics of the dielectric layer change, and there is a problem that stable electrical characteristics such as relative permittivity cannot be obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a wiring board and a package for accommodating a semiconductor element having stable electric characteristics and excellent airtightness and mechanical strength while having a high dielectric layer inside. It is in.

Another object of the present invention is to obtain excellent adhesion, airtightness and interlayer adhesive strength between an electrode layer and a high dielectric layer or an insulating layer, and to provide a high dielectric layer of an electrode layer forming material. It is an object of the present invention to provide a wiring board and a semiconductor element storage package provided with a capacitor portion, which suppresses diffusion transfer of components, and can further suppress diffusion of components such as W and Mo into an insulating layer.

[0009]

[Means for Solving the Problems] The wiring board of the present invention comprises:
A wiring board comprising a capacitor portion having a high dielectric layer sandwiched between a pair of electrode layers, wherein the high dielectric layer comprises alumina particles, high dielectric constant imparting agent particles made of ZrO ₂ , and a grain boundary between these particles. And an oxide of at least one element selected from the group consisting of alkaline earth metals, rare earth elements, Al and Si, and a glass phase containing an oxide of Zr. It is composed of an oxide of at least one of metals, rare earth elements, Al and Si, and a glass phase containing an oxide of Zr.

[0010] The package for housing a semiconductor element according to the present invention comprises:
A semiconductor element housing package having a capacitor part in which a high dielectric layer is sandwiched between a pair of electrode layers, the semiconductor element housing package having a semiconductor element housing part, wherein the high dielectric layer is made of alumina particles and ZrO _2. And a glass phase containing an oxide of at least one element selected from the group consisting of alkaline earth metals, rare earth elements, Al and Si and an oxide of Zr present at the grain boundaries. The insulating layer is composed of alumina particles and a glass phase containing an oxide of at least one of alkaline earth metal, rare earth element, Al and Si and an oxide of Zr.

In the above-described wiring board and package for housing a semiconductor element, it is preferable that the high dielectric layer further contains at least one of W, Mo and Re as high dielectric constant imparting agent particles.

[0012]

The dielectric constant of an Al ₂ O ₃ sintered body is usually about 10, but the dielectric layer and a pair of electrodes are provided in or on a multilayer wiring board having the Al ₂ O ₃ sintered body as an insulating layer. In the case where the capacitor portion is formed by lamination, a high capacitance cannot be obtained when the dielectric layer is made of an Al ₂ O ₃ sintered body having the same composition as the insulating layer. Therefore, it is required to increase the dielectric constant of the stacked dielectric layers.

Therefore, when ZrO ₂ is added to Al ₂ O ₃ , the dielectric constant can be improved by increasing the amount of ZrO ₂ as shown in FIG.

[0014] However, the clamping is laminated on the insulating interlayer or substrate surface in the pair of electrodes Al ₂ O ₃ quality sintered body containing ZrO ₂ as a high-dielectric layer, ZrO ₂ is in the dielectric layer Once melted in the glass phase, it diffuses into the electrode layer and the insulating layer via the glass phase. Therefore, the amount of ZrO ₂ in the dielectric layer changes, and the dielectric characteristics of the dielectric layer become ZrO.
It will change gradually with the diffusion of O ₂ .

In the present invention, Al ₂ O containing ZrO ₂ is used.
ZrO in the insulating layer of the insulating substrate on which the _three dielectric layers are laminated.
By preliminarily containing a Zr component such as ₂ , the diffusion of the ZrO ₂ component in the dielectric layer to the electrode layer and the insulating layer can be prevented, and the characteristics of the dielectric layer can be stabilized, and the capacitor portion Reliability can be improved.

Further, according to the present invention, by including a glass phase in both the high dielectric layer and the insulating layer, the adhesion strength between each of the high dielectric layer, the insulating layer, the electrode layer and the wiring layer is improved. At the same time, the airtightness of the package can be improved.

Furthermore, the multilayer wiring board and the package of the present invention can be manufactured stably by preventing a change in the thickness of the dielectric layer of the capacitor portion during firing, and preventing a change in dielectric characteristics and warpage after firing. can do.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. (Structure of Multilayer Wiring Board) FIG. 1 is a view showing an example of a multilayer wiring board according to the present invention. According to FIG. 1, a capacitor section 6 composed of a high dielectric layer 3 and a pair of electrode layers 4 and 5 is laminated inside an insulating layer 2 in a wiring board 1. Further, a wiring layer 7 is provided on the surface or inside of the insulating layer 2. In the configuration of FIG.
And 5 are led out through the through holes 8 and 9 to the substrate surface.

Further, in the multilayer wiring board of the present invention, in addition to the capacitor portion 6 being sandwiched between the insulating layers 2 as shown in FIG. 1, for example, as shown in FIG. The electrode layer 5, the high dielectric layer 3, and the electrode layer 4 may be formed on the outermost surface of the formed insulating layer 2. in this case,
The capacitor section 6 may have a protective film formed of a resin or the like on the surface thereof so as not to come into contact with the outside air.

(Structure of Semiconductor Device Storage Package) FIG. 2 is a diagram showing an example of a semiconductor device storage package according to the present invention. According to FIG. 2, a plurality of insulating layers 11 are stacked on a substrate of the semiconductor storage package 10, and a wiring layer 12 is provided inside or on the surface of the insulating layer 11. Further, inside the insulating base, a capacitor section 16 is formed by the high dielectric layer 13 and a pair of electrode layers 14 and 15 sandwiching the high dielectric layer. Also, the insulating substrate 1
A recess (housing portion) 18 for housing the semiconductor element 17 is formed on the upper surface of the housing 0, and the housing portion 18 is sealed by a lid 19. The electrode layer 15 of the capacitor section 16
Are connected to a wiring layer through through holes 20. Further, in the configuration of FIG. 2, the electrode layer 14 of the capacitor section 16 is exposed to the storage section 18 to form a storage section bottom surface, and the semiconductor element 17 is mounted on the bottom surface. Note that the wiring layer 11 is connected to the external terminals 2 through through holes or the like.
1 electrically.

There are various types of semiconductor element storage packages as shown in FIGS. FIG.
In this package, the high dielectric layers 13 and the electrode layers 14 and 15 are alternately stacked below the semiconductor element 17, and these electrode layers 14 and 15 are connected to the semiconductor element 17 by through holes 20. It is a thing.

The package shown in FIG. 5 has a structure in which a capacitor section 6 in which electrode layers 14 and 15 are formed above and below a high dielectric layer 13 is sandwiched between insulating layers 11.
5 is connected to the semiconductor element 17 by a through hole 20.

In the package shown in FIG. 6, electrode layers 14 and 15 are formed above and below a high dielectric layer 13 below a semiconductor element 17, and these electrode layers 14 and 15 are formed by through holes 20. 17 and the pins 31 are fixed to the lower surface.
In a state where the semiconductor element 17 is not in contact with the semiconductor element 17, the semiconductor element 17 is connected to the semiconductor element 17 through a through hole 22 formed through the electrode layers 14 and 15 and the high dielectric layer 13.

In the package of FIG. 7, the capacitor portion 6 is formed by alternately stacking the high dielectric layers 13 and the electrode layers 14 and 15, and the electrode layers 14 and 15 are connected to the semiconductor element 17 through the through holes 20. Further, the semiconductor element 17 is fixed to the heat sink 23.

The package shown in FIG. 8 is a flat package, in which high dielectric layers 13 and electrode layers 14 and 15 are alternately laminated in layers. These electrode layers 13 and 14 are connected to the semiconductor element 17 by through holes 20. It is connected.

(High Dielectric Layer) In the above-mentioned wiring board and semiconductor device housing package of the present invention, the high dielectric layer (No. 3 in FIG. 1 and No. 13 in FIG. 2) forming the capacitor portion is made of Al ₂ O. _It consists of _three particles, ZrO ₂ particles and a glass phase present at the grain boundaries of these particles. Among them, ZrO ₂ particles have an effect of increasing the dielectric constant, and can give a relative dielectric constant of 10.8 or more, particularly a dielectric constant of 13 to 40, and ZrO ₂ particles include Y ₂ O _{3 and the} like. It is desirable to contain a stabilizer such as a Group 3a element oxide of the periodic table or an alkaline earth oxide such as CaO and MgO in order to stabilize the effect of imparting a high dielectric constant. Accordingly, ZrO ₂ is mainly composed of tetragonal and / or cubic crystals, and in some cases, monoclinic crystals may be slightly mixed. The stabilizer amount necessary to ZrO ₂ becomes the above crystalline form is dissolved, for example, Y ₂
In the case of O ₃ , it is added at a ratio of 5 to 15 mol%.

Further, at least one of W, Mo, and Re, which has the function of increasing the dielectric constant similarly to the ZrO ₂ particles, can be added to the high dielectric layer. At this time,
Since W, Mo, and Re are added as metal powder, added as oxide powder, or added as other compounds, they exist as a metal after firing. Good. When at least one of Mo, W, and Re is thus contained, it is desirable to add and contain Mo at a ratio of 5 to 30% by weight, W at a ratio of 5 to 50% by weight, and Re at a ratio of 10 to 60% by weight. . This means that Mo
If the content is more than 50% by weight, W is more than 50% by weight, or Re is more than 60% by weight, the insulation resistance is sharply reduced.

The sintering aid (glass component) of the high dielectric layer used in the present invention is a rare earth oxide such as SiO ₂ and / or Y ₂ O ₃ and an oxide of an alkaline earth metal oxide or B or Zn. It is desirable to use the compound in a weight ratio of 3: 1 to 5: 1.

Further, Al ₂ O ₃ particles and Z in the high dielectric layer
The glass phase intervening at the grain boundaries of the rO ₂ particles is added as an oxide of at least one of Si, alkaline earth metal and rare earth element, which is also added as a sintering aid, and as a high dielectric constant imparting agent. Since a small amount of ZrO ₂ is dissolved in the glass phase, the chemical resistance of the grain boundary is improved because it is formed as a reaction product with a part of the ZrO ₂ particles and a part of the alumina particles.

The composition of the above-mentioned high dielectric layer is, as oxides, 3 to 90% by weight of Al and 95 to 8% of Zr.
% Of at least one of Si, alkaline earth metal and rare earth metal as a sintering aid in a proportion of 2% by weight or more. In addition, oxides such as B and Zn can also be added as a sintering aid.

This is because when the Al content is less than 3% by weight, the difference in thermal expansion between the insulating layer and the high dielectric layer becomes large when the alumina-based sintered body is used for the insulating layer. Is difficult to form, and if it is more than 90% by weight, the effect of improving the dielectric constant becomes small. When Zr is less than 8% by weight, the effect of improving the dielectric constant is small,
This is because there is no clear difference from ordinary alumina porcelain that does not contain Zr. When the content is more than 95% by weight, the thermal expansion of the insulating layer and the high dielectric layer when the alumina-based sintered body is used as the insulating layer This is because the difference becomes large and it becomes difficult to form a good laminate. When an alumina-based sintered body mainly composed of Al ₂ O ₃ is used as the insulating layer, the amount of Zr in the high dielectric layer is desirably 30 to 70% by weight in terms of oxide.

Further, when at least one element selected from the group consisting of alkaline earth metals, rare earth elements and Si is less than 2% by weight in terms of oxides, generation of a stable grain boundary glass phase is reduced, and The joint strength between the electrode layer and the dielectric layer when co-firing with the layer is reduced.

In the present invention, the high dielectric layer Al ₂
The average crystal grain size of the O ₃ particles is ₃ to 20 μm, and ZrO 2
The average crystal grain size of the _two particles is desirably 1.5 to 20 μm.

The thickness of the high dielectric layer is appropriately determined depending on the required capacitance and the dielectric constant of the high dielectric layer.
For example, in a package or a substrate having a size of 1 to 2 inches square, a capacitance of several nF to several hundred nF can be obtained.

(Electrode Layer) On the other hand, the pair of electrode layers for sandwiching the dielectric layer to form a capacitor portion can be formed of a known metallized layer. For example, at least one of W, Mo and Re is a main component. Is preferable. Such an electrode layer is formed with a thickness of about 3 to 15 μm. One of the pair of electrode layers is electrically connected to a semiconductor element as a power supply layer and the other as a ground layer in a semiconductor storage package, and this capacitor portion may be used as a decoupling capacitor.

In addition, in the electrode layer, a component contained in the high dielectric layer or the insulating layer other than the above metal component is added at a ratio of 10% by weight or less, so that the electrode layer is in close contact with the high dielectric layer or the insulating layer. Can be enhanced.

If a metal having a lower thermal expansion than the high dielectric layer, such as W or Mo, is used as the electrode layer, a surface compressive stress is generated on the electrode layer side, so that the strength of the entire substrate can be increased. . Such surface compressive stress is W,
A similar strength improving effect can be obtained by using Al ₂ O ₃ instead of Mo and disposing it on the outermost layer of the high dielectric layer.

(Insulating Layer) Further, the insulating layer in the wiring substrate or the insulating substrate of the package for housing the semiconductor element is
It is mainly composed of Al ₂ O ₃ particles and / or ZrO ₂ particles and a glass phase present at the grain boundaries, and the glass phase is at least one element among alkaline earth metals, rare earth elements, Al and Si. It is important to include an oxide of Zr together with an oxide of Zr. This glass phase is composed of Si,
At least one of an alkaline earth metal and a rare earth element
It is composed of a reaction product of an oxide of an element and a part of ZrO ₂ particles or a part of Al ₂ O ₃ particles added as a high dielectric constant imparting agent.

The specific composition of the insulating layer is as follows: Al is 3 to 97.5% by weight in terms of oxide;
Zr is 0.5 to 95% by weight, and at least one element of Si, alkaline earth metal and rare earth element is 2-1 to
It is contained in a proportion of 0% by weight or more. In addition, oxides such as B and Zn can also be added as a sintering aid.

Here, if the Zr component is not contained in the insulating layer at all, the ZrO ₂ component in the high dielectric layer described above elutes into the insulating layer and the composition of the high dielectric layer changes, Stable dielectric properties cannot be obtained, for example, the thickness of the body layer itself becomes thin, and when Zr is excessively contained, the dielectric constant of the insulating layer becomes high. Therefore, it is desirable that the amount of Zr be 0.5 to 10% by weight in terms of ZrO ₂ at a portion where a wiring layer which needs to have a low dielectric constant is provided as an insulating layer. Conversely, where no wiring layer is formed and there is no problem even if the dielectric constant is high, there is no problem even if the Zr content is more than 10% by weight, and the same composition as the dielectric layer may be used. .

In a structure in which a high dielectric layer and an insulating layer having different thermal expansion characteristics are in direct contact with each other or via an electrode layer in a substrate, breakage due to thermal stress caused by a difference in thermal expansion is likely to occur. Therefore, in the multi-layer wiring board of FIG. 1, between the high dielectric layer 3, the electrodes 4, 5 and the insulating layer 2, and in the semiconductor element housing package of FIG. And the insulating layer 11, an intermediate layer having an intermediate composition such as a mixture of the composition of the high dielectric layer and the insulating layer may be interposed.

As described above, according to the present invention, by adding Zr to the insulating layer, the ZrO in the high dielectric layer can be formed.
_Although diffusion of ₂ can be prevented, as described above, a stabilizer for stabilizing ZrO ₂ is contained in ZrO ₂ in the dielectric layer. Therefore, ZrO in the insulating layer
_In order not to destabilize ₂ , it is desirable to slightly contain a stabilizer similar to the stabilizer contained in ZrO ₂ of the high dielectric layer. Examples of the compound serving as a stabilizer include rare earth element oxides such as MgO, CaO, and Y ₂ O ₃ .

(Wiring Layer) The wiring layer provided in the insulating layer is formed by a usual metallization method.
It can be formed of at least one metal selected from W, Mo, Re, Ni, Co, Cu and the like. This wiring layer generally has a thickness of about 3 to 50 μm and is formed between layers or on the surface of the insulating layer. However, when high output is required, the thickness may reach several mm.

(Manufacturing Method) The multilayer wiring board and the package for housing a semiconductor element according to the present invention are manufactured, for example, as follows. First, as an insulating layer, an average particle size of 5
3-97.5% by weight of alumina powder having a particle size of
O ₂ powder and 0.5 to 95 wt%, SiO _2, MgO,
Oxides of rare earth elements such as Y ₂ O ₃ and alkaline earth metals;
2 to 10% by weight of sintering aid such as oxides such as B and Zn
And, if necessary, Fe, Cr, Mn, Ti, Mo, W,
Metals such as Ni and Co, and coloring agents such as oxides, carbonates and acetates thereof are added and mixed in an amount of 5% by weight or less, and a binder such as butyral and acryl and a plasticizer such as DBP are added to the mixture. Further, after adding and mixing a solvent such as toluene and alcohol, a thickness of 0.1 to 1 m is obtained by a known molding method such as a doctor blade method or a calender roll method.
Then, a sheet-like molded product of m is prepared. The sintering aid in the sheet-like molded body for forming the insulating layer is SiO 2
Rare earth oxides such as ₂ and / or Y ₂ O ₃ and alkaline earth metal oxides are used in a weight ratio of 3: 1 to 6: 1, and ZrO ₂ may be added in an amount of 0.5% by weight or more. desirable.

A metallizing paste containing a metal component such as W, Mo, or Mo-Mn for forming a wiring layer is printed on the surface of the sheet-like molded body by a screen printing method or the like to form a wiring pattern. , Through holes are formed, and the through holes are also filled with the metallizing paste.

On the other hand, as a high dielectric layer, _{3 to} 90% by weight of alumina powder having a particle size of 5 μm or less and ZrO ₂ powder of 8 to 9%
5% by weight, alkaline earth metal components such as SiO ₂ , CaO, MgO and the like, rare earth oxides such as Y ₂ O ₃ , B, Zn
2% by weight or more of a sintering aid component composed of an oxide such as
In some cases, a metal of W or Mo or a compound of these compounds is mixed in the above ratio as a high dielectric constant improver, and if necessary, a metal such as Fe, Cr, Mn, Ti, Ni, Co,
A colorant containing an oxide, a salt or the like is added and mixed. Then, for example, a binder such as butyral or acryl or a plasticizer such as DBP is added as necessary, and a solvent such as toluene or alcohol is further added and mixed, and then a known method such as a doctor blade method or a calender roll method is used. The sheet is formed into a sheet having a thickness of 10 to 120 μm to prepare a sheet-like molded body for a high dielectric layer.

The ZrO ₂ powder to be added as a high dielectric constant imparting agent in the high dielectric layer contains 5 to 15 mol% of Y ₂ O _{3 in} advance.
It is desirable to use ZrO ₂ powder containing a cubic crystal stabilized by solid solution. The reason why the content of the stabilizer is 5 to 15 mol% is that if the content is less than 5 mol%, phase transformation from tetragonal to monoclinic is likely to occur, causing problems such as cracks. If the amount is more than mol%, the dielectric constant of ZrO ₂ itself decreases, and the effect of increasing the dielectric constant of the dielectric layer decreases.

It is to be noted that, even if stabilized or partially stabilized ZrO ₂ is not used as a raw material powder, an oxide of a stabilizer element and its compound necessary for stabilizing ZrO ₂ by blending are added, and the compound is stabilized in the firing step. You may make it.

On the upper and lower surfaces of the high dielectric layer sheet-like formed body produced as described above, W,
70 to 100% by weight of Mo or Re, if necessary
_{l 2 O 3, SiO 2,} ZrO 2, to alkaline earth metals, rare earth metals and their compounds such as 0 to 30 wt% additive comprising electrode layer forming paste coating.

Then, the high dielectric layer sheet-like molded body to which the electrode layer forming paste is applied is laminated together with the insulating layer sheet-like molded body, and pressed under a predetermined pressure.

When a thin high dielectric layer is formed, a paste for forming an electrode layer, a slurry for forming a high dielectric layer, and a paste for forming an electrode layer are formed on the surface of the insulating layer sheet. By sequentially performing the above steps. Also in this case, the sintering aid component added to the high dielectric layer is desirably 2% by weight or more.

The laminated body produced as described above is treated in a reducing atmosphere such as a humidified mixed gas of nitrogen and hydrogen.
By firing at a temperature of 00 ° C. or lower for 1 to 2 hours, a multilayer wiring board in which a capacitor portion in which a high dielectric layer is sandwiched between a pair of electrode layers is formed.
The firing temperature is set as a condition for simultaneously firing the insulating layer, the wiring layer, and the capacitor portion. If the firing temperature is lower than 1400 ° C., it becomes difficult to simultaneously fire the wiring layer and the electrode layer made of a high melting point metal. When firing at 1400 ° C. or lower, it is preferable to use metallization of Ni, Cu, or a mixture of these and a high melting point metal powder as the wiring layer.

The capacitor section may be formed by alternately laminating high dielectric layers and electrode layers, and a high capacitance can be obtained by such a laminated structure.

In the case of manufacturing a semiconductor housing package, in addition to the above-described method of manufacturing a multilayer wiring board, an insulating layer is formed to form a recess 18 for housing a semiconductor element in FIG. Are laminated and press-bonded, and simultaneously baked to produce a wiring board. Then, a separately prepared lid is sealed with Au-Sn braze, solder, low-melting glass, welding (seam weld) so as to seal the recess of the wiring board. ) Can be obtained by closely adhering to an insulating substrate.

The following experiment was conducted to confirm the effects of the present invention. Experiment 1 First, the relationship between the composition of the dielectric layer and the dielectric constant was examined by the following method. Si as a sintering aid as a dielectric layer
₂ % by weight of O ₂ , 0.5% by weight of CaO and 0.5% by weight of MgO, 3% by weight in total, 15 to 90% by weight of the average particle size ZrO ₂ powder stabilized by Y ₂ O _3, and the average A composition composed of Al ₂ O ₃ powder having a diameter of 3 μm and a composition containing 100% by weight of the above ZrO ₂ powder were prepared.
The change in the dielectric constant with the change in the amount of O ₂ was measured. Note that Y
_{As the 2} O ₃ stabilized ZrO ₂ , the content of Y ₂ O ₃ is 5
Mole%, 8 mol%, 10 mol%, and 15 mol% powder were used.

This dielectric layer was mixed with the above composition, a binder made of butyral was added thereto, and toluene and alcohol were further added and mixed. Then, a sheet-like molded body for a high dielectric layer was formed by a doctor blade method. An electrode layer paste made of metal W was formed on the upper and lower surfaces of the molded body.
Printing was performed by a screen printing method in a size of 5 mm × 25 mm. This was simultaneously fired in a reducing atmosphere at 1550 ° C. for 2 hours to form a capacitor in which a 35 μm thick high dielectric layer was sandwiched between 5 μm electrode layers.

This capacitor was measured using an LCR meter (YHP4284A) to measure
The capacitance at 25 ° C. was measured under the condition of 1.0 Vrm, and the relative dielectric constant at 25 ° C. was calculated from the capacitance. The results are shown in FIG.

As is apparent from the results shown in FIG. 8, ZrO ₂
As the addition amount of Zr increases, the relative dielectric constant increases, and Zr
It can be seen that the smaller the amount of solid solution of Y ₂ O ₃ in O ₂ , the higher the relative dielectric constant.

Experiment 2 Next, 48.5% by weight of stabilized ZrO ₂ containing 8 mol% of Y ₂ O _{3 and} 48.5% by weight of Al ₂ O _{3 were} used as a high dielectric layer, and SiO ₂ was used as a sintering aid. Ratio of metal powder of W, Mo, Re to 0 to 60 parts by weight based on 100 parts by weight of a total of 3% by weight of 2% by weight, 0.5% by weight of CaO and 0.5% by weight of MgO. The change in the relative dielectric constant was measured in exactly the same manner as in Experiment 1 except that the one added in Example 1 was used, and the results are shown in FIG. WO ₃ , Mo
O ₃ and Re ₂ O _{7 in} the form of an oxide powder with a metal conversion amount of 0
The relative dielectric constant when an amount of ６０60 parts by weight was added was measured in the same manner, and shown in FIG.

9 and 10, the relative dielectric constant is further improved by adding W, Mo, and Re in addition to ZrO ₂ as high dielectric constant imparting agent particles.
It can be seen that the relative dielectric constant increases as the amounts of o and Re added increase.

In the above experiment, when the amount of Mo added is more than 30% by weight, when the amount of W added is more than 50% by weight, when the amount of Re added is more than 60% by weight, The insulation resistance suddenly decreased, and many short-circuits increased, making it impossible to measure the relative dielectric constant.

Experiment 3 The inventor conducted the following experiment in order to confirm the diffusion of ZrO ₂ in the high dielectric layer into the insulating layer.

First, alumina powder 48.5 having a particle size of 3 μm was used.
% By weight, 2% by weight of SiO ₂ as a sintering aid, CaO
0.5% by weight, 0.5% by weight of MgO, 3% by weight in total, and Z
48.5 wt% of partially stabilized ZrO ₂ (8YSZ) powder stabilized with 8 mol% of Y ₂ O ₃ with respect to the total amount of rO ₂ was added and mixed, and a binder made of butyral was added thereto. After adding and mixing the toluene and the alcohol, the sheet was formed into a sheet by a doctor blade method to prepare a 50 μm sheet-like molded body for a high dielectric layer.

An electrode layer paste containing 2% by weight of metal W and Al ₂ O ₃ powder was prepared on the upper and lower surfaces of the sheet-like molded body for a high dielectric layer, and the electrode paste was applied by a screen printing method. Then, this is normally fired at 1550 ° C. for 2 hours in a humidified nitrogen / hydrogen mixed gas (reducing atmosphere) to obtain a high dielectric layer having a thickness of 40 μm and an electrode layer having a thickness of 5 μm.
A capacitor having a thickness of m was prepared. The relative permittivity of this capacitor was measured in the same manner as in Experiment 1, and it was found that
It was 6.

Next, as an insulating layer, A having an average particle size of 3 μm was used.
93 wt% of l ₂ O ₃ powder and ZrO ₂ (8 mol% Y ₂
O ₃ content) 1% by weight, Y ₂ O ₃ as a sintering aid 2.0% by weight, SiO ₂ 3.0% by weight, CaO 0.5% by weight, M
A binder made of butyral was added to a mixture consisting of 0.5% by weight of gO and 6% by weight in total, and toluene was further added and mixed. Then, a sheet was formed by a doctor blade method, and a sheet-shaped molded product for an insulating layer having a thickness of 500 μm was obtained. Created. Then, a sheet-like molded product for a high dielectric layer having the same composition as described above is produced, and a through-hole is formed in the sheet-shaped molded product for a high dielectric layer and the sheet-shaped molded product for an insulating layer. Was filled with W paste. In addition, a W paste obtained by adding Al ₂ O ₃ to metal W by 2% by weight was printed on the electrode layer pattern on the upper and lower surfaces of the sheet-like formed body for a high dielectric layer by a screen method.

Then, the sheet-like molded body for a high dielectric layer is sandwiched from above and below by two sheet-like molded bodies for an insulating layer, laminated and pressed, and heated at 1550 ° C. in a humidified mixed gas of nitrogen and hydrogen. High-dielectric layer 40 after normal firing for 2 hours
A multilayer wiring board with a built-in capacitor having a thickness of 5 μm, an electrode layer of 5 μm, and an insulating layer of 1.6 μm was produced. The relative dielectric constant of this substrate was measured in the same manner as in Experiment 1 above, and it was 16 and the substrate had the high dielectric constant's original relative dielectric constant even when sandwiched between insulating layers. In addition, as a result of performing quantitative analysis using a wavelength dispersive X-ray microanalyzer, it was confirmed that there was no change in the composition of the high dielectric layer.

In Experiment 3, a 500-μm-thick sheet-shaped molded article having the exact same composition as the sheet-shaped molded article for the high-dielectric layer was prepared as the sheet-shaped molded article for the insulating layer. The same evaluation was performed on the sheet-like molded body, which was laminated and pressed on the sheet-like molded body for a high dielectric layer on which the above-mentioned electrode layer paste was printed on both sides, and then fired simultaneously at a temperature of 1550 ° C. for 2 hours. When I went,
The same result as above was obtained.

As a comparative experiment, as a sheet-like molded product for an insulating layer, 94% by weight of Al ₂ O ₃ powder having an average particle size of 3 μm without adding ZrO ₂ and Y ₂ O as a sintering aid were used.
₃ with a composition of 2% by weight, 3% by weight of SiO ₂ , 0.5% by weight of CaO, and 0.5% by weight of MgO in a total of 6% by weight. Was prepared, and the relative permittivity was measured in the same manner.

As a result, the relative dielectric constant was 15, which was lower than the case where ZrO ₂ was added to the above-mentioned insulating layer, and the thickness of the high dielectric layer after sintering was reduced. 30
μm. In addition, as a result of line analysis using an X-ray microanalyzer on the cross section, it was confirmed that Zr in the high dielectric layer was diffused into the insulating layer.

[0070]

As described in detail above, in the multilayer wiring board and the package of the present invention, the components in the high dielectric layer can be suppressed from diffusing into the insulating layer, so that the composition and thickness of the high dielectric layer change. Therefore, a desired relative permittivity can be obtained, long-term stability of electrical characteristics can be achieved, and reliability of a substrate or a package can be improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing one embodiment of a multilayer wiring board of the present invention.

FIG. 2 is a longitudinal sectional view showing an embodiment of a package for housing a semiconductor element according to the present invention.

FIG. 3 is a longitudinal sectional view showing another embodiment of the multilayer wiring board of the present invention.

FIG. 4 is a longitudinal sectional view showing another example of the semiconductor device housing package of the present invention.

FIG. 5 is a longitudinal sectional view showing still another embodiment of the package for housing a semiconductor element of the present invention.

FIG. 6 is a longitudinal sectional view showing still another embodiment of the semiconductor device housing package of the present invention.

FIG. 7 is a longitudinal sectional view showing still another embodiment of the package for housing a semiconductor element of the present invention.

FIG. 8 is a longitudinal sectional view showing still another embodiment of the semiconductor device housing package of the present invention.

FIG. 9 is a diagram showing the relationship between the amount of ZrO ₂ in a high dielectric layer and the relative dielectric constant.

FIG. 10 is a graph showing the relationship between the amount of Mo, the amount of W, and the amount of Re when the amount of Mo is further added to the high dielectric layer and the relative dielectric constant.

FIG. 11 shows that MoO ₃ , WO ₃ , R
It is a diagram showing the relationship between the amount of these to be added (in terms of metal amount) and the relative dielectric constant in the case of adding e ₂ O _7.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer wiring board 2,11 Insulating layer 3,13 High dielectric layer 4,5,14,15 Electrode layer 6,16 Capacitor part 7,12 Wiring layer 8,9,20,22 Through hole 10 Semiconductor package 17 Semiconductor element 18 Recess (storage part) 19 Lid 21 External terminal 23 Heat sink

Continuation of the front page (56) References JP-A-6-223625 (JP, A) JP-A-6-29420 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H05K 3 / 46 H01L 23/12

Claims (4)

(57) [Claims] An Al ₂ O ₃ particle and / or a ZrO ₂ particle are mixed with an alkaline earth metal, a rare earth element, Al and Si.
Al ₂ O ₃ particles are formed inside or on an insulating substrate having a metallized wiring layer disposed on an insulating layer and / or a surface made of an oxide of at least one element and a glass phase containing an oxide of Zr. A ZrO ₂ particle and a glass phase containing an oxide of at least one element selected from the group consisting of alkaline earth metals, rare earth elements, Al and Si and an oxide of Zr, and a ZrO ₂ Wherein a capacitor portion sandwiched between a pair of electrode layers is laminated. 2. The method according to claim 2, wherein said high dielectric layer contains W, Mo and Re.
2. The wiring board according to claim 1, wherein the wiring board contains at least one of the following. 3. Al ₂ O ₃ particles and / or ZrO ₂ particles, and alkaline earth metal, rare earth element, Al and Si
A metallized wiring layer inside or on a surface of a ceramic insulator made of an oxide of at least one element and a glass phase containing an oxide of Zr, and a housing part for housing a semiconductor element. an insulating substrate, a semiconductor element housing package comprising a lid, the interior or surface of the insulating substrate, and Al ₂ O ₃ particles, ZrO ₂
A pair of electrodes composed of a particle and a high-dielectric layer formed of a glass phase containing an oxide of at least one element selected from the group consisting of alkaline earth metals, rare earth elements, Al and Si and an oxide of Zr, which are present at these grain boundaries; A package for accommodating a semiconductor element, wherein a capacitor portion sandwiched between layers is laminated. 4. The method according to claim 1, wherein said high dielectric layer contains W, Mo and Re.
4. The package for housing a semiconductor element according to claim 3, wherein the package contains at least one of the following.