JP3339984B2 - Capacitor material, multilayer alumina wiring board, and package for housing semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer alumina wiring board containing a capacitor material and a high dielectric layer, and a package for accommodating a semiconductor element.

[0002]

2. Description of the Related Art Conventionally, for example, in a package for housing a semiconductor element, a semiconductor IC (integrated circuit) is liable to malfunction due to external noise or unnecessary radiation. Therefore, a ceramic capacitor having a capacitance of about 30 to 100 .mu.F is grounded to a power supply side. By inserting between them, noise was absorbed and malfunction was prevented. Conventionally, the connection of the capacitor was made externally separately from the package, so that the mounting density could not be improved.

From such a viewpoint, a package incorporating a capacitor has recently been developed (Japanese Patent Laid-Open No. Sho 62-62).
169461). In the disclosed packages in this publication, it is interposed between the insulating layers of dielectric layer of Al ₂ O ₃ which is sandwiched by a pair of electrodes made of Al ₂ O _3.

In such a package, a capacitor can be built-in. However, since the relative dielectric constant of Al ₂ O ₃ constituting the dielectric layer is as low as about 9.5 to 10, the area of the dielectric is required to obtain a large capacitance. And it is necessary to form a plurality of dielectric layers sandwiched by the electrodes. For this reason, there has been a problem that the size of the package or the substrate increases and the cost increases.

In recent years, for example, Japanese Patent Laid-Open Publication No.
As disclosed in Japanese Patent No. 7091, Mo is added to Al ₂ O ₃ .
It has been proposed to increase the relative dielectric constant by adding a metal such as W or W.

[0006]

However, in recent years, a higher dielectric constant has been required for a capacitor incorporated in a package.
The dielectric material disclosed in Japanese Patent No. 87091 has a problem that the relative dielectric constant is still low.

[0007]

Means for Solving the Problems The present inventors have thoroughly studied the above problems, and as a result, the increase in the dielectric constant by adding a metal occurs at the interface between two materials having different conductivity. Since it is caused by interfacial polarization, the contact state of the interface is TiO
₂ , Nb ₂ O ₅ , and Ta ₂ O ₅
The inventors have found that it is possible to further increase the relative permittivity, and have reached the present invention.

That is, the capacitor material of the present invention comprises 40 to 95% by weight of Al ₂ O ₃ containing a sintering aid, TiO ₂ , N
When at least one component selected from b ₂ O ₅ and Ta ₂ O ₅ is 2% by weight or less (excluding 0), the balance is Mo,
It is composed of at least one metal selected from W and Re.

Further, the multi-layer alumina wiring board of the present invention comprises a capacitor portion having a high dielectric layer sandwiched between a pair of electrode layers provided on an insulating layer mainly composed of Al ₂ O _3. A substrate, wherein the high dielectric layer comprises:
40 to 95% by weight of Al ₂ O ₃ containing a sintering aid and TiO
₂ , ₂ % by weight or less (not including 0) of at least one component selected from Nb ₂ O ₅ and Ta ₂ O _5, and the balance being at least one metal selected from Mo, W and Re. is there.

Further, in the package for accommodating a semiconductor element according to the present invention, a capacitor section in which a high dielectric layer is sandwiched between a pair of electrode layers is provided on an insulating layer mainly composed of alumina. A package for accommodating a semiconductor device, wherein the high dielectric layer includes a sintering aid.
40 to 95% by weight of l ₂ O ₃ and at least one component selected from TiO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅
% By weight (not including 0), and the balance consists of at least one metal selected from Mo, W and Re.

The capacitor material of the present invention comprises Al ₂ O ₃ containing a sintering aid, TiO ₂ , Nb ₂ O ₅ and Ta ₂ O.
₅ and at least one metal selected from Mo, W and Re. The reason why Al ₂ O ₃ containing a sintering aid is 40 to 95% by weight is as follows. If the amount of Al ₂ O ₃ containing the sintering aid is less than 40% by weight, the metal component is connected to lower the insulating property, and if it is more than 95% by weight, the effect of increasing the dielectric constant does not appear. Because. Al ₂ O ₃ containing sintering aid is
In order to maintain a high relative dielectric constant and insulating properties even when processed to be thin, it is desirable that the content be 55% by weight or more, particularly 60 to 90% by weight.

Further, TiO ₂ , Nb ₂ O ₅ and Ta ₂
The reason that at least one component selected from O ₅ is contained in an amount of 2% by weight or less (not including 0) is that even when a small amount is added, the effect of increasing the dielectric constant is obtained. This is because the insulation property deteriorates. TiO ₂ , N
component of at least one member selected from b ₂ O ₅ and Ta ₂ O ₅ is desirably contains 0.05 to 2 wt%.

The balance is made of at least one metal selected from Mo, W and Re, because the addition of these metals greatly improves the dielectric constant. M
The content of at least one metal selected from o, W and Re is preferably 5 to 30% by weight, particularly 10 to 20% by weight in the case of Mo, and 5 to 30% by weight in the case of W.
To 50% by weight, particularly preferably 20 to 35% by weight.
In the case of e, 5 to 60% by weight of the total amount, especially 25 to 40%
Desirably, it is contained by weight.

A multilayer alumina wiring board and a package for accommodating a semiconductor element according to the present invention are provided with a capacitor section in which a high dielectric layer is sandwiched between a pair of electrode layers, on an insulating layer mainly composed of Al ₂ O _3. Specifically, it is formed as follows.

That is, alumina powder having a particle size of 5 μm or less
And 8-96% by weight, and SiO _2, CaO, sintering aids alumina such as MgO 0.1 to 20 wt%, TiO _2, N
at least one component of b ₂ O ₅ and Ta ₂ O ₅
Add by weight or less. Chromium oxide if necessary,
A coloring agent such as Mo or W is added and mixed in an amount of 0.5 to 10% by weight, and a binder such as an acrylic resin or DBP is added thereto.
And a solvent such as toluene and alcohol are added and mixed, and then formed into a sheet having a thickness of 0.2 to 1 mm by a known method such as a doctor blade method. By laminating a plurality of such green sheets, an insulating layer molded body is produced.

The alumina sintering aid such as SiO ₂ , CaO, MgO or the like is used in an amount of 0.1 to 20% by weight and a particle size of 5 μm.
A total of 40 to 95% by weight of the following alumina powder and Mo
5 to 30% by weight for W, 5 to 50% by weight for W, Re
And at least one metal component of 5 to 60 wt% _{for, TiO 2, Nb 2 O 5} , Ta 2 and 2 wt% or less of at least one component of O _5, chromium oxide and the like, if necessary And a binder such as butyral or an acrylic resin, or a plasticizer such as DBP, and a solvent such as toluene and alcohol. The sheet is formed into a sheet having a thickness of 0.02 to 0.07 mm by the known method described above to produce a high dielectric layer molded body.

Then, through holes are formed in the high dielectric layer molded body and the insulating layer molded body, and filled with a high melting point metal paste such as W, Mo, and Re.

Thereafter, for example, 90 to 100% by weight of metal Re, W and Mo, and optionally alumina or the above-mentioned sintering aid component of alumina are added to the upper and lower surfaces of the high dielectric layer molded body, respectively. An electrode layer paste containing 10 to 10% by weight is applied. Then, the high dielectric layer molded body coated with the electrode layer paste is interposed between the insulating layer molded bodies and heated,
Pressure is applied at a predetermined pressure to perform pressure bonding.

After that, by degreased in a humidified mixed gas of nitrogen and hydrogen and baked normally for 1 to 2 hours, the high dielectric layer has a thickness of 15 to 55 μm between the insulating layers and the electrode layer has a thickness of 2 to 55 μm.
A multilayer alumina-based wiring board and a semiconductor element housing package interposed with a thickness of about 15 μm are obtained.

The high dielectric layer molded body may be formed by preparing a plurality of sheets as described above and alternately laminating these sheets and electrode layers. In such a case, the capacitance can be improved.

TiO ₂ , Nb ₂ O of ₂ % by weight or less
₅ , at least one component of Ta ₂ O ₅ is added only to the insulating layer or only to the high dielectric layer,
It may be added only to the electrode layer. This is because, by firing, 2 wt% or less of TiO ₂ , N is contained in the final sintered body of the high dielectric layer.
This is because at least one component of b ₂ O ₅ and Ta ₂ O ₅ is present.

Further, Re, W, and Mo may be added in a metal state or in an oxide state. Even if one or more of Re, W, and Mo as high dielectric constant imparting agents are added, the dielectric constant of the high dielectric layer can be increased.

The high dielectric layer may contain a sintering aid, a coloring agent, or the like.

[0024]

According to the capacitor material of the present invention, 40 to 95% by weight of Al ₂ O ₃ containing a sintering aid, TiO ₂ , Nb ₂ O ₅
And at least one component selected from Ta ₂ O ₅ and 2% by weight or less, and the balance is at least one metal selected from Mo, W and Re, so that the relative dielectric constant can be significantly improved. This is the conductive Mo,
W and Re are dispersed in the material without reacting with the alumina, and the relative dielectric constant increases due to the effect of apparently reducing the thickness and the interface polarization generated at the interface between materials having different conductivity.
By adding TiO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅ , the polarizability at the interface is increased, and the relative dielectric constant can be further improved.

Further, the capacitor material of the present invention can be incorporated in a multilayer alumina wiring board and a package for accommodating a semiconductor element by simultaneous firing, and such a high dielectric layer can be formed in the multilayer alumina wiring board and a semiconductor element accommodating package. By incorporating the semiconductor IC in the package, the wiring board or the package has heat dissipation properties, and the semiconductor IC can be prevented from malfunctioning due to external noise or unnecessary radiation.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer alumina wiring board according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a multilayer alumina wiring board of the present invention. In the figure, a multilayer alumina wiring board is composed of a high dielectric layer 11 and an insulator layer 13 laminated on the high dielectric layer 11. High dielectric layer 1
Electrode layers 15 are formed on the upper and lower sides of 1.

The high dielectric layer 11 is obtained by first forming a high dielectric layer molded body. The high dielectric layer molded body is
6: 1: 1 SiO ₂ , CaO, MgO as sintering aid
79% by weight of a total of 4% by weight of alumina powder having a particle size of 5 μm or less, 17% by weight of Mo powder as a high dielectric constant imparting agent, and 1% by weight of TiO ₂ powder as an interfacial polarization improving agent. And Cr ₂ O ₃ powder as a coloring agent.
% By weight, and thoroughly dispersed and mixed in a known solvent such as toluene or alcohol. A known binder such as an acrylic resin or a butyral resin and a known plasticizer such as DBP are added and mixed. A sheet was formed by a blade method to obtain a high dielectric layer molded body.

As an additive such as a sintering aid, powder having an average crystal grain size smaller than 3 μm or less than alumina powder was used. Mo, CaO and MgO are MoO ₃ , CaCO ₃ ,
MgCO ₃ powder was used after being converted into Mo, CaO, and MgO.

On the other hand, the insulator layer 13 can also be obtained by producing an insulating layer molded body. The insulating layer molded body was improved in interfacial polarization by adding SiO ₂ , CaO, and MgO as sintering aids in a ratio of 6: 1: 1 in total of 5% by weight and a total of 96% by weight of alumina powder having a particle size of 5 μm or less. 1% by weight of TiO ₂ powder as a coloring agent (which also has a coloring effect) and C as a coloring agent
r ₂ O ₃ powder was added in an amount of 3% by weight and thoroughly dispersed and mixed in a known solvent such as toluene or alcohol, and then mixed with a known binder such as an acrylic resin or a butyral resin.
A known plasticizer such as BP was added and mixed, and then sheeted by a doctor blade method to obtain a molded insulating layer.

As an additive such as a sintering aid, powder having a size of 3 μm or less smaller than alumina powder was used. Also, CaO, M
gO was obtained by converting CaCO ₃ and MgCO ₃ powder into CaO and MgO.

In the molded article of the high dielectric layer and the molded article of the insulating layer, Cr ₂ O ₃ was used as a coloring agent. If necessary, metals such as Mo, W, Ni, Co, Mn and Fe and oxides thereof were used. , Hydroxide, nitrate, carbonate and the like. When forming the sheet, other known agents such as a dispersant, an antifoaming agent, a surfactant, and an antistatic agent may be added as necessary.

Then, through-holes are formed in the insulating layer molded body and the high dielectric layer molded body, and filled with a high melting point metal paste such as W or Mo.

Thereafter, at least one of the metals Re, Mo, and W is used as a main component on the upper and lower surfaces of the high dielectric layer molded body,
An additive mainly composed of Al ₂ O ₃ is added to the metal in an amount of 1%.
An electrode layer paste containing about 10% by weight to about 10% by weight is screen-printed to form an electrode layer having a thickness of about 8 μm.

Then, the high dielectric layer molded body coated with the electrode layer paste is interposed between the insulating layer molded bodies. Thereafter, degreasing is performed in a humidified mixed gas of nitrogen and hydrogen, and normal firing is performed at a maximum temperature of about 1600 ° C. for 2 hours to obtain a multilayer alumina wiring board of the present invention.

By the way, the present inventors, in order to confirm the effect of adding W, Mo, and Re in the present invention, to Al containing 1 wt% of TiO ₂ and containing 4 wt% of the same sintering aid as above.
W, Mo, and Re are contained in ₂ O ₃ ,
Experiment 1 was conducted in which the relative permittivity was measured by changing the contents of Mo and Re. The result is shown in FIG.

In Experiment 1, the thickness of the high dielectric layer was 35 μm, and the electrode shape was 25 mm on both sides of the dielectric layer.
An electrode layer made of a metal W of × 25 mm × 6 μm was formed. The measurement was performed using an LCR meter (YHP4284).
A) was carried out, the capacitance at 25 ° C. was measured under the conditions of 100 kHz and 1.0 Vrsm, and the relative dielectric constant at 25 ° C. was measured from the capacitance.

It can be seen from the graph of FIG. 2 that the relative dielectric constant increases as the content of W, Mo, and Re increases. FIG. 2 shows the case where two types of W and Mo are contained at a ratio of 1: 1.

Further, the present inventors have determined that Ti
In order to confirm the effect of adding the interfacial polarization improver composed of O ₂ , Nb ₂ O _5, and Ta ₂ O _5, an experiment 2 in which the content of the interfacial polarization improver was changed in the above example was performed. At this time, an interfacial polarization improving agent was added and contained based on a sample having a Mo content of 17% by weight, a W amount of 32% by weight, or a Re amount of 45% by weight and a relative dielectric constant of 16. The relative permittivity in this case was measured and is shown in FIG. In Experiment 2, a high dielectric layer and an electrode layer were formed as in Experiment 1, and the relative dielectric constant was determined as in Experiment 1.

As shown in the graph of FIG.
It can be seen that in any case of using either o or Re, the relative dielectric constant increases as the content of the interfacial polarization improver increases. Further, the present inventors have proposed that TiO ₂ ,
An experiment was conducted in which an interfacial polarization improver consisting of Nb ₂ O ₅ and Ta ₂ O ₅ was added in an amount of 2% by weight or more. As a result, the insulation resistance of the capacitor was lowered, and application to a multilayer substrate was difficult.

In the above embodiment, the multilayer alumina wiring board has been described. However, the package for accommodating the semiconductor element can be formed in substantially the same manner. Also, Ti
O ₂ , Nb ₂ O ₅ , and Ta ₂ O ₅ can be used as long as the raw material powder is added in any form, such as metal, nitride, and carbide, as long as it can be finally converted into an oxide form by firing. The same effect can be obtained even if it is added in such a form. This is because the oxide is oxidized into an oxide by firing in a steam-containing atmosphere.

Incidentally, as a package for housing a semiconductor element, there is a configuration as shown in FIGS. 4 to 8 show a pin grid array (PGA) type package, and FIG. 9 shows a flat package.

In the package of FIG. 4, the lower surface of the semiconductor element 21 and the upper electrode layer 23 are connected by a conductive material, and the lower electrode layer 25 is connected to the semiconductor element 21 by a through hole.

In the package shown in FIG. 5, high dielectric layers 27 and electrode layers 29 are alternately stacked below the semiconductor element 21, and these electrode layers 29 are connected to the semiconductor element 21 through through holes. I have.

In the package of FIG. 6, electrode layers 29 are formed above and below the high dielectric layer 27 below the semiconductor element 21, and these electrode layers 29 are connected to the semiconductor element 21 by through holes. I have.

In the package shown in FIG. 7, electrode layers 29 are formed above and below the high dielectric layer 27 below the semiconductor element 21, and these electrode layers 29 are connected to the semiconductor element 21 through through holes. Further, the pins 31 are fixed to the lower surface, and the through holes which are passed without contacting the electrode layer 29 are connected to the pins 31.

In the package shown in FIG. 8, high dielectric layers 27 and electrode layers 29 are alternately stacked.
Are connected to the semiconductor element 21 by through holes, and the semiconductor element 21 is fixed to a heat sink 33.

The package shown in FIG. 9 is a flat package in which high dielectric layers 27 and electrode layers 29 are alternately laminated, and these electrode layers 29 are connected to the semiconductor element 21 through through holes.

Incidentally, a high dielectric layer may be formed on a lid of a package for housing a semiconductor element by using the capacitor material of the present invention. In this case, the lid has a structure in which a high dielectric layer having electrode layers formed on both surfaces is sandwiched between insulating layers mainly composed of alumina. FIG. 10 shows a case where a high dielectric layer is formed on the lid. In FIG. 10, a high dielectric layer 2
7 is formed, and the high dielectric layer 27 is
It is pinched by.

[0050]

As described above in detail, the capacitor material according to the present invention is characterized in that Al ₂ O ₃ containing a sintering aid is 40 to 95% by weight.
And at least one component selected from TiO ₂ , Nb ₂ O ₅ and Ta ₂ O _{5 in} an amount of 2% by weight or less (excluding 0)
And the balance is at least one metal selected from Mo, W and Re, so that the relative dielectric constant can be greatly improved. In addition, the high dielectric layer made of the capacitor material can be incorporated into the multilayer alumina wiring board and the package for housing the semiconductor element by simultaneous firing, so that the wiring board or the package has a heat dissipation property and the semiconductor IC can be connected to the outside. It is possible to prevent a malfunction from occurring due to noise or unnecessary radiation.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a multilayer alumina wiring board of the present invention.

FIG. 2 shows W, Mo, and Re when TiO ₂ is 1% by weight.
3 is a graph showing the relationship between the content and relative dielectric constant.

FIG. 3 shows Ti added to Al ₂ O ₃ containing 17% by weight of Mo, 32% by weight of W, or 45% by weight of Re.
₅ is a graph showing the relationship between the content and the relative permittivity when O ₂ , Nb ₂ O ₅ , and Ta ₂ O ₅ are added and contained.

FIG. 4 is a longitudinal sectional view showing an embodiment of a semiconductor element storage package according to the present invention.

FIG. 5 is a longitudinal sectional view showing another embodiment of the semiconductor device housing package of the present invention.

FIG. 6 is a longitudinal sectional view showing still another embodiment of the semiconductor device housing package of the present invention.

FIG. 7 is a longitudinal sectional view showing still another embodiment of the package for housing a semiconductor element of the present invention.

FIG. 8 is a longitudinal sectional view showing still another embodiment of the semiconductor device housing package of the present invention.

FIG. 9 is a longitudinal sectional view showing an embodiment of a flat type semiconductor element housing package of the present invention.

FIG. 10 is a longitudinal sectional view showing an example in which a high dielectric layer is formed on a lid of a package for housing a semiconductor element.

[Explanation of symbols]

 11, 27 High dielectric layer 13 Insulator layer 15, 23, 25, 29 Electrode layer

Continued on the front page (51) Int.Cl. ⁷ Identification code FI H05K 3/46 H05K 3/46 T C04B 35/10 D H01L 23/14 M

Claims (3)

(57) [Claims] 1. An aluminum oxide containing 40 to 95% by weight of Al ₂ O ₃ containing a sintering aid and at least one component selected from TiO ₂ , Nb ₂ O ₅ and Ta ₂ O _{5 in} an amount of 2% by weight or less (including 0%). And a balance of at least one metal selected from Mo, W and Re. 2. A multilayer alumina-based wiring board comprising a capacitor portion having a high dielectric layer sandwiched between a pair of electrode layers provided on an insulating layer mainly composed of Al ₂ O ₃ , wherein the high dielectric layer is Is Al ₂ O ₃ containing a sintering aid 40 to 95% by weight
And at least one component selected from TiO ₂ , Nb ₂ O ₅ and Ta ₂ O _{5 in} an amount of 2% by weight or less (excluding 0)
And a balance of at least one metal selected from Mo, W and Re. 3. A semiconductor element housing package having a semiconductor element housing section, wherein a capacitor section having a high dielectric layer sandwiched between a pair of electrode layers is provided on an insulating layer mainly composed of alumina. the high dielectric layer, and the Al ₂ O ₃ 40 to 95 wt%, including sintering aids, TiO _2, Nb ₂ O
A semiconductor element characterized in that at least one component selected from ₅ and Ta ₂ O ₅ is 2% by weight or less (not including 0) and the balance is at least one metal selected from Mo, W and Re. Package for storage.