JP3199563B2 - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JP3199563B2 JP3199563B2 JP09016894A JP9016894A JP3199563B2 JP 3199563 B2 JP3199563 B2 JP 3199563B2 JP 09016894 A JP09016894 A JP 09016894A JP 9016894 A JP9016894 A JP 9016894A JP 3199563 B2 JP3199563 B2 JP 3199563B2
- Authority
- JP
- Japan
- Prior art keywords
- film resistor
- thin film
- wiring layer
- metallized wiring
- thick
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は混成集積回路装置や半導
体素子を収容する半導体素子収納用パッケージ等に使用
される配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a hybrid integrated circuit device, a semiconductor device housing package for housing a semiconductor device, and the like.
【0002】[0002]
【従来の技術】従来、配線基板、例えば、半導体素子を
収容する半導体素子収納用パッケージに使用される配線
基板は一般に、酸化アルミニウム質焼結体等の電気絶縁
材料から成り、その上面略中央部に半導体素子を収容す
るための凹部を設けると共に該凹部周辺から外周部にか
けて複数個のメタライズ配線層(信号用メタライズ配線
層、電源用メタライズ配線層及び接地用メタライズ配線
層)を被着導出させた構造を有しており、絶縁基体の凹
部底面に半導体素子を接着剤を介して接着固定するとと
もに該半導体素子の各電極(信号電極、電源電極及び接
地電極)をボンディングワイヤを介してメタライズ配線
層に電気的に接続させ、しかる後、前記絶縁基体の上面
に蓋体をガラス、樹脂等の封止材を介して接合させ、絶
縁基体と蓋体とから成る容器内部に半導体素子を気密に
封止することによって製品としての半導体装置となる。2. Description of the Related Art Conventionally, a wiring board, for example, a wiring board used for a semiconductor element housing package for housing a semiconductor element is generally made of an electrically insulating material such as an aluminum oxide sintered body, and has a substantially upper central portion. And a plurality of metallized wiring layers (a metallized wiring layer for signal, a metallized wiring layer for power supply, and a metallized wiring layer for grounding) were attached and derived from the periphery to the outer periphery of the concave portion. The semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base via an adhesive, and each electrode (signal electrode, power supply electrode, and ground electrode) of the semiconductor element is metalized via a bonding wire. Then, a lid is bonded to the upper surface of the insulating base via a sealing material such as glass or resin, and then the insulating base and the lid are connected to each other. A semiconductor device as a product in a container inside made by sealing a semiconductor element hermetically.
【0003】尚、前記酸化アルミニウム質焼結体等から
成る絶縁基体は一般にアルミナ(Al2 O3 )、シリカ
(SiO2 )、カルシア(CaO)、マグネシア(Mg
O)等の原料粉末に適当な有機溶剤、溶媒を添加混合し
て泥漿状となすとともにこれを従来周知のドクターブレ
ード法やカレンダーロール法等を採用することによって
セラミックグリーンシート(セラミック生シート)を形
成し、しかる後、前記セラミックグリーンシートに適当
な打ち抜き加工を施すとともに複数枚積層し、高温(約
1600℃)で焼成することによって製作され、また前
記メタライズ配線層は、タングステン、モリブデン、マ
ンガン等の高融点金属粉末から成り、該高融点金属粉末
に適当な有機溶剤、溶媒を添加混合して得た金属ペース
トをスクリーン印刷法等の厚膜形成技術を採用し、絶縁
基体と成るセラミックグリーンシートに予め印刷塗布し
ておくことによって絶縁基体の凹部周辺から外周部にか
けて被着形成される。[0003] The insulating substrate made of the aluminum oxide sintered body or the like is generally made of alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), magnesia (Mg
O) or the like, an appropriate organic solvent and a solvent are added and mixed to form a slurry, and a ceramic green sheet (green ceramic sheet) is formed by employing a conventionally known doctor blade method or calender roll method. Then, the ceramic green sheet is manufactured by subjecting the ceramic green sheet to appropriate punching, laminating a plurality of sheets, and firing at a high temperature (about 1600 ° C.). The metallized wiring layer is made of tungsten, molybdenum, manganese, etc. A ceramic green sheet to be used as an insulating substrate by employing a thick film forming technique such as a screen printing method using a metal paste obtained by adding and mixing an appropriate organic solvent and a solvent to the high melting point metal powder. Is formed from the periphery of the concave portion of the insulating base to the outer peripheral portion by printing and coating in advance. .
【0004】しかしながら、この従来の半導体素子収納
用パッケージに使用される配線基板は絶縁基体に設けた
メタライズ配線層のうち、電気信号が伝播する信号用メ
タライズ配線層のインピーダンスが伝播する信号の減衰
を極小とするため一般に50〜100Ωに設定されてお
り、半導体素子の入力インピーダンス(数Ω)及び出力
インピーダンス(数MΩ)と大きく相違する。そのため
信号用メタライズ配線層を通して半導体素子に電気信号
の出し入れを行った場合、前記半導体素子の特性(入出
力)インピーダンスが半導体素子側から見た信号用メタ
ライズ配線層のインピーダンスと不整合であるため信号
用メタライズ配線層を伝わる電気信号に反射によるノイ
ズが発生し、該ノイズが半導体素子に入力されて半導体
素子を正常に作動させることができないという欠点を有
していた。However, the wiring board used in the conventional package for accommodating a semiconductor element is provided with a metallized wiring layer provided on an insulating base, which is used to reduce the attenuation of a signal in which the impedance of the signal metallized wiring layer in which an electric signal propagates propagates. Generally, the impedance is set to 50 to 100Ω to minimize the difference, which is largely different from the input impedance (several Ω) and the output impedance (several MΩ) of the semiconductor element. Therefore, when an electric signal is input / output to / from the semiconductor element through the signal metallization wiring layer, the characteristic (input / output) impedance of the semiconductor element is mismatched with the impedance of the signal metallization wiring layer viewed from the semiconductor element side. However, there is a drawback that noise due to reflection is generated in an electric signal transmitted through the metallized wiring layer for use, and the noise is input to the semiconductor element and the semiconductor element cannot be normally operated.
【0005】そこで上記欠点を解消するために半導体素
子の信号電極が接続される信号用メタライズ配線層と半
導体素子の電源電極もしくは接地電極が接続される電源
用メタライズ配線層もしくは接地用メタライズ配線層と
の間に薄膜抵抗体から成る終端抵抗を被着接続し、半導
体素子の特性インピーダンスと信号用メタライズ配線層
のインピーダンスを整合させ、信号用メタライズ配線層
を伝播する電気信号に反射によるノイズが発生するのを
防止したり、各信号用メタライズ配線層に隙間を設ける
とともに該隙間に薄膜抵抗体から成るダンピング抵抗を
直列に被着接続させ、信号用メタライズ配線層のインピ
ーダンスと半導体素子の特性インピーダンスの相違に起
因して発生するノイズをダンピング抵抗で減衰させ、該
ノイズが信号用メタライズ配線層を伝播して半導体素子
に入り込むのを防止するようにしている。In order to solve the above drawbacks, a signal metallized wiring layer to which a signal electrode of a semiconductor element is connected and a power metallized wiring layer or a ground metallized wiring layer to which a power supply electrode or a ground electrode of a semiconductor element is connected. A terminating resistor composed of a thin film resistor is attached and connected between them, and the characteristic impedance of the semiconductor element and the impedance of the signal metallization wiring layer are matched, and noise due to reflection is generated in the electric signal propagating through the signal metallization wiring layer. And a gap is formed in each signal metallization wiring layer, and a damping resistor made of a thin film resistor is connected in series to the gap, and the difference between the impedance of the signal metallization wiring layer and the characteristic impedance of the semiconductor element. The noise generated due to the noise is attenuated by the damping resistor, and the noise is So as to prevent from entering the semiconductor element propagates through the rise wiring layer.
【0006】尚、前記終端抵抗やダンピング抵抗として
の薄膜抵抗体は、一般に窒化タンタルやニッケル−クロ
ム等、電気抵抗率が100乃至150μΩcmの材料か
ら成り、スパッタリング法やイオンプレーティング法及
びフォトリソグラフィ技術等の薄膜形成技術を採用する
ことによって、絶縁基体の表面で信号用メタライズ配線
層と電源用メタライズ配線層もしくは接地用メタライズ
配線層との間、或いは各信号用メタライズ配線層に設け
た隙間に被着される。The thin-film resistor as the terminating resistor or the damping resistor is generally made of a material having an electrical resistivity of 100 to 150 μΩcm, such as tantalum nitride or nickel-chromium, and is formed by a sputtering method, an ion plating method, and a photolithography technique. By adopting a thin film forming technique such as that described above, it is possible to cover the gap between the metallized wiring layer for signal and the metallized wiring layer for power supply or the grounded metallized wiring layer on the surface of the insulating substrate, or the gap provided in each metallized wiring layer for signal. Be worn.
【0007】また前記絶縁基体表面に被着される薄膜抵
抗体は信号用、電源用及び接地用の各メタライズ配線層
に確実、強固に電気的接続させるため一部を各メタライ
ズ配線層の側面から上面にかけて延出させ、各メタライ
ズ配線層との接合面積が広いものとなっている。The thin film resistor applied to the surface of the insulating base is partially connected to the metallized wiring layers for signal, power supply and ground for reliable and strong electrical connection. It extends toward the upper surface and has a large bonding area with each metallized wiring layer.
【0008】[0008]
【発明が解決しようとする課題】しかしながら、この薄
膜抵抗体から成る終端抵抗やダンピング抵抗を被着させ
た配線基板は信号用、電源用及び接地用の各メタライズ
配線層がスクリーン印刷等の厚膜形成技術で形成されて
いるのに対し、薄膜抵抗体はスパッタリング、蒸着等の
薄膜形成技術で形成されていることから下記の欠点を有
したものとなる。However, the wiring board on which the terminating resistor and the damping resistor made of the thin film resistor are applied has a metallized wiring layer for signal, power and ground, which is a thick film such as screen printed. While the thin-film resistor is formed by a thin-film forming technique such as sputtering or vapor deposition, it has the following disadvantages, whereas the thin-film resistor is formed by a forming technique.
【0009】即ち、薄膜抵抗体から成る終端抵抗を被着
させた配線基板を例に説明すれば、 (1)隣接する信号用メタライズ配線層と電源用メタラ
イズ配線層もしくは接地用メタライズ配線層間の絶縁基
体上に薄膜抵抗体を、一部が両メタライズ配線層の側面
から上面にかけて延出接合するようにして薄膜形成技術
により被着させる際、両メタライズ配線層は厚膜形成技
術により形成され、厚みが10乃至20μmと厚いこと
から両メタライズ配線層の側面下方と絶縁基体上面との
交差部に薄膜抵抗体となる抵抗材料の入り込みが悪くな
り、その結果、絶縁基体上面に被着する薄膜抵抗体の厚
みは0.1乃至0.5μmと厚いものの両メタライズ配
線層の側面と絶縁基体上面との交差部に被着する薄膜抵
抗体の厚みは0.01μmと1/10以下の極めて薄い
ものとなってしまう。そのためこの配線基板に半導体素
子が作動時に発生する熱等が印加されると絶縁基体、メ
タライズ配線層及び薄膜抵抗体間に各々の熱膨張係数の
相違に起因する応力が発生し、これがメタライズ配線層
の側面下方と絶縁基体上面とが交差する位置で薄膜抵抗
体の厚みが薄い領域に集中して薄膜抵抗体にクラックに
よる電気的断線を発生させ、終端抵抗としての機能が喪
失してしまう。In other words, a wiring substrate having a terminating resistor formed of a thin film resistor attached thereto will be described as an example. (1) Insulation between an adjacent signal metallization wiring layer and a power metallization wiring layer or a ground metallization wiring layer When a thin film resistor is applied on a substrate by a thin film forming technique such that a part of the thin film resistor extends and joins from the side surface to the upper surface of the metallized wiring layers, the metallized wiring layers are formed by a thick film forming technique, Is 10 to 20 μm, the resistance material to be a thin film resistor is hardly penetrated into the intersection between the lower side surface of both metallized wiring layers and the upper surface of the insulating substrate, and as a result, the thin film resistor Although the thickness of the thin film resistor is 0.1 μm to 0.5 μm, the thickness of the thin film resistor attached to the intersection of the side surface of both metallized wiring layers and the upper surface of the insulating substrate is 0.01 μm and 1/10 or less. It will be extremely thin below. Therefore, when heat or the like generated when the semiconductor element is operated is applied to the wiring board, a stress is generated between the insulating base, the metallized wiring layer and the thin-film resistor due to a difference in their respective thermal expansion coefficients. At the position where the lower side surface of the thin film resistor and the upper surface of the insulating substrate intersect, the thin film resistor is concentrated in a thin region, and the thin film resistor is electrically disconnected due to cracks, and the function as a terminating resistor is lost.
【0010】(2)また絶縁基体上に被着された信号
用、電源用、接地用の各メタライズ配線層は、スクリー
ン印刷法等の厚膜形成技術により形成されていることか
ら、その線幅及び線長に10μm程度のばらつきを有
し、信号用メタライズ配線層と電源用もしくは接地用メ
タライズ配線層間の間隔も大きなばらつきを有したもの
となっている。そのため、例えば信号用メタライズ配線
層と電源用メタライズ配線層間に終端抵抗としての薄膜
抵抗体を被着形成しても、薄膜抵抗体の長さが一定とな
らず、抵抗値にばらつきを有して信号用メタライズ配線
層のインピーダンスを半導体素子の特性インピーダンス
に正確に整合させることができず、依然として信号用メ
タライズ配線層に電気信号を伝播させればインピーダン
スの不整合に起因するノイズが発生してしまう。(2) Since the metallized wiring layers for signal, power, and ground applied on the insulating base are formed by a thick film forming technique such as a screen printing method, their line widths are increased. In addition, the line length has a variation of about 10 μm, and the distance between the signal metallization wiring layer and the power supply or ground metallization wiring layer also has a large variation. Therefore, for example, even when a thin-film resistor as a terminating resistor is formed between the signal metallization wiring layer and the power-supply metallization wiring layer, the length of the thin-film resistor is not constant, and the resistance value varies. The impedance of the signal metallization wiring layer cannot be accurately matched to the characteristic impedance of the semiconductor element. If an electric signal is still propagated to the signal metallization wiring layer, noise due to the impedance mismatch occurs. .
【0011】尚、上記欠点は薄膜抵抗体を終端抵抗とし
て使用する場合を例に挙げて説明したがダンピング抵抗
として使用する場合も同様の欠点を招来する。The above-mentioned disadvantage has been described by taking the case where a thin-film resistor is used as a terminating resistor as an example. However, the same disadvantage occurs when the thin-film resistor is used as a damping resistor.
【0012】[0012]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は、絶縁基体に被着させた厚膜メタライズ
配線層間に所定電気抵抗値の薄膜抵抗体を、断線を発生
することなく強固に被着接続させることができる配線基
板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a method of disconnecting a thin-film resistor having a predetermined electric resistance between thick-film metallized wiring layers attached to an insulating substrate. It is an object of the present invention to provide a wiring board which can be firmly connected without being attached.
【0013】[0013]
【課題を解決するための手段】本発明の配線基板は、絶
縁基体の上面に複数の厚膜メタライズ配線層を被着さ
せ、且つ隣接する厚さが10〜20μmの厚膜メタライ
ズ配線層間の絶縁基体上面に薄膜形成技術によって厚さ
が0.1〜0.5μmの薄膜抵抗体を、一部が各厚膜メ
タライズ配線層の側面から上面にかけて延出接合するよ
う被着させた配線基板であって、前記薄膜抵抗体はその
表面で、前記少なくとも隣接する厚膜メタライズ配線層
の各々の側面と絶縁基体上面との交差部に対向する前記
薄膜抵抗体の厚みが薄くなっている2つの領域に、前記
薄膜抵抗体を前記隣接する厚膜メタライズ配線層の各々
に電気的接続させるための導電材料から成り、厚さが
0.5μm以上の2つのカバー電極が間に間隔をあけて
被着されていることを特徴とするものである。According to the present invention, there is provided a wiring board having a plurality of thick metallized wiring layers deposited on an upper surface of an insulating base, and an insulating layer between adjacent thick metallized wiring layers having a thickness of 10 to 20 μm. A wiring substrate in which a thin film resistor having a thickness of 0.1 to 0.5 μm is adhered to the upper surface of the base by a thin film forming technique so that a part thereof extends and joins from the side surface to the upper surface of each thick film metallized wiring layer. The thin film resistor has, on its surface, two regions in which the thickness of the thin film resistor facing the intersection of at least each side surface of the adjacent thick film metallized wiring layer and the upper surface of the insulating base is thin. And said
Each of the adjacent thick metallized wiring layers is connected to a thin film resistor.
, And two cover electrodes each having a thickness of 0.5 μm or more are attached with an interval between them.
【0014】[0014]
【作用】本発明の配線基板によれば、薄膜抵抗体の表面
で、少なくとも隣接する厚さが10〜20μmの厚膜メ
タライズ配線層の各々の側面と絶縁基体上面との交差部
に対向する薄膜抵抗体の厚みが薄くなっている2つの領
域に、薄膜抵抗体を隣接する厚膜メタライズ配線層の各
々に電気的接続させるための導電材料から成り、厚さが
0.5μm以上の2つのカバー電極を、間に間隔をあけ
て被着させたことから、厚膜メタライズ配線層の側面と
絶縁基体の上面とが交差する位置で、薄膜抵抗体の厚み
が薄い領域に薄膜抵抗体と厚膜メタライズ配線層と絶縁
基体の熱膨張係数の相違に起因する応力が印加されクラ
ックが発生したとしても、薄膜抵抗体は導電材料から成
るカバー電極によって厚膜メタライズ配線層の各々に確
実に電気的接続されるので電気的断線を生じることはな
く、また厚膜メタライズ配線層間の間隔にばらつきが発
生したとしても2つのカバー電極の間隔を所定間隔とす
ることによって、薄膜抵抗体の抵抗値を所定値となすこ
とができる。According to the wiring board of the present invention, on the surface of the thin film resistor, at least the thin film opposing the intersection of each side surface of the thick metallized wiring layer having a thickness of 10 to 20 μm and the upper surface of the insulating substrate. In the two regions where the thickness of the resistor is thin, a thin film resistor is placed on each of the adjacent thick metallized wiring layers.
Since two cover electrodes each made of a conductive material for electrical connection and having a thickness of 0.5 μm or more are applied with a space between them, the side surface of the thick metallized wiring layer and the insulating substrate Even at the position where the upper surface intersects, even if a stress is applied to a region where the thickness of the thin-film resistor is thin, a stress caused by a difference in thermal expansion coefficient between the thin-film resistor, the thick metallized wiring layer and the insulating base is applied, and a crack occurs, The thin-film resistor is secured to each of the thick metallized wiring layers by a cover electrode made of conductive material.
Since the electrical connection is actually made, there is no electrical disconnection. Even if the interval between the thick metallized wiring layers varies, by setting the interval between the two cover electrodes to a predetermined interval, the resistance of the thin film resistor can be reduced. The value can be a predetermined value.
【0015】従って、この配線基板を半導体素子収納用
パッケージに使用し、薄膜抵抗体を終端抵抗として用い
た場合、信号用の厚膜メタライズ配線層のインピーダン
スは半導体素子の特性インピーダンスに正確に整合し、
信号用の厚膜メタライズ配線層を伝わる電気信号に反射
によるノイズが発生することはほとんどなく、またダン
ピング抵抗として用いた場合、厚膜メタライズ配線層を
伝播するノイズがダンピング抵抗によって有効に減衰さ
れ、その結果、半導体素子に不要なノイズが入り込むこ
とはなく、半導体素子を常に正常に作動させることが可
能となる。Therefore, when this wiring board is used for a package for housing a semiconductor element and a thin film resistor is used as a terminating resistor, the impedance of the thick metallized wiring layer for signals accurately matches the characteristic impedance of the semiconductor element. ,
There is almost no noise due to reflection in the electric signal transmitted through the thick metallized wiring layer for signals, and when used as a damping resistor, the noise propagating through the thick metallized wiring layer is effectively attenuated by the damping resistor. As a result, unnecessary noise does not enter the semiconductor element, and the semiconductor element can always be normally operated.
【0016】[0016]
【実施例】次に本発明の配線基板を、半導体素子を収容
する半導体素子収納用パッケージに使用した場合を例に
採って説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where the wiring board of the present invention is used for a semiconductor device housing package for housing a semiconductor device will be described as an example.
【0017】図1、図2、図3は本発明の配線基板を用
いた半導体素子収納用パッケージの一実施例を示し、1
は絶縁基体、2は蓋体である。この絶縁基体1と蓋体2
とで半導体素子を収容するための容器4が構成される。FIGS. 1, 2 and 3 show an embodiment of a package for housing a semiconductor element using a wiring board according to the present invention.
Is an insulating base, and 2 is a lid. The insulating base 1 and the lid 2
Thus, the container 4 for housing the semiconductor element is configured.
【0018】前記絶縁基体1はその上面略中央部に半導
体素子3を収容するための凹部1aが設けてあり、該凹
部1a底面には半導体素子3が樹脂、ガラス、ロウ材等
の接着剤を介して載置固定される。The insulating substrate 1 is provided with a recess 1a for accommodating the semiconductor element 3 at a substantially central portion of the upper surface thereof, and the semiconductor element 3 is provided with an adhesive such as resin, glass, brazing material or the like on the bottom of the recess 1a. It is placed and fixed via
【0019】前記絶縁基体1は酸化アルミニウム質焼結
体、窒化アルミニウム質焼結体、ムライト質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば、酸化アルミニウム質焼結体か
ら成る場合は、アルミナ(Al2 O3 )、シリカ(Si
O2 )、カルシア(CaO)、マグネシア(MgO)等
の原料粉末に適当な有機溶剤、溶媒を添加混合して泥漿
状となすとともにこれを従来周知のドクターブレード法
やカレンダーロール法等を採用することによってセラミ
ックグリーンシート(セラミック生シート)を形成し、
しかる後、前記セラミックグリーンシートに適当な打ち
抜き加工を施すとともに複数枚積層し、高温(約160
0℃)で焼成することによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. When it is made of an aluminum oxide sintered body, alumina (Al 2 O 3 ), silica (Si
O 2), calcia (CaO), employing a magnesia (MgO) well-known doctor blade method or calendar roll method this with raw material powder in a suitable organic solvent, the solvent was admixed makes with mud漿状such like Forming a ceramic green sheet (ceramic green sheet)
Thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of the green sheets are laminated.
(0 ° C.).
【0020】また前記絶縁基体1には凹部1a周辺から
外周にかけて導出する複数のメタライズ配線層5(信号
用メタライズ配線層、電源用メタライズ配線層及び接地
用メタライズ配線層)が被着形成されており、該メタラ
イズ配線層5の凹部1a周辺部には半導体素子3の各電
極(信号電極、電源電極及び接地電極)がボンディング
ワイヤ6を介して電気的に接続され、また外周に導出さ
れた部位には外部電気回路と接続される外部リード端子
7が銀ロウ等のロウ材を介して取着される。A plurality of metallized wiring layers 5 (metallized wiring layers for signal, metallized wiring layers for power supply and metallized wiring layers for grounding) are formed on the insulating substrate 1 so as to extend from the periphery to the outer periphery of the recess 1a. Each electrode (signal electrode, power supply electrode, and ground electrode) of the semiconductor element 3 is electrically connected to the peripheral portion of the concave portion 1a of the metallized wiring layer 5 via a bonding wire 6, and at a portion led out to the outer periphery. The external lead terminal 7 connected to an external electric circuit is attached via a brazing material such as silver brazing.
【0021】前記メタライズ配線層5は半導体素子3の
各電極を外部リード端子7に電気的に接続させる作用を
為し、厚膜形成技術、即ちタングステン、モリブデン、
マンガン等の高融点金属粉末に適当な有機溶剤、溶媒を
添加混合して得た金属ペーストを絶縁基体1となるセラ
ミックグリーンシートに予めスクリーン印刷等により印
刷塗布しておくことによって絶縁基体1の凹部1a周辺
から外周にかけて被着形成される。The metallized wiring layer 5 functions to electrically connect each electrode of the semiconductor element 3 to the external lead terminal 7, and uses a thick film forming technique, that is, tungsten, molybdenum,
A concave portion of the insulating substrate 1 is obtained by previously printing and applying a metal paste obtained by adding a suitable organic solvent and a solvent to a high melting point metal powder such as manganese to a ceramic green sheet serving as the insulating substrate 1 by screen printing or the like. 1a is formed from the periphery to the outer periphery.
【0022】尚、前記メタライズ配線層5はその露出す
る表面にニッケル、金等の良導電性で、且つ耐蝕性に優
れた金属をメッキ法により1. 0乃至20. 0μmの厚
みに層着させておくとメタライズ配線層5の酸化腐食を
有効に防止することができるとともにメタライズ配線層
5とボンディングワイヤ6との接続及びメタライズ配線
層5と外部リード端子7とのロウ付けを極めて強固なも
のとなすことができる。従って、前記メタライズ配線層
5の酸化腐食を防止し、メタライズ配線層5とボンディ
ングワイヤ6との接続及びメタライズ配線層5と外部リ
ード端子7とのロウ付けを強固とするにはメタライズ配
線層5の露出する表面にニッケル、金等を1.0乃至2
0. 0μmの厚みに層着させておくことが好ましい。The metallized wiring layer 5 is formed by plating a metal having good conductivity and excellent corrosion resistance, such as nickel and gold, on the exposed surface to a thickness of 1.0 to 20.0 μm by plating. By doing so, oxidation corrosion of the metallized wiring layer 5 can be effectively prevented, and the connection between the metallized wiring layer 5 and the bonding wire 6 and the brazing between the metallized wiring layer 5 and the external lead terminals 7 are extremely strong. I can do it. Therefore, in order to prevent the metallized wiring layer 5 from being oxidized and corroded, and to firmly connect the metallized wiring layer 5 to the bonding wires 6 and braze the metallized wiring layer 5 to the external lead terminals 7, 1.0 to 2 nickel, gold, etc. on the exposed surface
It is preferable that the layer is deposited to a thickness of 0.0 μm.
【0023】また、前記複数のメタライズ配線層5が被
着形成された絶縁基体1はその上面で、且つ半導体素子
3の信号電極及び電源電極が電気的に接続される信号用
メタライズ配線層5aと電源用メタライズ配線層5bと
の間に薄膜抵抗体8が形成されており、該薄膜抵抗体8
を信号用メタライズ配線層5aと電源用メタライズ配線
層5b間に電気的に接続させることによって信号用メタ
ライズ配線層5aのインピーダンスは半導体素子3の特
性インピーダンスに整合し、これによって信号用メタラ
イズ配線層5aを伝播する電気信号に反射によるノイズ
が発生することはなくなる。The insulating substrate 1 on which the plurality of metallized wiring layers 5 are adhered is formed on the upper surface of the insulating base 1 and the signal metallized wiring layer 5a to which the signal electrode and the power supply electrode of the semiconductor element 3 are electrically connected. The thin film resistor 8 is formed between the thin film resistor 8 and the power supply metallized wiring layer 5b.
Is electrically connected between the metallization wiring layer 5a for signal and the metallization wiring layer 5b for power supply, so that the impedance of the metallization wiring layer 5a for signal matches the characteristic impedance of the semiconductor element 3, whereby the metallization wiring layer 5a for signal is used. No noise due to reflection is generated in the electric signal propagating through.
【0024】前記薄膜抵抗体8は窒化タンタル、ニッケ
ル−クロム、ニッケル−クロム−シリコン、珪酸タンタ
ル等から成り、スパッタリング法やイオンプレーティン
グ法等の薄膜形成技術によって絶縁基体1の上面で、隣
接する信号用メタライズ配線層5aと電源用メタライズ
配線層5b間に、一部が両メタライズ配線層5a、5b
の側面から上面にかけて延出接合するようにして厚さ約
0.1〜0.5μmに被着される。The thin film resistor 8 is made of tantalum nitride, nickel-chromium, nickel-chromium-silicon, tantalum silicate, or the like, and is adjacent to the upper surface of the insulating substrate 1 by a thin film forming technique such as a sputtering method or an ion plating method. Between the metallization wiring layer for signal 5a and the metallization wiring layer for power supply 5b, part of both metallization wiring layers 5a, 5b
Is attached to a thickness of about 0.1 to 0.5 μm so as to extend and join from the side surface to the upper surface.
【0025】尚、前記薄膜抵抗体8は窒化タンタルで形
成すると該窒化タンタルは絶縁基体1及び信号用及び電
源用メタライズ配線層5a、5bとの接合性が良好で、
且つ温度変化に対する電気抵抗値の変化が少ないことか
ら信号用メタライズ配線層5aと電源用メタライズ配線
層5bとの間に薄膜抵抗体8を確実、強固に接続でき、
同時に温度変化に伴う電気抵抗値のばらつきを皆無とな
すことができる。従って、前記薄膜抵抗体8は窒化タン
タルで形成することが好ましい。When the thin film resistor 8 is formed of tantalum nitride, the tantalum nitride has good bonding properties with the insulating base 1 and the metallized wiring layers 5a and 5b for signal and power supply.
In addition, since the change in the electrical resistance value with respect to the temperature change is small, the thin film resistor 8 can be securely and firmly connected between the signal metallization wiring layer 5a and the power metallization wiring layer 5b,
At the same time, there is no variation in the electric resistance value due to the temperature change. Therefore, it is preferable that the thin film resistor 8 is formed of tantalum nitride.
【0026】前記薄膜抵抗体8はまた図3に示す如くそ
の表面で、少なくとも信号用及び電源用メタライズ配線
層5a、5bの各々の側面と絶縁基体1上面との交差部
Aに対向する2つの領域に、導電材料から成り、厚さが
0.5μm以上の2つのカバー電極9、9が間に間隔を
あけて被着されている。As shown in FIG. 3, the thin film resistor 8 has two surfaces opposed to the intersection A between at least the side surfaces of the signal and power metallization wiring layers 5a and 5b and the upper surface of the insulating substrate 1 as shown in FIG. In the region, two cover electrodes 9 made of a conductive material and having a thickness of 0.5 μm or more are attached with an interval therebetween.
【0027】前記カバー電極9は、信号用及び電源用メ
タライズ配線層5a、5b間に薄膜抵抗体8を確実に電
気的接続させる作用を為し、半導体素子3を作動させた
際等に発生する熱が薄膜抵抗体8、信号用及び電源用メ
タライズ配線層5a、5b及び絶縁基体1に印加され、
各々の熱膨張係数の相違に起因する応力が信号用及び電
源用メタライズ配線層5a、5bの側面と絶縁基体1の
上面との交差する位置で薄膜抵抗体8の厚みが薄い領域
に作用し、薄膜抵抗体8にクラックによる断線を発生さ
せたとしても、その断線は薄膜抵抗体8の表面に被着さ
れている導電材料から成るカバー電極9によって再接続
されることとなり、その結果、薄膜抵抗体8は常に信号
用メタライズ配線層5aと電源用メタライズ配線層5b
間に所定の電気抵抗値で接続されることとなる。The cover electrode 9 functions to reliably connect the thin film resistor 8 between the signal and power metallization wiring layers 5a and 5b, and is generated when the semiconductor element 3 is operated. Heat is applied to the thin film resistor 8, the signal and power supply metallized wiring layers 5a and 5b, and the insulating base 1,
The stress resulting from the difference between the respective thermal expansion coefficients acts on the region where the thickness of the thin film resistor 8 is thin at the position where the side surfaces of the signal and power metallization wiring layers 5a, 5b intersect with the upper surface of the insulating base 1, Even if the thin film resistor 8 is broken by cracks, the broken wire is reconnected by the cover electrode 9 made of a conductive material adhered to the surface of the thin film resistor 8, and as a result, the thin film resistor The body 8 always includes the signal metallization wiring layer 5a and the power metallization wiring layer 5b.
A predetermined electrical resistance value is connected between them.
【0028】前記カバー電極9は例えば、ニクロム(ニ
ッケル−クロム)−金、チタン−タングステン、銅、金
等の電気抵抗率が60μΩcm以下、より好ましくは1
0μΩcm以下の導電材料によって形成され、蒸着やス
パッタリング、めっき等によって薄膜抵抗体8の表面で
少なくとも信号用及び電源用メタライズ配線層5a、5
bの各々の側面と絶縁基体1上面との交差部Aに対向す
る2つの領域に被着される。The cover electrode 9 is made of, for example, nichrome (nickel-chromium) -gold, titanium-tungsten, copper, gold or the like having an electric resistivity of 60 μΩcm or less, more preferably 1 μm or less.
It is formed of a conductive material of 0 μΩcm or less, and at least the signal and power metallization wiring layers 5 a, 5 a on the surface of the thin film resistor 8 are formed by vapor deposition, sputtering, plating or the like.
b are attached to two regions facing the intersection A between each side surface and the upper surface of the insulating base 1.
【0029】尚、前記カバー電極9はその厚みが0.5
μm未満であるとカバー電極9の機械的強度が低下し、
薄膜抵抗体8にクラックによる断線が発生する際、カバ
ー電極9にも断線が発生して信号用及び電源用メタライ
ズ配線層5a、5b間に薄膜抵抗体8を確実に電気的接
続させることができなくなる。従って、前記カバー電極
9はその厚みが0.5μm以上に特定される。The cover electrode 9 has a thickness of 0.5.
If it is less than μm, the mechanical strength of the cover electrode 9 decreases,
When a break occurs in the thin-film resistor 8 due to a crack, a break also occurs in the cover electrode 9 and the thin-film resistor 8 can be reliably electrically connected between the signal and power metallization wiring layers 5a and 5b. Disappears. Therefore, the thickness of the cover electrode 9 is specified to be 0.5 μm or more.
【0030】また前記カバー電極9はその厚みが20μ
mを越えると、カバー電極9を薄膜抵抗体8に被着させ
る際の応力によって、カバー電極9と薄膜抵抗体8との
間に剥離を発生する恐れがあるので、カバー電極9はそ
の厚みを20μm以下としておくことが好ましい。The cover electrode 9 has a thickness of 20 μm.
When the thickness exceeds m, there is a possibility that the cover electrode 9 may peel off between the cover electrode 9 and the thin film resistor 8 due to the stress at the time of applying the cover electrode 9 to the thin film resistor 8. It is preferable to set the thickness to 20 μm or less.
【0031】更に前記カバー電極9はニッケル−クロム
層と金層の2層構造となしておくと、ニッケル−クロム
層は薄膜抵抗体8を構成する窒化タンタルと電気抵抗値
が極めて小さい金の両方に接合性が良いため、電気抵抗
値が小さいカバー電極9を薄膜抵抗体8上に極めて強固
に被着させることが可能となる。従って、前記カバー電
極9はニッケル−クロム層と金層の2層構造として、窒
化タンタルから成る薄膜抵抗体8の表面に被着させるこ
とが好ましい。Further, when the cover electrode 9 has a two-layer structure of a nickel-chromium layer and a gold layer, the nickel-chromium layer is composed of both tantalum nitride constituting the thin film resistor 8 and gold having an extremely small electric resistance. Since the bonding property is good, the cover electrode 9 having a small electric resistance value can be extremely firmly adhered on the thin film resistor 8. Therefore, it is preferable that the cover electrode 9 has a two-layer structure of a nickel-chromium layer and a gold layer and is attached to the surface of the thin film resistor 8 made of tantalum nitride.
【0032】また更に前記薄膜抵抗体8の表面に被着さ
れる2つの導電材料から成るカバー電極9、9は、その
両者間の間隔を所定値となすと信号用メタライズ配線層
5aと電源用メタライズ5b間に接続される薄膜抵抗体
8の電気抵抗値を任意の所定値となすことができる。従
って、絶縁基体1上の信号用メタライズ配線層5aと電
源用メタライズ配線層5bの間隔をばらつきを考慮して
多少広くし、両メタライズ配線層5a、5b間に形成さ
れる薄膜抵抗体8もその電気抵抗値を若干高いものとし
ておくと薄膜抵抗体8はその表面に被着される2つのカ
バー電極9、9によって電気抵抗値が所定値となるよう
に調整され、その結果、信号用メタライズ配線層5aと
電源用メタライズ配線層5bとの間に所定の電気抵抗値
を有する薄膜抵抗体8を常に電気的に接続することがで
きる。Further, the cover electrodes 9, 9 made of two conductive materials and adhered to the surface of the thin film resistor 8 are provided with a signal metallized wiring layer 5a and a power supply The electric resistance value of the thin film resistor 8 connected between the metallizations 5b can be set to an arbitrary predetermined value. Accordingly, the distance between the metallized wiring layer 5a for signal and the metallized wiring layer 5b for power supply on the insulating substrate 1 is slightly widened in consideration of the variation, and the thin-film resistor 8 formed between the metallized wiring layers 5a and 5b also has When the electric resistance is set to be slightly higher, the thin film resistor 8 is adjusted so that the electric resistance becomes a predetermined value by the two cover electrodes 9 and 9 attached to the surface thereof. The thin film resistor 8 having a predetermined electric resistance value can always be electrically connected between the layer 5a and the power supply metallized wiring layer 5b.
【0033】また一方、前記絶縁基体1に被着形成した
信号用、電源用及び接地用のメタライズ配線層5の各々
にはその一端に外部リード端子7がロウ付けされてお
り、該外部リード端子7は内部に収容する半導体素子3
を外部電気回路に接続する作用を為し、外部リード端子
7を外部電気回路に接続することによって内部に収容さ
れる半導体素子3はメタライズ配線層5及び外部リード
端子7を介し外部電気回路と電気的に接続されることと
なる。On the other hand, an external lead terminal 7 is brazed to one end of each of the signal, power and ground metallized wiring layers 5 formed on the insulating base 1. 7 is a semiconductor element 3 housed inside
By connecting the external lead terminal 7 to the external electric circuit, the semiconductor element 3 housed therein is electrically connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7. Will be connected.
【0034】前記外部リード端子7はASTM F−1
5(Fe−Ni−Co合金)や42アロイ(Fe−Ni
合金)等の金属材料から成り、ASTM F−15等の
インゴット(塊)を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用することによって所定の板状
に形成される。The external lead terminal 7 is ASTM F-1
5 (Fe-Ni-Co alloy) and 42 alloy (Fe-Ni
Alloy) or the like, and is formed into a predetermined plate shape by adopting a conventionally known metal working method such as a rolling method or a punching method on an ingot (lump) such as ASTM F-15.
【0035】尚、前記外部リード端子7はその露出する
表面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡
れ性の良い金属を1.0乃至20μmの厚みに層着させ
ておくと外部リード端子7の酸化腐食を有効に防止する
ことができるとともに外部リード端子7と外部電気回路
との接続を強固となすことができる。従って、前記外部
リード端子7はその露出する表面にニッケル、金等を
1.0乃至20μmの厚みに層着させておくことが好ま
しい。The external lead terminal 7 is preferably formed by coating a metal having excellent corrosion resistance such as nickel and gold and having good wettability with a brazing material to a thickness of 1.0 to 20 μm on the exposed surface. Oxidative corrosion of the external lead terminal 7 can be effectively prevented, and the connection between the external lead terminal 7 and the external electric circuit can be made firm. Therefore, it is preferable that nickel, gold, or the like be layered on the exposed surface of the external lead terminal 7 to a thickness of 1.0 to 20 μm.
【0036】かくして本発明の配線基板を使用した半導
体素子収納用パッケージは、絶縁基体1の凹部1a底面
に半導体素子3をガラス、樹脂、ロウ材等の接着剤によ
り接着固定するとともに、半導体素子3の各電極をメタ
ライズ配線層5にボンディングワイヤ6を介して電気的
に接続し、しかる後、絶縁基体1上面に蓋体2をガラ
ス、樹脂、ロウ材等から成る封止材によって接合させ、
絶縁基体1と蓋体2とから成る容器4内部に半導体素子
3を気密に収容させることによって製品としての半導体
装置となる。Thus, in the semiconductor device housing package using the wiring board of the present invention, the semiconductor device 3 is bonded and fixed to the bottom surface of the concave portion 1a of the insulating base 1 with an adhesive such as glass, resin or brazing material. Are electrically connected to the metallized wiring layer 5 via bonding wires 6, and then the lid 2 is joined to the upper surface of the insulating base 1 with a sealing material made of glass, resin, brazing material, or the like.
A semiconductor device as a product is obtained by housing the semiconductor element 3 in an airtight manner inside a container 4 including the insulating base 1 and the lid 2.
【0037】尚、上述の実施例は薄膜抵抗体8を信号用
メタライズ配線層5aと電源用メタライズ配線層5b間
に接続させ、信号用メタライズ配線層のインピーダンス
を半導体素子の特性インピーダンスに整合させる終端抵
抗として用いる場合を例に挙げて説明したが、これを信
号用メタライズ配線層に接続させるダンピング抵抗とし
て用いる場合にも適用し得る。In the above-described embodiment, the thin-film resistor 8 is connected between the signal metallization wiring layer 5a and the power supply metallization wiring layer 5b, and the terminator for matching the impedance of the signal metallization wiring layer to the characteristic impedance of the semiconductor element. The case of using as a resistor has been described as an example, but the present invention can also be applied to a case where this is used as a damping resistor connected to a signal metallization wiring layer.
【0038】[0038]
【発明の効果】本発明の配線基板によれば、薄膜抵抗体
の表面で、少なくとも隣接する厚さが10〜20μmの
厚膜メタライズ配線層の各々の側面と絶縁基体上面との
交差部に対向する前記薄膜抵抗体の厚みが薄くなってい
る2つの領域に、薄膜抵抗体を隣接する厚膜メタライズ
配線層の各々に電気的接続させるための導電材料から成
り、厚さが0.5μm以上の2つのカバー電極を間に間
隔をあけて被着させたことから、厚膜メタライズ配線層
の側面と絶縁基体の上面とが交差する位置で、薄膜抵抗
体の厚みが薄い領域に薄膜抵抗体と厚膜メタライズ配線
層と絶縁基体の熱膨張係数の相違に起因する応力が印加
されクラックが発生したとしても、薄膜抵抗体は導電材
料から成るカバー電極によって厚膜メタライズ配線層の
各々に確実に電気的接続されるので電気的断線を生じる
ことはなく、また厚膜メタライズ配線層間の間隔にばら
つきが発生したとしても2つのカバー電極の間隔を所定
間隔とすることによって、薄膜抵抗体の抵抗値を所定値
となすことができる。According to the wiring substrate of the present invention, on the surface of the thin-film resistor, at least the adjacent side surfaces of the thick metallized wiring layer having a thickness of 10 to 20 μm and the upper surface of the insulating substrate. A thin-film resistor adjacent to a thick-film metallization in two regions where the thickness of the thin-film resistor facing the intersection is reduced.
Since two cover electrodes each made of a conductive material for electrical connection to each of the wiring layers and having a thickness of 0.5 μm or more are applied with a space between them, the side surfaces of the thick metallized wiring layers and At the position where the upper surface of the insulating substrate intersects, it is assumed that a stress is applied to a region where the thickness of the thin film resistor is thin due to a difference in thermal expansion coefficient between the thin film resistor, the thick metallized wiring layer, and the insulating substrate, and a crack is generated. Also, the thin-film resistor is made of a thick metallized wiring layer by a cover electrode made of conductive material .
Since each of the thick metallized wiring layers is electrically connected to each other, no electrical disconnection occurs, and even if the gap between the thick film metallized wiring layers varies, the gap between the two cover electrodes is set to a predetermined distance, whereby the thin film resistor is formed. The resistance value of the body can be set to a predetermined value.
【0039】従って、この配線基板を半導体素子収納用
パッケージに使用し、薄膜抵抗体を終端抵抗として用い
た場合、信号用の厚膜メタライズ配線層のインピーダン
スは半導体素子の特性インピーダンスに正確に整合し、
信号用の厚膜メタライズ配線層を伝わる電気信号に反射
によるノイズが発生することはほとんどなく、またダン
ピング抵抗として用いた場合、厚膜メタライズ配線層を
伝播するノイズがダンピング抵抗によって有効に減衰さ
れ、その結果、半導体素子に不要なノイズが入り込むこ
とはなく、半導体素子を常に正常に作動させることが可
能となる。Therefore, when this wiring board is used for a package for accommodating a semiconductor element and a thin film resistor is used as a terminating resistor, the impedance of the thick film metallized wiring layer for signals accurately matches the characteristic impedance of the semiconductor element. ,
There is almost no noise due to reflection in the electric signal transmitted through the thick metallized wiring layer for signals, and when used as a damping resistor, the noise propagating through the thick metallized wiring layer is effectively attenuated by the damping resistor. As a result, unnecessary noise does not enter the semiconductor element, and the semiconductor element can always be normally operated.
【図1】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment in which a wiring board of the present invention is applied to a package for housing a semiconductor element.
【図2】図1に示す半導体素子収納用パッケージの絶縁
基体の平面図である。FIG. 2 is a plan view of an insulating base of the package for housing a semiconductor element shown in FIG. 1;
【図3】図2の丸部拡大断面図である。FIG. 3 is an enlarged sectional view of a round part of FIG. 2;
1・・・絶縁基体 2・・・蓋体 3・・・半導体素子 4・・・容器 5・・・メタライズ配線層 8・・・薄膜抵抗体 9・・・カバー電極 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Metallized wiring layer 8 ... Thin film resistor 9 ... Cover electrode
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 1/16 H05K 3/24 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 1/16 H05K 3/24
Claims (3)
線層を被着させ、且つ隣接する厚さが10〜20μmの
厚膜メタライズ配線層間の絶縁基体上面に薄膜形成技術
によって厚さが0.1〜0.5μmの薄膜抵抗体を、一
部が各厚膜メタライズ配線層の側面から上面にかけて延
出接合するよう被着させた配線基板であって、前記薄膜
抵抗体はその表面で、前記少なくとも隣接する厚膜メタ
ライズ配線層の各々の側面と絶縁基体上面との交差部に
対向する前記薄膜抵抗体の厚みが薄くなっている2つの
領域に、前記薄膜抵抗体を前記隣接する厚膜メタライズ
配線層の各々に電気的接続させるための導電材料から成
り、厚さが0.5μm以上の2つのカバー電極が間に間
隔をあけて被着されていることを特徴とする配線基板。1. A technique for forming a plurality of thick metallized wiring layers on an upper surface of an insulating substrate and forming a thin film on an upper surface of the insulating substrate between adjacent thick metallized wiring layers having a thickness of 10 to 20 μm.
The thin film resistor of a thickness of 0.1 to 0.5 [mu] m, a wiring substrate having deposited so that a part is extended junction toward the upper surface from the side of the thick-film metallized wiring layer by the thin-film resistor at its surface, wherein at least adjacent the thin film resistor opposite to the intersection of the respective side surface and the insulating substrate upper surface of the thick film metallized wiring layer thickness becomes in two has a thin region, the thin film resistor The adjacent thick metallization
A wiring substrate, comprising two cover electrodes each made of a conductive material for making an electrical connection to each of the wiring layers and having a thickness of 0.5 μm or more with a gap therebetween.
且つカバー電極がニッケル−クロム合金層と金層の2層
構造を有していることを特徴とする請求項1に記載の配
線基板。2. A thin film resistor comprising tantalum nitride,
The wiring board according to claim 1, wherein the cover electrode has a two-layer structure of a nickel-chromium alloy layer and a gold layer.
抗率が60μΩcm以下であることを特徴とする請求項
1に記載の配線基板。3. The wiring substrate according to claim 1, wherein the cover electrode made of the conductive material has an electric resistivity of 60 μΩcm or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09016894A JP3199563B2 (en) | 1994-04-27 | 1994-04-27 | Wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09016894A JP3199563B2 (en) | 1994-04-27 | 1994-04-27 | Wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07297515A JPH07297515A (en) | 1995-11-10 |
JP3199563B2 true JP3199563B2 (en) | 2001-08-20 |
Family
ID=13990962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP09016894A Expired - Fee Related JP3199563B2 (en) | 1994-04-27 | 1994-04-27 | Wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3199563B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4741624B2 (en) * | 2008-03-21 | 2011-08-03 | 京セラ株式会社 | Wiring board |
JP5391981B2 (en) * | 2009-02-02 | 2014-01-15 | 富士通株式会社 | Circuit board, manufacturing method thereof, and resistance element |
-
1994
- 1994-04-27 JP JP09016894A patent/JP3199563B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH07297515A (en) | 1995-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3199563B2 (en) | Wiring board | |
JP2005243970A (en) | Complex circuit board | |
JP2851732B2 (en) | Electronic component storage package | |
JP3566508B2 (en) | Package for storing high-frequency elements | |
JP2738622B2 (en) | Package for storing semiconductor elements | |
JP2735708B2 (en) | Ceramic wiring board | |
JP2000340716A (en) | Wiring substrate | |
JP2735759B2 (en) | Package for storing semiconductor elements | |
JP3631588B2 (en) | Wiring board | |
JP2713841B2 (en) | Package for storing semiconductor elements | |
JP2823720B2 (en) | Ceramic wiring board | |
JPH0888449A (en) | Ceramic interconnection board | |
JPH1117344A (en) | Multilayer wiring board | |
JP2710893B2 (en) | Electronic components with leads | |
JP2000208885A (en) | Wiring board | |
JP3411204B2 (en) | Package for storing semiconductor elements | |
JPH11204691A (en) | High frequency i/o terminal and package for high frequency semiconductor device | |
JP5171751B2 (en) | WIRING BOARD, ACTIVE ELEMENT STORAGE PACKAGE USING THE SAME, AND ACTIVE ELEMENT DEVICE | |
JP2813074B2 (en) | Package for storing semiconductor elements | |
JPH05160537A (en) | Ceramic wiring board | |
JPH06275737A (en) | Package for housing semiconductor element | |
JPH066000A (en) | Ceramic wiring board | |
JP2000188454A (en) | Wiring substrate | |
JPH0521495A (en) | Semiconductor device | |
JP2001044328A (en) | High-frequency semiconductor element mounting wiring board and high-frequency semiconductor device using the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090615 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090615 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100615 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110615 Year of fee payment: 10 |
|
LAPS | Cancellation because of no payment of annual fees |