JP3198001B2 - Digital temperature compensated crystal oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital temperature compensated crystal oscillator (DTCXO) capable of fine frequency adjustment.

[0002]

2. Description of the Related Art In recent years, mobile communication devices (cellular phones, cordless phones, etc.) have been reduced in size and cost with the advancement of IC technology, whereby the number of subscribers has been accelerated, and Therefore, the carrier frequency interval (for example, 12.5 KHz) and the modulation bandwidth (for example, 5 KHz) are becoming narrower, and the accuracy requirements for the frequency source are becoming increasingly strict as shown in the following equation.

| △ f / f | ≦ 2 ppm For example, a device that satisfies the above requirements in a wide temperature range such as -40 ° C. to 85 ° C. is DTCXO.

FIG. 13 is a block diagram showing the basic structure of the DTCXO. In FIG. 13, reference numeral 1 denotes a digital temperature compensation data generator, and this data generator 1 is a crystal oscillator included in a crystal oscillator 4 described later. And outputs an analog voltage Vt corresponding to the temperature, and converts the voltage Vt into a digital value T. Further, data to be compensated at each temperature is stored in a memory (for example, ROM) in advance, and the compensation data V (for example, 10 bits) is set in a register by the address data of T, and a signal 10 is output. It is supplied to the D / A converter 2.

The D / A converter 2 converts the input V signal 10 into an analog voltage Vcw, and then smoothes the Vcw that changes with an LPF (low-pass filter) having an appropriate time constant (for example, 5 ms). , And outputs the voltage Vc11. The voltage Vc11 is input to the voltage-to-capacity converter 3. The voltage-to-capacity converter 3 is a variable capacitor (varactor diode).
And the like, hereinafter referred to as a varicap), a resistor, a semiconductor switch, etc., and the equivalent capacitance Cc between the reference numerals 12a and 12b linearly corresponds to the input voltage Vc.

Reference numeral 4 denotes a crystal oscillator. The crystal oscillator 4 is composed of a crystal oscillator (Xtal) and an inverting amplifier. The equivalent capacitance Cc between reference numerals 12a and 12b is connected in series or parallel to the crystal oscillator. Temperature compensation becomes possible, and a constant frequency signal voltage 13 independent of the ambient temperature is output. In this way, a DTCXO of ± 1 ppm can be realized even with a quartz oscillator that changes by, for example, 15 ppm in a wide range.
However, at a standard temperature (for example, 20 ° C.), when the equivalent capacitance Cc has a value Cc ₀ substantially at the center between the maximum value and the minimum value, the deviation of the constant frequency signal voltage 13 from the expected value is 0. If this is the case, there is no problem, but in practice, the deviation is about ± 16 ppm when estimated by adding the adjustment deviation of Xtal itself and the variation of the constant of the oscillation circuit. As a countermeasure, if the offset method is adopted, the digital temperature compensation data generator 1 can be used.
The bit length for storing the compensation data V in the ROM must be increased from 12 bits to 12 bits, and the storage capacity of the ROM is increased and the bit length of the D / A converter 2 is increased accordingly (2 bits). , And the voltage V in the D / A converter 2
Approximately twice as large as c is required, resulting in a large and expensive device. In particular, the digital temperature compensation data generator 1, the D / A converter 2 and the voltage-to-capacity converter 3 are implemented by an LSI.
The difference becomes remarkable when it is changed.

As a current technique for avoiding this, there is a method of providing a frequency fine adjustment command function unit 5 at a standard temperature. In response to this, there is a means for adding circuits indicated by reference numerals A and B in the specific circuit diagram of the voltage-to-capacity converter 3 shown in FIG. Here, the circuit A is a varicap VC
21 to VC2N and the semiconductor switches S21 to 2N are connected in series to form a varicap VC.
20 and connected in parallel. An example of the capacity distribution is as follows.

[0008]

(Equation 1)

This is because it is appropriate that the gate group 14 of the semiconductor switches S21 to S2N is turned on so as to satisfy the equation (1) at the standard temperature. C _{VC2, m} for capacity allocation, the number of branches N is dependent on the design, for example, to ^{2 L PF, L = 3,2,1,0,} -1, etc. -2 chosen.

The circuit B has an analog control voltage V in series with Vc.
It comprises a terminal 15 for applying k and a protection diode D2. R0, R1, R2 and D1 are protection resistors and diodes for Vc, respectively, and the circuits A and B described above.
Existed before adding.

Next, the frequency fine adjustment command function unit 5 will be described. The frequency fine adjustment command function unit 5 is composed of two independent circuits, one of which is composed of a ROM, a register and N two-state drivers of 0 and Vcc (drive voltage of the whole circuit), and the other is composed of an internal resistor. Code 1 with small analog voltage source Vk
5 is output. The frequency fine adjustment command function unit 5 shown in FIG. 13 can control the circuits A and B provided in the voltage-to-capacity changing unit 3 so that the above-mentioned deviation at the standard temperature ± 16 ppm is set to ± 1 ppm, for example. The control is performed as follows.
The ON data of the capacity C _VC1 , _m to be offset is written in the ROM, and the corresponding semiconductor switch S2m is turned on by the register and the driver based on the information, and the C _VC2 , _m is put into the operating state. The frequency can be adjusted at the standard temperature by applying the analog voltage Vk. Normally, there are many instructions 14 and an auxiliary instruction 15 is used.

[0012]

As described above, the DTCXO having the frequency fine adjustment command function unit 5 falls within a desired frequency deviation as a single unit. However, as described above, DT
The CXO functions in a communication device. Incorporation of the latest SMT in response to the demand for miniaturization of communication equipment
(Surface Mount Technology) is used, and DTCXO is also of SMD (Surface Mount Device) type. SMT uses reflow soldering, while SMD type DTCXO uses reflow soldering.
Dive down the furnace. Due to this temperature shock, the frequency of the DTCXO slightly changes. The amount of the change mainly depends on the temperature shock resistance of Xtal built-in DTCXO. X withstand
Even if tal is used, it is always ± 0.3 ppm, for example.
It would be expensive to do the following.

After the operation of the communication device, that is, Xta
The frequency aging occurs due to the driving of 1. This is also expensive if demands are strict. Further, recently, a phase lock function for adjusting the frequency of the mobile station to the frequency of the base station has been required.

The above is summarized as follows.

A. Frequency shift due to reflow temperature shock (± 0.3 ppm) b. Frequency shift due to aging (± 0.
3 ppm) c. Adjustment function to adjust the frequency to the base station (± 2.
DTCXO corrects or adjusts the above with the built-in communication equipment (the required specification is 0.1 ppm)
(The range of ± 3.0 ppm or more with the following fineness) is required, and this cannot be dealt with by the conventional method of FIG. The reasons are listed below.

(1) A method in which the ROM included in the frequency modulation command function unit 5 is replaced with an EEPROM (actually, this form is often used) to rewrite data, and the capacity C _VC2 , _m of the varicap VC _2m controlled by this method is effective. Since the minimum value is limited by the relationship between the lead capacitance and the floating distribution capacitance, and the ON resistance value of the semiconductor switch is limited (the smaller the ON resistance, the larger the size and the higher the price), the control of fineness of 0.1 ppm is required. Can not.

(2) Digital temperature compensation data generator 1
Is replaced with an EEPROM (actually, this is often the case) and the compensation data is replaced. It is not easy to re-create data, write data, and confirm temperature compensation, and it is not realistic.

(3) The method using Vk of the command 15 and the method using this Vk are based on the DT after being incorporated in the communication equipment.
It is often used for frequency adjustment of CXO. In this case, the signal terminal of the command 15 is disconnected from the internal connection to the frequency tuning command function unit 5 and becomes independent. It is sufficient to apply an appropriate Vk voltage to the external terminal of the newly created command 15, but 0.1
In order to control with a fineness of ppm, Vk needs to have an accuracy of, for example, about 3 mV. Therefore, it is not practical to mount a Vk generation circuit including a D / A converter or the like on a communication device.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital temperature-compensated crystal oscillator capable of fine frequency adjustment without impairing miniaturization and cost reduction of DTCXO.

[0020]

According to the present invention, in order to achieve the above object, a first invention senses an ambient temperature of a crystal oscillator, obtains an analog voltage corresponding to the temperature, and converts this voltage into a digital signal. A digital temperature compensation data generating unit for setting this as an address value and setting temperature compensation data stored in advance in a register, and a D / A conversion unit for converting the output of this register into an analog voltage And this D /
An analog voltage of the A conversion unit is supplied, a voltage-to-capacity conversion unit that converts the voltage into a capacitance, a frequency fine adjustment command function unit that is provided to the voltage-to-capacity conversion unit and performs fine adjustment of a frequency at a standard temperature ; A digital temperature-compensated crystal oscillator comprising: a crystal oscillator that applies a change in capacitance of the voltage-to-capacity converter to a crystal oscillator and outputs a constant frequency signal voltage independent of an ambient temperature. Previous
A signal sending section for controlling the data set of the serial register, before
An adder data from serial register is supplied, is supplied to the adder, an up / down counter for sending data to be added to the data provided, the signal on the signal transmitting section and the up / down counter Rutotomoni provided external frequency control means for sending an external frequency control means signal transmission
Enable signal to the section and up / down counter
It consists of an up signal and a down signal
Control up and down signals with
And up / down the LSB of the register.
The LSB of the counter to 2 ^M (M = 1, 2, 3, ...) times
It is characterized by having been set .

[0021]

[0022]

[0023]

[0024] The second invention senses the ambient temperature of the crystal oscillator to obtain an analog voltage corresponding to the temperature, the voltage and digital conversion to the address value Re lever, the temperature compensation data stored in advance V register , A D / A converter for converting the output of the V register into an analog voltage, and a voltage for supplying the analog voltage of the D / A converter and converting this voltage into a capacitance. and to volume conversion unit, provided to the voltage-to-capacitance converter unit exerts a frequency fine adjustment command function unit for performing fine adjustment of the frequency at the standard temperature, the capacitance variation of the voltage versus capacity conversion unit in the crystal oscillator, the ambient temperature A digital temperature-compensated crystal oscillator including a crystal oscillation unit that outputs a constant-frequency signal voltage independent of an integrator, a sample-and-hold circuit, and an external circuit in a D / A conversion unit. Number Control (AFC) grant signal generation and control unit and the input clock signal during AFC enable signal
And count with frequency adjustment count up / down signal
The provided F register is up / down, performs control to set the temperature compensation data into the V register of digital temperature compensation data generating unit from the AFC permission signal generation and control unit, F register is the count up / down
Control of the star , integrator, and sample-and-hold circuit,
F register and AFC to be counted up / down
The permission signal generation and control unit is controlled by a signal from an external frequency control unit.

According to a third aspect of the present invention , the L of the F register of the D / A converter is
The SB is set to 2 ^M (M = 1, 2, 3,...) Times the LSB of the V register of the digital temperature compensation data generator.

The fourth invention is characterized in that the interruption of the AFC enable signal is monitored at regular intervals with respect to the data set repetition cycle of the V register of the digital temperature compensation data generator.

According to a fifth aspect of the present invention, the integrator of the D / A converter is provided with an additional voltage function in addition to a voltage reduction function by a counter, and both functions are controlled by a signal from an external frequency control means by a semiconductor switch. It is characterized by having done.

[0028]

According to the first aspect of the present invention, A is supplied from the external frequency control means.
The FC enable signal is supplied to the signal transmission unit, and the up pulse signal and the down pulse signal are supplied to the up / down counter, respectively, to operate them. In this operation, it is added to the temperature compensation data and offset, the total compensation data is generated in the digital domain, passed to the D / A converter, and the equivalent voltage of the varicap is controlled by the analog voltage, and the frequency of the crystal oscillation circuit is adjusted. It does not depend on temperature. A desired constant value can be obtained even in an operation state after being incorporated in a communication device. When an up / down pulse is input simultaneously, the counter is reset, and the up / down counter is reset.
If LSB is set to 2 ^M times the temperature compensation data, high-speed adjustment becomes possible.

In the second to fourth inventions , the integrator of the D / A converter, the sample-and-hold circuit, the AFC permission signal generation / conversion controller, and the F register are provided.
When the C enable signal is interrupted, it is determined whether a DAC (digital-to-analog conversion) is being performed.
If the AC is completed, immediately issue an AFC permission if not completed. The DAC does not end at the V-counter counter 0 cross, but ends when the value of the DAC is equal to that of the F register. Updating of the data in the V register is prohibited when the AFC permission signal is turned on, and updating is started when the signal is turned off, thereby starting the DAC.

According to the fifth aspect of the present invention , since an additional voltage function corresponding to the integrator count-up is provided, the AFC can immediately respond in the analog domain.

[0031]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment, and FIG.
The same parts as those shown in FIG. In FIG. 1, 3
Reference numeral 1 denotes a digital temperature compensation data generator 1 shown in FIG.
A temperature compensation data generation unit (detailed blocks will be described later) is an improvement of the above-described embodiment, and the temperature compensation data generation unit 31 includes an external frequency control unit (AFC: Auxiliary Frequency Control).
rol), the temperature compensation data generation unit 31 is controlled by the setting content data 33 supplied from this means 32 to the temperature compensation data generation unit 31. 34 is a temperature compensation data generator 3
1 is the total compensation data sent out.

Next, the temperature compensation data generator 31 will be described with reference to FIG. FIG. 2 shows a first example of a specific configuration diagram of the first embodiment. In FIG. 2, reference numeral 31a denotes a voltage output unit that senses the ambient temperature of the crystal unit and outputs a voltage Vt corresponding to the temperature. An A / D converter 31b converts an analog voltage from the voltage output unit 31a into a digital value T. A register 31c stores data to be compensated for each temperature in a memory (ROM) in advance. Compensation data is V-registered by T address data
It is set to the data.

The output of the register 31c is supplied to an adder 41. The adder 41 adds the output of the up / down counter 42 and the output of the register 31c, and gives the added value to the D / A converter 11. Reference numeral 43 denotes a signal transmission unit that transmits an output for inhibiting data setting of the register 31c when a signal is input from the external input signal terminal 44 (AFC enable signal reception terminal) of the external frequency control unit 32. When the register 31c is in the process of setting, the signal sending unit 43 waits for the completion of the setting, and sends a signal prohibiting the next setting. Reference numerals 45 and 46 of the external frequency control means 32 are external input signal terminals for supplying an up pulse signal and a down pulse signal to the up / down counter 42. The up / down counter 42 is configured to pass data to the adder 41 when a set predetermined time t ₀ pulse signal does not arrive. The total compensation data output from the adder 41 includes an N-bit (for example, N = 10) signal 47 and a guarantee signal 48 indicating that the signal 47 has been determined.
8 is supplied to the D / A converter 11.

In the above-described configuration, after inputting an AFC enable signal from the communication device equipped with DTCXO to the external input terminal 44 and inputting an up pulse signal or a down pulse signal from the external input terminals 45 and 46, a desired frequency is obtained. Fine adjustment is possible. Pause is taken after a fixed period of pulse input pause, and then fine adjustment can be performed again. When the desired frequency is reached, the AFC enable signal is turned off, and the offset value is added to return to the normal temperature compensation operation.

In the first example, the following effects can be obtained.
(1) With recent LSI semiconductor technology, it is possible to cope with a short up-down pulse signal width and a sufficiently high-speed A
FC can be realized. (2) One section of control can be performed without inputting a pulse for a certain period (t ₀ ) or more, and re-input can be performed, so that over control can be easily performed. Both up and down pulses can be received without narrowing t0.

Next, a second example of the configuration of the first embodiment will be described with reference to FIG. The second example is a reset function unit 50 of the up / down counter 42 shown in FIG. 1. The reset function unit 50 is configured to be up if the inputs of the external input signal terminals 45 and 46 are simultaneous for a certain period (one pulse or two pulses). A signal for resetting the down counter 42 is transmitted. FIG. 4 is a time chart for explaining this. In the time chart, the first half shows that the reset is performed, and the second half shows that the pre-count value is held. The effect of the second example can be reset without providing a new terminal.

[0037] The first example, in the second example, LSB of 2 ^M of the up-down counter 42 against the LSB of the V register 31c (e.g. 0.03ppm) (M = 1,2,3
……) times (8 times if M = 3) external input signal terminal 4
The frequency adjustment amount per pulse of 5, 46 is increased. M =
In the case of 3, the adder 41 shifts the data of the counter 42 to the V register 31c by 3 bits and adds it. Although not shown, selection and setting can also be performed using a memory, a switch, or the like. In this way, the adjustment sensitivity per pulse can be easily varied, and high-speed adjustment is possible.

Next, a third example of the specific configuration of the first embodiment will be described with reference to FIG. Although the external input signal terminals 44, 45, and 46 are provided in the first and second examples, the terminals 45 and 4 are provided for the purpose of downsizing the DTCXO, specifically, reducing the number of terminals.
6 is used in combination with a terminal used for another purpose, and a terminal 44 is used.
Is dedicated to the AFC enable signal terminal. FIG. 5 shows the configuration, in which a function section 70 is provided in the external frequency control means 32. When the AFC enable signal input from the terminal 44 is ON, the function unit 70 switches the signals of the terminals 45 and 46 into the temperature compensation data generation unit 31 by the command 33. In addition,
The terminal which can be used together is offline ROM data writing,
Confirmation read, test terminal, etc. With the configuration as in the third example, the number of terminals can be reduced, and the size and cost can be reduced.

Next, a second embodiment will be described. FIG. 6 is a block diagram of the second embodiment, and the same parts as those of the first embodiment are denoted by the same reference numerals. In FIG. 6, a control signal 33 of the external frequency control means 30 is input to the D / A converter 2 , and a detailed block thereof is shown in FIG. In FIG.
Signal sending section 31 provided in temperature compensation data generating section 31
d is controlled by an AFC permission signal 34B sent from an AFC permission signal generation / conversion control section 11C provided in the D / A conversion section 2 , and the V register 31
A signal for prohibiting the setting of C is transmitted. And OFF
Release the prohibition with.

Repetition period τ of V register 31C set
Indicates that the ambient temperature change of DTCXO is not large (for example, 1 ° C.
/ Min) The amount of compensation at the time of temperature change is not large (for example, 1
ppm / ° C. or less) When frequency jitter is evaluated by Allan dispersion or the like, it is 1
It is usually performed in units of seconds of 0 second or less. Here, the external frequency control means 30 will be described. In FIG.
Reference numerals 51 to 54 denote external input / output signal terminals, which are connected to the communication device on which the DTCXO is mounted. Reference numeral 51 denotes an AFC enable input signal terminal. This enable signal is sent from the signal line 33A to the AFC enable signal generation / conversion control section 11C.
It turns on when it is desired to enter the FC operation, and turns off at the end. Reference numeral 52 denotes an AFC permission signal output terminal, which is connected to the signal line 3 from the AFC permission signal generation / conversion control unit 11C.
3B. This signal is turned off in conjunction with the turning off of the AFC enable signal.
53 UP / DOWN signal terminal, 54 is a clock signal terminal, both terminals signal the signal line 33C, is supplied to the F register 13 via 33D, to specify the behavior of the count-up / down of F register 13.

Next, the D / A converter 2 will be described. Reference numeral 11 denotes a D / A converter, 12 denotes an LPF, and an LPF 12
Is a signal to which not only V data but also F data as a result of AFC is taken into account. D / in this case
The A converter 11 includes an integrator 11A and a sample hold circuit 1.
1B, an AFC permission signal generation / conversion control unit 11C.

Here, the addition of the function of the AFC permission signal generation / conversion control unit 11C will be described. One of them is signal line 3
When the AFC enable signal of 3A is received and the DAC operation is not started, the AFC enable signal is immediately transmitted.
On the other hand, if the DAC is in operation, an AFC permission signal is transmitted as soon as the operation is completed. The other is that the DAC operation is terminated when the conventional V register becomes 0, but when the same value is obtained by comparing with the F register. F
When the register is positive, it ends earlier than the conventional 0. When the F register is negative, the V register passes through 0 and counts down further, ending later when the most significant bit has the same value on the code that becomes 1. . This operation is an addition of the V register and the F register.

Next, the F register will be described. The F register is counted up / down by the clock signal input in the AFC permission signal and the count up / down signal. To increase the frequency, count down. To decrease the frequency, count up. FIG. 8 is a time chart showing the timing relationship between the enable signal and the AFC enable signal during the DAC operation and the non-operation, and the relationship between the count-up / down signal and the clock signal.

Even in the integral type, in recent LSI semiconductor technology, D
Since the speed of the AC is increased, the time during which the AFC permission signal is delayed from the enable signal does not matter because the operation is being performed in FIG. The left side of FIG. 8 is an example of 5 count-up, and the right side of FIG. 8 is an example of 4 count-down. Although the embodiment in which the adjustment speed is improved by the LSB of the F register has been described, the fineness is lost in that case. As another means for eliminating this, it can be realized by increasing the speed of the clock signal. This is also recent LS
With I-semiconductor technology, considerable speed can be achieved without increasing manufacturing costs. Here, a series of operations of the AFC will be described below.
The communication device equipped with the DTCXO includes: (1) Turn on the AFC enable signal and put it into the terminal 51; (2) confirm that the AFC enable signal from the terminal 52 is on; (3) Specify the direction by up / down. (5) AF is transmitted by the number corresponding to the frequency at which the clock pulse of an appropriate speed is to be adjusted (the number of pulses is calculated because the sensitivity ppm is known per pulse). (5) AF
The C enable signal is released. (6) Since the frequency becomes a new frequency after the adjustment, go to the above (1) if readjustment is necessary, and terminate if unnecessary.

On the other hand, the DTCXO has a flow chart shown in FIG.
Behaves like In FIG. 9, D is set in step S1.
Turn on the power of TCXO. Thereafter, initialization is performed in step S2, and data is set in the V register in step S3. Step S4 is a DAC control step, in which DAC control is performed. With this control, a new frequency output is obtained in step S5. Next, it is determined in step S6 whether or not the AFC is enabled. If the determination result is "NO", the process returns to step S3 after waiting τ seconds in step S7. If "YES" in the step S6, the process of the step S8 is performed. Step S8 is a process of setting the AFC permission signal (Ready signal) to High, and if this process is completed, the process proceeds to step S9.
Proceed to. Step S9 is a process of prohibiting the set update of the V register. After that, the F register is counted by the up / down signal and the clock signal. This processing is step S10. In step S11, it is determined in step S11 whether the count value of the F register is AFC enabled. If the result of the determination is "NO", the flow returns to step S3. If "YES", the process returns to the step S10. S12 is A
If there is an interrupt in the FC enable interrupt step, it is determined in step S13 whether the DAC is operating. If the determination is "NO", the flow proceeds to step S8. If "YES", the process of step S14 is performed. Step S14 is DAC
This is a process of setting the AFCReady signal to High after the end.

The flow chart of FIG. 10 is almost the same as FIG. 9, and a part thereof is different from the flow chart of FIG. That part is between step S5 and step S6, J = U of step S15.
Add. If "NO" in the step S6, the processing of the steps S16 to S18 is added. Step S1
6 is a process of waiting for τ / u seconds, and after this process, step S1 is executed.
7, the processing of J = J-1 is performed, and in step S18, J = 0.
Is determined. If the determination is "NO", the flow returns to step S6. If "YES", the process returns to the step S3. As described above, the DTCXO operates as shown in FIGS. 9 and 10, and the rise of the AFCReady signal is facilitated as shown in FIG. Although the above configuration has been described in terms of a hardware image, it is advantageous to mix a DSP (digital signal processor) and a F / W (firmware) as shown in FIGS. 9 and 10, and to reduce the size in an LSI.

With the configuration as in the second embodiment, the control of the communication device on which the DTCXO is mounted is logical, simple and accurate, and the entire set can be reduced in size and cost. Further, high-speed adjustment is possible by making the LSB of the F register 2 ^M (M = 1, 2, 3,...) Times that of the V register. Further, the width of the clock signal can be reduced, and high-speed adjustment can be separately performed. According to the flowchart of FIG. 10, the responsiveness adjustment without waiting for τ seconds becomes possible.

Next, a third embodiment will be described. The third embodiment is similar in block configuration to those of the second embodiment shown in FIGS. 6 and 7, but is different in the configuration of the integrator 11A and the sample hold circuit 11B shown in FIG. Due to this configuration difference,
This is to improve the responsiveness of the AFC even in the analog region in the embodiment. FIG. 11 is a specific circuit diagram of the integrator and the sample and hold circuit. The parts different from the second embodiment are semiconductor switches SW5 and SW6. In the second embodiment, SW5 is short-circuited, SW6 is open, and there is no input of VR2. In FIG.
SW6 is a semiconductor switch, OP Amp is an operational amplifier,
C1 to C3 are capacitors. Semiconductor switch SW1
ON and OFF of SW6 are as shown in the following table.

[0049]

[Table 1]

The operation of the above table except for the parts denoted by reference numerals 61 and 62 is well known.

In FIG. 11, VR1, VR2,
VR3 is a design value, for example, 2Vr, 1.6Vr,
If 1.8Vr is selected, VR2 will have the same value subtracted from VR1 at every countdown.

Here, the operation of FIG. 11 will be described with reference to the flowchart of FIG. First, in step S1, DTCXO
Is turned on, and initialization is performed in step S2. Thereafter, it is determined in step S3 whether the AFC enable is "LOW", and if "YES", data is set in the V register in step S4. After the data set, D
An AC operation is performed, and a new frequency output is obtained in step S6. After obtaining a new frequency output, the process returns to step S3 after waiting for τ seconds in step S7. D in step S5
The AC operation is the same as in the second embodiment, and ends when the count value of the V register is equal to the value obtained by comparison with the counter F register instead of the 0 cross end. Therefore, the adjustment value obtained by the AFC operation stored in the F register is used as an offset.

On the other hand, step S8 is a step for starting the AFC operation, in which the AFC enable is set to H from the outside.
igh. In this operation, whether or not the DAC is operating is determined in step S9.
If “NO”, the process proceeds to step S10.
In step S10, the AFCReady signal is set to High, and DA
This is a step of setting so as not to enter the C operation. If "YES" is determined in step S9, step S11 is performed.
Waits for the end of the DAC operation, and sets the AFReady signal to Hig.
Set to h so as not to enter the DAC operation.

S12 is a step of judging whether it is up / down. If "YES", F is executed by the processing of step S13.
Make the register a down counter (increase the frequency).
Then, the configuration of the D / A is changed in step S14, and a clock is input and the frequency is adjusted in step S15. In step S16, it is determined whether the adjustment of the frequency has been completed.
If "NO", the process returns to the step S12. If "YES", the flow proceeds to step S17 to set AFCReady to "LOW". Thereafter, in step S18, the D / A configuration is returned to the original state, and the process of step S3 is performed. If "NO" in the step S12, the F register is set to an up counter (the frequency is reduced) in a step S19. Thereafter, the configuration of the DAC is changed, and the process proceeds to step S15.

In steps S14 and S20, the states of the semiconductor switches SW3 to SW6 are designated at the time of increment or decrement of reference numeral 62 in the table.
When SW4 is ON, the sampling hold voltage is added in an analog manner according to the count of the F register. SW3 is O
The integration is executed by the FF, and the direction of the integration is designated by SW5 and SW6. A step S18 designates the states of SW1 to SW6 immediately before the DAC operation in the table.

In the third embodiment configured as described above, DT
AFC can be performed in the analog domain without increasing the size and cost of the CXO, so that a responsive characteristic is obtained. In particular, although recent LSI technology can increase the speed in the digital domain, the DTCXO can be controlled with a slow cycle of τ seconds (seconds of 10 seconds or less) as described above, and therefore the cost can be reduced. The logic aimed at is a low speed itself. There is an advantage that high-speed AFC can be realized in the analog domain without the high speed of digital logic.

[0057]

As described above, according to the present invention,
Since the AFC is provided in the digital temperature compensation data generation unit, fine frequency adjustment can be performed without compromising miniaturization and cost reduction of DTCXO, and control of communication equipment equipped with DTCXO is simple and accurate, and set As a result, the size and cost can be reduced. In addition, since the D / A converter is provided with the AFC means, fine frequency adjustment or correction can be performed in the same manner as described above, and DAC termination is performed not by counting down the V register but by comparing it with the F register by the same value. Thus, an apparent adder was made, hardware was omitted, and miniaturization and cost reduction were made possible. Further, high-speed adjustment and quick adjustment of frequency can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a first example of a specific configuration of the first embodiment.

FIG. 3 is a block diagram showing a second example of the specific configuration of the first embodiment.

FIG. 4 is a time chart of a second example.

FIG. 5 is a block diagram showing a third example of the specific configuration of the first embodiment.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a block diagram showing a specific configuration of the second embodiment.

FIG. 8 is a time chart of the second embodiment.

FIG. 9 is a flowchart.

FIG. 10 is a flowchart.

FIG. 11 is a circuit diagram showing a third embodiment of the present invention.

FIG. 12 is a flowchart.

FIG. 13 is a block diagram showing a conventional example.

FIG. 14 is a circuit diagram of a voltage-to-capacity converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Digital temperature compensation data generation part 2 ... D / A conversion part 3 ... Voltage-to-capacity conversion part 4 ... Crystal oscillation part 5 ... Frequency fine adjustment command function part 31 ... Temperature compensation data generation part 32 ... External frequency control means 41 ... Addition Unit 42 ... Up / down counter 43 ... Signal sending unit

──────────────────────────────────────────────────続 き Continued on the front page (72) Kazunari Matsumoto 2-1-1-17 Osaki, Shinagawa-ku, Tokyo Inside Meidensha Co., Ltd. (72) Inventor Takashi Matsui 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-3-226103 (JP, A) JP-A-63-108806 (JP, A) Sho-61-158723 (JP, U) Sho-sho 59-55791 (JP, U) Sho-sho 56-160041 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03B 5 / 32 H03L 1/02

Claims (5)

(57) [Claims] 1. Sensing the ambient temperature of a crystal unit,
Obtain an analog voltage corresponding to the temperature, Digitally this voltage
And Le converts, which was an address value, a digital temperature compensation data generating unit for setting the temperature compensation data stored in advance in the register, a D / A converter for converting the output of the register to an analog voltage, the An analog voltage of a D / A converter is supplied, and a voltage-to-capacity converter for converting the voltage into a capacitance, and a frequency fine-adjustment command function unit, which is provided to the voltage-to-capacity converter and fine-tunes the frequency at a standard temperature When,
A digital temperature-compensated crystal oscillator comprising: a crystal oscillator that applies a change in capacitance of the voltage-to-capacity converter to a crystal oscillator and outputs a constant frequency signal voltage independent of an ambient temperature. a signal sending section for controlling the data set of register, an adder data from the register is supplied, is supplied to the adder, provided an up / down counter for sending data to be added to the data , Rutotomo provided external frequency control means for sending a signal to the signal transmitting section and the up / down counter
In addition, the external frequency control means enables
Signal and the up signal given to the up / down counter.
And down signal.
Control up and down signals while prohibiting set
And the LSB of the register
The LSB of the up / down counter is set to 2 ^M (M = 1, 2,
3.) A digital temperature-compensated crystal oscillator characterized in that the frequency is doubled . 2. Sensing the ambient temperature of the crystal unit,
Obtain an analog voltage corresponding to the temperature, the voltage and digital conversion to the address value Re lever, a digital temperature compensation data generating unit for setting the temperature compensation data stored in advance in the V register, the output of the V register A D / A converter for converting the voltage to an analog voltage, an analog voltage of the D / A converter are supplied, and a voltage-to-capacity converter for converting the voltage to a capacitance. A frequency fine adjustment command function unit for performing fine adjustment of the frequency at the time of temperature, and a crystal oscillation unit that applies a change in capacitance of the voltage-to-capacity conversion unit to the crystal oscillator and outputs a constant frequency signal voltage independent of the ambient temperature. In a digital temperature compensated crystal oscillator, an integrator, a sample-and-hold circuit, an external frequency control (AFC) permission signal generation / control unit, and an AFC are provided in a D / A conversion unit.
The clock signal input in the enable signal and the frequency
Count up / down by count up / down signal
The F register is provided to set the temperature compensation data from the AFC permission signal generation and control unit in the V register of the digital temperature compensation data generating unit
And count up / down.
Controls the F register , integrator, and sample-and-hold circuit, and counts up / down the F register.
A digital temperature-compensated crystal oscillator characterized in that a star and an AFC permission signal generation / control unit are controlled by a signal from an external frequency control means. 3. The LSB of the F register of the D / A converter is set to 2 ^M (M = 1, 2, 3,...) Times the LSB of the V register of the digital temperature compensation data generator. A digital temperature compensated crystal oscillator according to claim 2. 4. The V level of the digital temperature compensation data generator.
4. The digital temperature-compensated crystal oscillator according to claim 2, wherein an interrupt of an AFC enable signal is monitored at regular intervals with respect to a data set repetition cycle of the register . 5. The integrator of the D / A converter has an additional voltage function in addition to a voltage reduction function by a counter, and both functions are controlled by a signal from an external frequency control means by a semiconductor switch. The digital temperature-compensated crystal oscillator according to claim 2, wherein: