JPH06152401A - Pll circuit - Google Patents

Abstract

PURPOSE:To compensate dispersion at the time of manufacture and to fix a loop band by adjusting the gain of a voltage controlled oscillator(VCO). CONSTITUTION:A V/I converter 2A converts a signal voltage from a switch 4 by using an operational amplifier 6 and outputs it through transistors(TR) 7 and 8. A gain adjuster 2C inputs the output current from the converter 2A to the gates of respective TRs 9-12 in common and according to a signal from a correction circuit 5, respective switches 13-16 are closed. Every time the number of closed switches is increased, the value of the current for flowing from the converter 2A to an ICO 2B is increased. When the number of closed switches is one, for example, the gain of the VCO 2 is minimum and every time the number of closed switches is increased, the gain of the VCO is increased. The ICO 2B is provided with two capacitors 17 and 18, the time for charging the capacitors changes corresponding to the current value from the gain adjuster 2C, and the frequency of an output signal from the VCO is changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art FIG. 7 shows the configuration of a conventional PLL circuit.
The phase comparator 101 compares the phase of the input signal with the phase of the output signal of the voltage controlled oscillator (hereinafter referred to as “VCO”) 103, and the signal corresponding to the phase difference is detected by the loop filter 10
It is input to the VCO 103 via 2 as a control signal.
Therefore, the output signal b of the VCO 103 is controlled so as to be in phase with the input signal and locked to the input signal. The VCO 103 includes a V / I converter 103A that converts a voltage value (V) of an input signal into a current value (I), and the V / I converter 103A.
Oscillates a signal with a frequency corresponding to the output of the converter 103A,
Output current controlled oscillator (hereinafter referred to as "ICO") 10
3B and 3B. A lag lead filter is often used as the loop filter 102 from the viewpoint of the stability of the PLL circuit.

[0003]

FIG. 8 shows gain and phase characteristics of a conventional PLL circuit using a lag lead filter as a loop filter. It can be seen from FIG. 8 that at a high frequency, the gain is rapidly reduced and the phase is changed due to the influence of the time delay of the circuit.

In order to obtain high stability as a PLL circuit, it is desirable that the gain be 1 with a sufficient phase margin (this condition is satisfied at the frequency a in FIG. 8).

However, such a PLL is actually used.
The gain of the VCO changes due to variations in the circuit when integrated into an IC. Therefore, the frequency at which the gain of the PLL circuit becomes 1 changes before and after a, for example, and the phase margin decreases. As a result, the phase transfer characteristic of the PLL circuit changes (peaking occurs), and in the worst case, it becomes an oscillating state and stops operating. That is, the phase transfer characteristic of the PLL circuit represents how much a certain jitter (noise) is overlapped with the input signal and appears in the output (output jitter / input jitter).
An example is shown in. In FIG. 9, the portion where the gain is 0 dB shows that the jitter appears in the output at the same level as the input, b shows the characteristic when the gain of the PLL circuit increases and the phase margin decreases, and c Shows the characteristic when the gain of the PLL circuit becomes small and the phase margin decreases, and d shows the characteristic when the phase margin is sufficient. In this way, the phase margin is reduced, and thus the peaking of the phase transfer characteristic (jitter is amplified).
Occurs, the frequency and phase accuracy of the PLL circuit deteriorates in the synchronized state.

Therefore, an object of the present invention is to provide a PLL circuit which solves the above problems.

[0007]

To achieve the above object, the present invention provides a voltage controlled oscillator, a phase comparator for comparing the phase of an input signal with the phase of an output signal of the voltage controlled oscillator, and the phase comparator. Of a loop filter for inputting the output signal of the above and outputting a control voltage to the voltage controlled oscillator, the voltage controlled oscillator is a voltage-current converter for converting the output voltage of the loop filter into a current. And a current control oscillator that gives the output signal to the phase comparator, and a gain adjuster that adjusts the current supplied from the voltage-current converter to the current control oscillator.

[0008]

According to the present invention, by adjusting the gain of the VCO, variations in manufacturing are compensated and the loop band becomes constant.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, the phase comparator 1 compares the phase of the input signal with the phase of the output signal of the VCO 2, and inputs a signal corresponding to the phase difference to the loop filter 3. Reference numeral 4 denotes a 3-input 1-output type switch, which is an output signal from the loop filter 3,
And two reference voltages (VREF with different values
1, VREF2) is input, and one of the three inputs is selected and output based on the control signal from the calibration circuit 5.

The VCO 2 includes a V / I converter 2A and an ICO.
2B and a gain adjuster 2C. V / I converter 2
A inputs the output signal from the switch 4, V / I converts it, and inputs it to the gain controller 2C. The gain adjuster 2C receives V from the signal from the calibration circuit 5 (details will be described later).
The value of the current flowing from the / I converter 2A to the ICO 2B is adjusted.

FIG. 2 shows details of the VCO2. The V / I converter 2A converts the signal voltage from the switch 4 into a voltage by the operational amplifier 6 and outputs the voltage via the transistors 7 and 8. The gain adjuster 2C includes a plurality of transistors 9 to 1
2 and switch 1 connected in series with each transistor 9-12
3 to 16 are connected in parallel, the output current from the V / I converter 2A is commonly input to the gates of the transistors 9 to 12, and the switches 13 to 13 are connected based on the signal from the calibration circuit 5.
16 is closed, and the current value flowing from the V / I converter 2A to the ICO 2B is increased each time the number of closed switches is increased.
For example, if the number of closed switches is one, the gain of VCO2 becomes the minimum, and as the number of closed switches increases, VCO2
Gain increases. The ICO 2B has two capacitors 17 and 18, the charging time of these capacitors 17 and 18 changes according to the value of the current from the gain adjuster 2C, and the frequency of the output signal changes. That is, now I
Considering the case where the output A of CO2B changes from Low to High, the output B of the flip-flop 19 is High.
From h to Low, P MOS FET 20 turns on, N MOS FET 21 turns off, both FETs
The capacitor 18 connected to the connection point (G) between the source and drain of 20 and 21 starts charging at a rate proportional to the current from the gain adjuster 2C. At this time, two FET2
The capacitor 17 connected to the connection point (F) between the source and drain 2 and 23 is discharged.

The charging voltage of the capacitor 18 is the reference potential Va.
After that, the comparator 24 becomes High, its output E is input to the clock input terminal of the flip-flop 19 via the OR gate 25 (output C), and its output A is inverted and becomes High to Low. At this time, the PMOS
The FET 20 is turned off, the NMOS FET 21 is turned on, the capacitor 18 is discharged, and the comparator 26
The capacitor 17 connected to the + input terminal of (output D) starts charging at a rate proportional to the current from the gain adjuster 2C.

As described above, the charging time of the capacitors 17 and 18 changes according to the current from the gain adjuster 2C, and the frequency of the output signal of the ICO 2B (VCO2) changes.

FIG. 3 shows details of the calibration circuit 5. 27,2
Reference numeral 8 is a J-bit / K-bit counter, 29 is an L-bit comparator (K> L), and 30 is an N-bit counter (N is the same as the number of transistors of the gain adjuster 2C). 31
Is a control circuit, and each of the counters 27, 28, 30
And L-bit comparator 29 and switch 4
Control to select one of the three inputs.

The J-bit counter 27 counts the pulse signal fa having an arbitrary frequency, and the K-bit counter 28 counts I.
The output signal of CO2B is counted, and the L-bit comparator 29
Compares the value of the lower L bits of the K-bit counter 28 with the gain setting value M (M ≦ L), and outputs the comparison result to the control circuit 31.
To enter. The N-bit counter 230 turns on the switch of the gain adjuster 2C by the number of bits set by the control circuit 31.

A calibration operation of the PLL circuit having the above configuration will be described. In addition, VREF input to the switch 4 here
1 and VREF2 are set to VREF1 = VREF2 + 1V.

First, the N-bit counter 30 is set to N = 1.
(The gain of VCO2 is the minimum).

VREF1 is input to the V / I converter 2A, and the J and K bit counters 27 and 28 are reset (set to 0).

The counting up of the J, K bit counters 27, 28 is started.

When the J-bit counter 27 is fully counted, the K-bit counter 28 stops counting.

The J-bit counter 27 is set to 0, and VR is set.
The EF2 is input to the V / I converter 2A.

The count-up of the J-bit counter 27 and the count-down of the K-bit counter 28 are started.

When the J-bit counter 27 is fully counted, the K-bit counter 28 stops counting, and the count value of the K-bit counter 28 at this time is set to Q.

In the L-bit comparator 29, Q <M
If so, the gain of VCO2 is small, so the N-bit counter 30 is incremented by 1 (gain increase of VCO2), and the operation is repeated after that. On the other hand, if Q ≧ M, the gain of VCO2 is appropriate. Therefore, the calibration is completed, and the output of the loop filter 3 is selected by the switch 4.

Since the gain of the VCO 2 can be adjusted as described above, the gain of the PLL circuit can be made constant by compensating for variations in manufacturing the PLL circuit, and a sufficient phase margin can be obtained. Furthermore, the band of the PLL loop (the frequency width at which the phase transfer characteristic becomes 0 dB) can be made constant, and if a PLL circuit is used for the FM demodulation circuit, the demodulation gain (to the VCO with respect to the frequency change of the input signal, The rate at which the control voltage changes) is constant.

FIG. 4 shows another embodiment of the present invention. 4, the same components as those in FIG. 1 are designated by the same reference numerals. As shown in FIG. 4, reference numeral 32 denotes a calibration circuit, which further has a configuration described below in addition to the configuration of the calibration circuit 5 shown in FIG. 1, and the D / A converter 34 includes a counter circuit described below. Enter the count data.

Reference numeral 33 is a VCO, which is different from the V / I converter shown in FIG. 1 in the structure of the V / I converter portion, which will be described later, and is otherwise similar to the VCO 2.

FIG. 5 shows the details of the VCO 33. 33A is a V / I converter, which is a first conversion unit 35 including an operational amplifier that converts the output signal voltage from the switch 4 into a current.
And a second converter 36 including an operational amplifier that converts the signal voltage from the D / A converter 34 into a current, and a current that is proportional to the current output by the first and second converters 35, 36. One current mirror section 37, 38 is provided, and the total output current of the two current mirror sections 37, 38 is input to the ICO 2B via the gain adjusting section 2C.

FIG. 6 shows details of the calibration circuit 32. The control circuit 39 uses the J-bit counter 27 and the K-bit counter 2
8, L bit comparator 29, N bit counter 30 are controlled, switch 4 is controlled, input selector 40 is controlled, and gain setting value M and free running frequency setting value M '(L≥M') are controlled.
Is input to the L-bit comparator 29, and P
The bit counter 41 is controlled. The D / A converter 34 is P
The analog voltage corresponding to the count value of the bit counter 41 is input to the second conversion unit 36 of the V / I converter 33A. Other operations are similar to those in FIG.

The calibration operation of the PLL circuit shown in FIG. 4 having the above configuration will be described.

(A) Input the gain setting value M to the input selector 40
And the count value of the P-bit counter 41 is set to the median value, and the operations 1 to 3 of the configuration of FIG. 3 are performed.

(B) The free-running frequency set value M'is selected by the input switch 40, and VREF1 is set to the V / I converter 33.
It is input to the first conversion unit 35 of A and the count value of the P-bit counter 41 is set to 0 (thus, the second conversion unit 36
The voltage input to is the minimum).

(C) J, K bit counters 27, 28
Set both to 0.

(D) J, K bit counters 27, 28
Start counting up.

(E) When the J-bit counter 27 has full count, the K-bit counter 28 stops counting,
The value of the K-bit counter 28 at this time is Q '.

(F) In the L-bit comparator 29,
If Q '<M', the P-bit counter 41 is incremented by 1 (which increases the output frequency of the VCO 33),
Return to (c) and repeat the subsequent operation, while Q '
If> M ', the frequency adjustment is terminated and the output of the loop filter 3 is selected by the switch 4.

As described above, since the gain of the VCO 33 can be adjusted and the free-running frequency can be adjusted, the frequency pull-in range can be narrowed and the operation of the PLL circuit can be further stabilized, in addition to the effect obtained in the above embodiment. Can be

[0039]

As described above, according to the present invention, P
Since the gain of the LL circuit can be easily adjusted,
It is possible to compensate for variations during manufacturing, and thus to keep the loop band constant and obtain a sufficient phase margin.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a voltage controlled oscillator according to the embodiment.

FIG. 3 is a block diagram of the calibration circuit.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a block diagram of a voltage controlled oscillator according to the embodiment.

FIG. 6 is a block diagram of the calibration circuit.

FIG. 7 is a block diagram of a conventional PLL circuit.

FIG. 8 is a diagram showing a gain / phase characteristic of the PLL circuit.

FIG. 9 is a diagram showing a phase transfer characteristic of a PLL circuit.

[Explanation of symbols]

 1 phase comparator 2 voltage controlled oscillator 3 loop filter 4 switch 5 calibration circuit

Claims (2)

[Claims] 1. A voltage controlled oscillator, a phase comparator for comparing a phase of an input signal with a phase of an output signal of the voltage controlled oscillator, and an output signal of the phase comparator for inputting control to the voltage controlled oscillator. In a PLL circuit including a loop filter that outputs a voltage, the voltage-controlled oscillator includes a voltage-current converter that converts an output voltage of the loop filter into a current, and a current that gives the output signal to the phase comparator. Controlled oscillator and the voltage-
And a gain adjuster for adjusting the current supplied from the current converter to the current controlled oscillator.
circuit. 2. A switch for selectively supplying two different reference voltages to the voltage-current converter, and a difference between two output frequencies of the voltage controlled oscillator based on the two voltages is set to a predetermined value. The PLL circuit according to claim 1, further comprising: a calibration circuit that controls the gain adjuster.