JP3196200B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of semiconductor devices, and more particularly to a semiconductor device intended to improve alignment accuracy such as patterning of a wiring pattern and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration and miniaturization of semiconductor integrated circuits such as LSIs, a connection opened in an interlayer insulating film for connection between a lower wiring and an upper wiring. The opening diameter of the hole has been reduced, and the aspect ratio has become 1 or more. The upper wiring is generally formed by depositing an Al (aluminum) -based material by a sputtering method. However, with a connection hole having an aspect ratio of 1 or more, it is difficult to obtain sufficient step coverage, and this is becoming a problem from the viewpoint of improving reliability.

In order to improve the insufficient step coverage, a technique of burying Al in a connection hole by a multi-step high-temperature Al sputtering method has been proposed. This method is disclosed, for example, in
No. -76736. This multi-stage high temperature A
The technique of embedding Al in the connection hole by the 1 sputtering method will be described below with reference to the drawings. In the following drawings, a circuit portion on which wiring is formed and an alignment mark portion used for alignment are shown.

As shown in FIG. 9A, after an element or the like is formed on a silicon substrate (not shown), a first interlayer insulating film 1 is formed, and a first wiring (lower wiring) 2 is formed thereon. (3 is a barrier metal). Then, a second interlayer insulating film 4 is formed so as to cover them, and a connection hole to the first wiring 2 is formed in the second interlayer insulating film 4.

Next, as shown in FIG. 9B, a Ti film 11 for improving the wettability of Al is formed on the entire surface of the wafer.

Subsequently, as shown in FIG. 9C, a first Al film 12 is formed at a low temperature and a high rate without breaking the processing system vacuum. By forming a film at a low temperature and a high rate, A
1 continuous film is formed.

Further, as shown in FIG. 10, a second Al film 8 is formed at a high temperature and a low rate without breaking the processing system vacuum. By forming the film at a high temperature and a low rate in this manner, the surface diffusion of Al occurs and the connection hole can be buried. here,
By the reaction between the Ti film 11 and the first Al film 12, T
An i-Al alloy 9 is formed.

However, when the connection holes are buried by the above-described method, outgas from the interlayer insulating film 4 serving as a base layer is released into the sputtering chamber, the atmosphere in the chamber deteriorates, and surface diffusion of Al occurs. When it becomes difficult, there is a high possibility that an embedding defect occurs and the reliability of the semiconductor device is reduced. Therefore, in order to obtain a stable embedding property, it is necessary to reduce outgas released into the sputtering chamber. Therefore, in the above method, the barrier metal film 6 (shown in FIG. 10) is formed on the interlayer insulating film. As the barrier metal film 6, a TiN film or a TiN / Ti film in which a TiN film is laminated on a Ti film is desirable.

By the way, it has been found that the surface state of an Al film formed on a barrier metal film by high-temperature Al sputtering or the like has a large degree of unevenness, large light scattering, and low surface reflectance. When patterning an Al film having such a large degree of surface irregularities to form an Al wiring pattern, it is difficult to perform wafer alignment with a stepper and to measure positional deviation after alignment. This is because the method of wafer alignment and position shift measurement is an optical method. These will be described with reference to the drawings.

FIG. 11A shows the state of the alignment mark portion formed by the method shown in FIGS. Since the high-temperature sputtered Al film 8 is formed on the barrier metal TiN film 6, the surface of the Al film 8 has severe irregularities. FIG. 11B shows a signal waveform obtained from the measurement of the alignment mark portion. Noise increases due to unevenness on the surface of the Al film, a good signal waveform cannot be obtained, and there is a high possibility of causing an alignment error in the stepper.

On the other hand, even if alignment is possible, it becomes difficult to measure the displacement. FIG. 12A shows the state of the mark portion for measuring the displacement. As shown in FIG. 12B, the signal waveforms obtained from the lower layer pattern (the concave portion formed in the interlayer insulating film 4 at the misalignment measurement mark portion) and the current pattern (photoresist pattern 10) are as shown in FIG.
The noise increases due to the influence of the irregularities on the film surface. Then, the signal waveform from the lower layer pattern is not clear, the measurement error increases, and the reproducibility of the measurement deteriorates. Therefore, productivity is significantly reduced. Another factor is that the edge portion of the Al film becomes smooth due to the flow of Al in the alignment mark portion (the same applies to the misalignment measurement mark portion). Such a problem is also disclosed in, for example, Japanese Patent Application Laid-Open No. 5-152446. To solve this problem, the method shown here is to form the Al film in the alignment mark portion as conformably as possible. The specific method will be described with reference to FIG.

After forming a connection hole with the lower wiring 2, FIG.
As shown in FIG. 3A, the Ti film 11 is conformably formed.
Is formed. Next, as shown in FIG. 13B, an Al film is formed at a high temperature and partially reacted with the Ti film 11 to form a Ti film.
-Forming an Al alloy layer 13; Reference numeral 14 denotes an unreacted Al film. As a result, in the alignment mark portion, Ti-A
The 1 alloy layer 13 is formed in a conformable manner, and is filled with the Ti—Al alloy layer 13 in the connection hole. Therefore, the smoothness of the alignment mark edge can be solved.

However, this method has the following problems. That is, even though conformability can be ensured in the Al film of the alignment mark portion formed in this way, the surface shape of the Al film is still severe when a barrier metal is used.

In view of the above-mentioned problems, the present invention provides a method of embedding a metal such as Al in a connection hole by a high-temperature Al sputtering method or the like at an alignment mark portion simultaneously with embedding a metal such as Al.
It is an object of the present invention to improve the surface condition of a metal film such as 1 when forming a metal film and to improve the alignment accuracy of patterning of a wiring pattern such as an Al wiring. It is another object of the present invention to provide a highly reliable semiconductor device that can easily improve the alignment accuracy of patterning of a wiring pattern such as an Al wiring.

[0015]

According to the present invention, an object of the present invention is to provide a circuit including a conductive pattern formed by a conductive layer formed on a base having a circuit portion and an alignment mark portion. Wiring is formed in a portion, and a barrier metal pattern of a barrier metal layer is interposed between the conductive pattern and the base on the surface of the base in a region excluding the alignment mark portion. A semiconductor device is provided.

In one embodiment of the present invention, a connection hole for wiring is formed in the circuit portion on the base, and the connection hole is filled with the conductive layer. The upper layer wiring is electrically connected to the lower layer wiring existing at the bottom of the connection hole, and the conductive pattern and the barrier metal pattern form an upper layer wiring.

In one embodiment of the present invention, the connection hole is filled with the conductive layer via a barrier metal layer formed on an inner surface thereof, and the conductive layer is formed in the connection hole via a barrier metal layer. It is connected to the lower wiring present at the bottom.

In one embodiment of the present invention, a connection hole for wiring is formed in the underlying circuit portion, and the connection hole is filled with a conductive filling member. The member is electrically connected to the lower wiring existing at the bottom of the connection hole, and is also electrically connected to the upper wiring formed by the conductive pattern and the barrier metal pattern.

In one embodiment of the present invention, the connection hole is filled with the conductive filling member via a barrier metal layer formed on the inner surface thereof, and the conductive filling member is filled with the barrier metal layer via the barrier metal layer. It is connected to the lower wiring existing at the bottom of the connection hole.

In one embodiment of the present invention, an uneven pattern forming an alignment mark is formed on the surface of the base in the alignment mark portion, and the conductive layer is formed on the uneven pattern.

According to the present invention, a conductive layer is formed on a base having a circuit portion and an alignment mark portion, and a conductive pattern is formed by the conductive layer. A method of manufacturing a semiconductor device that forms at least a part of a wiring of the circuit unit, comprising: forming a barrier metal layer on a surface of the base in the circuit unit; and forming a barrier metal layer on the barrier metal layer of the circuit unit. And a step of forming the conductive layer on the base of the alignment mark section, and a step of patterning the conductive layer and the barrier metal layer in the circuit section. , Are provided.

In one embodiment of the present invention, the step of forming the barrier metal layer in the circuit section includes patterning the barrier metal layer formed in both the circuit section and the alignment mark section to form the barrier mark layer. This is done by removing the barrier metal layer.

In one embodiment of the present invention, a connection hole between wiring layers of a circuit portion is formed in the base, and the inside of the connection hole is filled with the conductive layer to form a lower layer wiring at the bottom of the connection hole. And an upper layer wiring formed by the conductive pattern and the barrier metal pattern formed by patterning the conductive layer and the barrier metal layer.

In one embodiment of the present invention, a barrier metal layer is formed on the inner surface of the connection hole and on the surface of the lower wiring existing at the bottom of the connection hole, and the connection hole is formed through the barrier metal layer through the conductive film. The conductive layer is filled with a layer, and the conductive layer is connected to the lower wiring existing at the bottom of the connection hole via a barrier metal layer.

In one embodiment of the present invention, a connection hole between wiring layers of a circuit portion is formed on the base, and the inside of the connection hole is filled with a conductive filling member, and the barrier metal layer and the conductive layer are formed thereon. A layer is formed, and a lower layer wiring existing at the bottom of the connection hole and an upper layer wiring formed by a conductive pattern formed by patterning the conductive layer and the barrier metal layer and an upper layer wiring formed by the barrier metal pattern are electrically connected by a conductive filling member. Electrical conduction.

In one embodiment of the present invention, a barrier metal layer is formed on the inner surface of the connection hole and on the surface of the lower wiring existing at the bottom of the connection hole, and the connection hole is formed through the barrier metal layer through the conductive metal. And filling the conductive filling member with the lower wiring existing at the bottom of the connection hole via a barrier metal layer.

In one embodiment of the present invention, a concavo-convex pattern forming an alignment mark is formed on the surface of the base in the alignment mark portion, and the conductive layer is formed on the concavo-convex pattern.

In the present invention as described above, the surface of the base can be constituted by an interlayer insulating film.

In the present invention as described above, a TiN layer, a TiN / Ti layer, a TiN layer,
A W layer, a TiON layer, a WN layer, a Ta layer, or a TaN layer can be used.

In the present invention as described above, the conductive layer may be an Al layer, an AlSi layer, an AlCu layer or an A layer.
An lSiCu layer can be used.

In the present invention as described above, the conductive layer such as the Al layer can be formed by a high-temperature sputtering method (including a multi-step high-temperature sputtering method) such as a high-temperature Al sputtering method.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic partial sectional view showing a first embodiment of a semiconductor device according to the present invention, and FIGS. 2 and 3 are schematic partial sectional views showing a manufacturing process of the semiconductor device of the present embodiment. is there. In these figures, a circuit portion on which wiring is formed and an alignment mark portion used for alignment are shown.

In manufacturing the semiconductor device of this embodiment, first, as shown in FIG. 2A, after forming an element or the like on a silicon substrate (not shown), a first interlayer insulating film 1 is formed thereon. To form the first wiring 2 as a lower layer wiring. Under the first wiring 2, a barrier metal layer 3 having the same pattern as the first wiring 2 is formed. A second interlayer insulating film 4 is formed so as to cover them. The first wiring 2 is formed in the circuit portion on the wafer, but no wiring is formed in the alignment mark portion. The surface of the base is formed by the second interlayer insulating film 4.

Thereafter, as shown in FIG. 2B, a photoresist is applied to the entire surface of the wafer in order to form a via hole (connection hole) to the first wiring 2 in the second interlayer insulating film 4, and pattern exposure is performed. And development to form a resist pattern 5 at a desired location. At this time, a resist pattern 5 corresponding to a desired concavo-convex pattern is also formed on the alignment mark portion.

Thereafter, as shown in FIG. 2C, the second interlayer insulating film 4 is etched by dry etching or the like using the resist pattern 5 as a mask to form a via hole.

Thereafter, as shown in FIG. 3D, a barrier metal (TiN) layer 6 is formed by a reactive sputtering method or the like.
Is formed on the entire surface of the wafer.

Thereafter, as shown in FIG. 3E, a photoresist is applied on the barrier metal layer 6, pattern exposure and development are performed, and patterning is performed to open only the alignment mark portion.

Thereafter, as shown in FIG. 3F, using the resist pattern 7 patterned as described above as a mask, the barrier metal layer 6 is removed by etching using a polyetch solution or the like.

Thereafter, the resist pattern 7 is removed, and Ti is removed to improve the wettability of Al for the upper wiring.
Then, as shown in FIG. 1, an Al layer 8 is formed by a high-temperature Al sputtering method or the like. The Ti film reacts with the Al layer 8 to form a Ti—Al alloy layer 9.

Next, the operation of the present embodiment will be described.

Generally, wafer alignment in a stepper is performed by an optical method. In the case of the interferometric search, the alignment mark portion is irradiated with a laser and scanned. Since the intensity of the interference light changes due to the interference at the mark portion, virtual coordinates of the peak on the wafer are obtained. This is performed at several points on the wafer surface to perform alignment. In the case of the image processing type search, a microscope image is obtained by irradiating the alignment mark portion with a halogen lamp or the like. Virtual coordinates on the wafer are obtained from the contrast of the image. This is performed at several points on the wafer surface to perform alignment.

In this embodiment, as shown in FIG. 4A, the barrier metal layer 6 is removed only in the alignment mark portion, so that the surface of the Al layer 8 is smooth in the alignment mark portion where the barrier metal layer 6 does not exist. is there. FIG. 4B shows a signal waveform of the image processing type search in this case.
Since the surface of the Al layer at the alignment mark portion is smooth, the S / N ratio of the contrast is improved, and a good signal waveform is obtained.

In general, the displacement measurement is also performed by an optical method. A microscope image is obtained by irradiating a position difference measuring mark portion with a halogen lamp or the like. From the contrast of this image, the difference in position between the lower layer pattern and the current pattern is measured.

FIG. 5A shows a cross section of the mark portion for measuring the displacement, and the signal waveform obtained from this mark portion is shown in FIG.
(B). From these signal waveforms, L1 shown in FIG.
And L2, and the displacement amount ΔL is ΔL = (L1−L
2) Calculate as / 2. Since the Al surface of the misalignment measurement mark portion where the barrier metal layer 6 does not exist is smooth, the signal waveform from the lower layer pattern (in this case, the pattern when the connection hole is formed) has a small noise locally.
Thus, the peak of the signal waveform becomes clear, and the difference from the reflection from the photoresist pattern 10 showing the current pattern can be accurately measured.

The surface condition of the Al layer formed by high-temperature Al sputtering or the like depends on the presence or absence of a barrier metal layer below the Al layer, as shown in FIG. The value of the Al surface reflectance in FIG. 6 is expressed assuming that the surface reflectance of bare Si is 100%. The surface reflectance of Al shown here is Al
It is related to the surface irregularities. That is, when the degree of the irregularities on the surface of the Al layer is large, the scattering of light increases and the surface reflectance decreases. When there is no barrier metal layer, the reflectance is high and A
The surface condition of the l layer is relatively smooth. On the other hand, when the Al layer is formed on the barrier metal TiN single layer, the reflectance is low, and the degree of irregularities on the surface of the Al layer is large. This Al
Although the surface reflectivity of the layer is desirably 150% or more, according to the present embodiment, a surface reflectivity of about 200% is obtained. It is equivalent to the reflectance.

The operation and effect of this embodiment is that the barrier metal layer in a region including accessories such as an alignment mark and a misalignment measurement mark (in the present invention, these are collectively referred to as an “alignment mark portion”) is removed. In this way, the degree of unevenness of the surface state of the Al layer in the alignment mark portion is reduced and smoothed, so that the surface reflectance is improved, and alignment and displacement measurement can be performed easily and accurately. .

A comparison between the misalignment measurement error performed using the above-described semiconductor device of the present embodiment and the misalignment measurement error performed using the conventional semiconductor device having an Al layer formed by using a high-temperature Al sputtering method is compared. As a result, the device using the present embodiment was reduced to about 67% of the device using the conventional device. As described above, the measurement error when the present invention is applied is reduced, the deviation from the standard is reduced, and the productivity is improved.

FIG. 7 is a schematic partial sectional view showing a second embodiment of the semiconductor device according to the present invention, and FIG. 8 is a schematic partial sectional view showing a manufacturing process of the semiconductor device of the present embodiment. In these figures, the same parts as those in FIGS. 1 to 5 are denoted by the same reference numerals.

In manufacturing the semiconductor device of this embodiment, first, as shown in FIG. 8A, after forming an element or the like on a silicon substrate (not shown), a first interlayer insulating film 1 is formed thereon. To form the first wiring 2 as a lower layer wiring. Under the first wiring 2, a barrier metal layer 3 having the same pattern as the first wiring 2 is formed. A second interlayer insulating film 4 is formed so as to cover them. The first wiring 2 is formed in the circuit portion on the wafer, but no wiring is formed in the alignment mark portion. The surface of the base is formed by the second interlayer insulating film 4. Up to this point, the operation is the same as in the first embodiment.

In this embodiment, as shown in FIG. 8A, a barrier metal (TiN) layer 6 is formed on the entire surface of the second interlayer insulating film 4 by a reactive sputtering method or the like.

Thereafter, as shown in FIG. 8B, a photoresist pattern is formed, the barrier metal layer 6 is partially removed by wet etching, and the second interlayer insulating film 4 is formed.
Is partially removed by dry etching to form a via hole to the first wiring 2 in the circuit section. that time,
At the same time, a desired concavo-convex pattern (opening) is formed also on the alignment mark portion.

Thereafter, as shown in FIG. 7, a Ti film is formed to improve the wettability of Al for the upper layer wiring,
An Al layer 8 is formed by a sputtering method or the like. Ti film is A
It reacts with the I layer 8 to form the Ti—Al alloy layer 9.

Also in the present embodiment, by removing the barrier metal layer in the alignment mark portion, the degree of unevenness of the surface state of the Al layer 8 in the alignment mark portion is reduced and smoothed, the surface reflectance is improved, and In addition, the same operation and effect as in the first embodiment described above that the alignment and the amount of displacement can be accurately measured can be obtained.

In addition, in this embodiment, the removal of the barrier metal layer in the alignment mark portion and the formation of the opening pattern in the alignment mark portion can be performed by one-time photoresist film formation, so that the process is simplified. There is an advantage that it is done.

In the above description, T is used as the barrier metal layer.
Although the description has been given with respect to the iN layer, other examples of the barrier metal layer include a TiN / Ti layer in which a TiN film is laminated on a Ti film.
It is also possible to use a layer, a TiW layer, a TiON layer, a WN layer, a Ta layer, a TaN layer, or the like.

In the above description, Al is used as the conductive layer.
The layer is described, but other conductive layers such as AlS
It is also possible to use an i layer, an AlCu layer, an AlSiCu layer, or the like.

Further, in the above embodiment, the interlayer insulating film 4
When the conductive layer is formed on the surface of the substrate, the conductive layer fills the via hole of the circuit portion at the same time (that is, the via hole is filled with the same material as the wiring pattern). Is filled with a conductive filling member (plug: made of, for example, tungsten) made of a different material from the conductive layer used to form the wiring pattern, and then a barrier metal for forming an upper wiring pattern is formed. A layer and a conductive layer may be formed.

The high-temperature sputtering method such as the high-temperature Al sputtering method may be a multi-step high-temperature sputtering method such as the multi-step high-temperature Al sputtering method.

[0060]

As described above, according to the present invention,
By removing the barrier metal layer at the alignment mark portion when forming the conductive layer on the alignment mark portion performed at the time of forming the conductive layer on the barrier metal layer in the circuit portion, the high temperature Al sputtering method or the like can be used. Improves the surface condition of the formed conductive layer such as Al at the alignment mark part, facilitates the alignment when forming the upper wiring pattern by patterning the barrier metal layer and the conductive layer in the circuit part, and the alignment accuracy. Can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a schematic partial cross-sectional view showing a manufacturing process of the first embodiment of the semiconductor device according to the present invention.

FIG. 3 is a schematic partial cross-sectional view showing a manufacturing process of the first embodiment of the semiconductor device according to the present invention.

FIG. 4 is a schematic partial cross-sectional view of an alignment mark portion of the semiconductor device according to the first embodiment of the present invention, showing a signal waveform obtained from the mark portion.

FIG. 5 is a schematic partial cross-sectional view of a misalignment measurement mark portion of the semiconductor device according to the first embodiment of the present invention, showing a signal waveform obtained from the mark portion.

FIG. 6 shows A of the first embodiment of the semiconductor device according to the present invention;
5 is a graph showing the surface reflectance of an l layer in comparison with that of another Al layer.

FIG. 7 is a schematic partial cross-sectional view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 8 is a schematic partial sectional view showing a manufacturing process of a second embodiment of the semiconductor device according to the present invention.

FIG. 9 is a schematic partial cross-sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 10 is a schematic partial sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 11 is a schematic partial sectional view of an alignment mark portion of a conventional semiconductor device and a diagram showing a signal waveform obtained from the mark portion.

FIG. 12 is a schematic partial cross-sectional view of a misalignment measurement mark portion of a conventional semiconductor device and a diagram showing a signal waveform obtained from the mark portion.

FIG. 13 is a schematic partial sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st interlayer insulating film 2 1st wiring (lower wiring) 3 barrier metal layer 4 2nd interlayer insulating film 5 photoresist pattern 6 barrier metal layer 7 photoresist pattern 8 Al layer 9 Ti-Al alloy layer 10 photoresist pattern

Claims (11)

(57) [Claims] A barrier metal layer is provided on an underlayer surface.
Conductive pattern with conductive layer via rear metal pattern
In the semiconductor device in which the conductive layer is formed with the wiring in the circuit portion and the alignment mark,
And the barrier metal pattern is interposed between the conductive pattern and the base in a region other than the alignment mark portion, and the alignment mark portion is provided on the surface of the base.
The conductive layer is formed without interposing a barrier metal layer
A semiconductor device characterized by being performed . 2. The semiconductor device according to claim 1, wherein a surface of said base is made of an interlayer insulating film. 3. A being the uneven pattern on the surface of the base constituting the alignment mark is formed in the alignment mark portion, wherein the conductive layer on uneven pattern is formed, claims The semiconductor device according to any one of claims 1 and 2 . Wherein said barrier metal layer is TiN layer, TiN
4. The semiconductor device according to claim 1 , wherein the semiconductor device is a Ti layer, a TiW layer, a TiON layer, a WN layer, a Ta layer, or a TaN layer. 5. The semiconductor device according to claim 1, wherein the conductive layer is an Al layer, an AlSi layer, an Al layer.
A Cu layer or an AlSiCu layer,
The semiconductor device according to claim 1 . 6. A conductive layer is formed on a surface of an underlayer via a barrier metal layer, and a conductive pattern formed by the conductive layer is formed to align with at least a part of a wiring of a circuit portion.
A method of manufacturing a semiconductor device for forming a mark portion , comprising: forming a barrier metal layer on a surface of the base; and patterning the barrier metal layer to form the alignment.
Removing the barrier metal layer of the mark portion; forming the conductive layer on the barrier metal layer of the circuit portion and on the base of the alignment mark portion; and forming the conductive layer and the conductive layer on the circuit portion. Patterning the barrier metal layer. A method for manufacturing a semiconductor device, comprising: 7. The surface of the undercoat is characterized in that it is constituted by the interlayer insulating film, a method of manufacturing a semiconductor device according to claim 6. 8. A forming an uneven pattern constituting the surface alignment mark of the base in the alignment mark portion, and forming the conductive layer on the concavo-convex pattern, any claim 6-7 13. A method for manufacturing a semiconductor device according to 9. The barrier metal layer is a TiN layer, TiN
9. The method of manufacturing a semiconductor device according to claim 6 , wherein the semiconductor device is a Ti layer, a TiW layer, a TiON layer, a WN layer, a Ta layer, or a TaN layer. Wherein said conductive layer is Al layer, AlSi layer, A
The method of manufacturing a semiconductor device according to claim 6 , wherein the method is an lCu layer or an AlSiCu layer. 11. The method according to claim 10 , wherein said conductive layer is formed by a high-temperature sputtering method.