GB2339072A

GB2339072A - A semiconductor device having an alignment mark

Info

Publication number: GB2339072A
Application number: GB9914942A
Authority: GB
Inventors: Yoshiaki Yamamoto
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1998-06-26
Filing date: 1999-06-25
Publication date: 2000-01-12
Anticipated expiration: 2019-06-25
Also published as: JP3196200B2; KR20000006483A; GB2339072B; GB9914942D0; JP2000021880A

Description

2339072 SENUCONDUCTOR DEVICE HAVING AN ALIGNMENT MARK AND MANUFACTURING

METHOD THEREFOR

BACKGROUND OF THE INVENTION 5 Field of the Invention

The present invention relates to a semiconductor device. In particular, one with high alignment precision for pattering and forming necessary elements such as the interconnection, as p art of the conductive layer. It also relates to a method of manufacturing the semiconductor device.

Description of the Related Art

In recent years, semiconductor integrated circuits such as LSI (LargeScale Integration) have been developed and mounted in high-density packaging as their size has gotten smaller. Accordingly, the diameter of the via hole, which is formed in an inter-layer insulating layer and connects the upper-interconnection wiring to lower-interconnection wiring, has become shorter. In addition, the aspect ratio has become greater than 1. The upper interconnection generally is formed by depositing an Al (aluminum) layer using the sputtering process. However, it is difficult for a via hole with its aspect ratio being equal to or greater than 1 to provide sufficient step-coverage, thereby causing problems with reliability.

In order to improve the insufficient step coverage, techniques for filling the via hole with aluminum, dependent upon the multi-step controlled high temperature/aluminum sputtering process, have been proposed. This process is disclosed in, for example, Japanese Patent Application Laid-open No.

2 Sho-64-76736. The techniques for filling the via hole with aluminum dependent upon the multi-step controlled high temperature/ aluminum sputtering process will be described below while referencing the drawings. In these drawings the circuit formation region in which an interconnection is 5 formed and the alignment mark formation region are illustrated.

In Fig.1a, a device is formed on a silicon substrate. (The silicon substrate is not shown in the illustration). The first inter-layer insulating layer 1 is formed next. The first interconnection (an underlayer interconnection) 2 is then formed above the first inter-layer insulating layer 1.

In this figure, reference numeral 3 denotes the barrier metal layer. The reafter, a second inter-layer insulating layer 4 is formed over the entire surface of the substrate. A via hole 30 toward the first interconnection 2 and an alignment mark 20 having a concave shape are formed next, in the second inter-layer insulating layer 4. Then a barrier metal layer 6 is formed on the second inter-layer insulating layer 4 and in the via hole.

In Fig. 1b, a Ti (titanium) layer 11 is then formed, covering the entire surface of the wafer. The Ti layer serves to increase the wettability of an aluminum layer, which will be formed on the resulting surface.

Next a shown in Fig. 1c, without breaking the vacuum of the processing apparatus, the first aluminum layer 12 is deposited at a high deposition rate using low temperature. As a result, a continuous layer of aluminum is formed.

Next, as shown in Fig. 2, without breaking the vacuum of the processing apparatus, the second aluminum layer 8 is deposited at a low 3 deposition rate using a higher tempe rature. This high temperature low deposition-rate process causes a surface-diffusion of the aluminum, so that the via hole is filled-in with the layer of aluminum. At this point the Ti layer 11 reacts with the first aluminum layer 12 (see Fig. 1c), forming a TiAl alloy 9.

However, filling the via hole by using the process as described above, allows an outgassing to be released from the inter-layer insulating layer 4 (an under-layer) and enter a sputtering chamber, thereby deteriorating the atmosphere in the chamber, and possibly prohibiting the surface diffusion of aluminum to occur. As a result, the via hole may be poorly filled, and the reliability of a semiconductor apparatus, which is structured with the semiconductor device including the via hole, may also go down. Accordingly, in order to completely and invariably fill the via hole, the amount of outgassing given off into the sputtering chamber needs to be decreased. Therefore, the barrier metal layer 6 is formed on the inter- layer insulating layer 4 in the process as described above. A TiN layer or a TiN/Ti layer (which is made of a TiN layer and a TiN layer on the Ti layer) is preferably used for the barrier metal layer 6.

However, the present inventor discovered that the surface of the aluminum layer, which has been formed on the barrier metal layer by using the aluminum sputtering process, which is performed in a high temperature, or other related processes, is very uneven, so the optical reflectance of the surface is low. Although it is not the intention of the present inventor to be limited to a particular theory on the mechanism of the foregoing, it is believed that when an aluminum layer is formed on a barrier metal layer such as TiN, 4 the aluminum layer grows under the influence of the crystallographic orientation of the barrier metal layer. Therefore, the degree of ordering with respect to the proper orientation of the aluminum layer (1,1,1) becomes small and an unevenness of the aluminum layer's surface is enhanced When the very uneven aluminum layer is patterned so as to form an aluminum interconnection, it is difficult for the stepper make an alignment and also to measure a possible misregistration after a wafer-alignment has been made. This emanates from that fact that the methods of making a wafer-alignment and measuring a possible misregistration are based upon an optical approach. The problem as described above will be explained below in more detail while referencing the figures.

The configuration of the alignment mark formation region, which has been formed by using the above process steps as described in conjunction with Figs. 1 and 2, is illustrated in Fig. 3a. Since the high temperaturefsputtered aluminum layer 8 has been formed on the barrier metal (TiN) layer 6, the surface of the aluminum layer 8 is very uneven. The signal waveform, which is obtained by measuring the reflection intensity corresponding to the depth of surface in the alignment mark formation region, is shown in Fig. 3b. In this figure, the signal waveform fluctuates sharply, indicating that the surface of the aluminum layer is uneven. This may cause an alignment error in the stepper.

In addition, it is difficult to measure the possible misregistration, even though no alignment error occurs. Fig. 4a shows the configuration of a mark formation region for measurement of a possible misregistration. As shown in Fig. 4b, the signal waveform, corresponding to both the underpattern (the concave region formed in the inter-layer insulating layer 4, which is in the mark formation region for measurement of a possible misregistration) and the latest pattern (photo resist pattern 10), greatly fluctuates. This 5 occurs because it is influenced by the uneven surface of the aluminum layer 8. Accordingly, the signal waveform corresponding to the under-pattern is not clear, so the measurement error is large, and the reproducibility in the measurement gets worse. This causes a great deal of deterioration of the productivity of semiconductor devices.

There is another factor underlying the difficulty in measuring a possible misregistration: the edges of the aluminum layer in the alignment mark formation region (and in the mark formation region for measuring a possible misregistration) are not sharp due to a migration of aluminum. This problem is disclosed in Japanese Patent Application Laid- open No. Hei-5- 152446. In the Laid-open, the proposed solution to the problem would be to form an aluminum layer in the alignment mark formation region as conformably as possible. The solution will be described below in more detail, while referencing Fig. 5.

Once a via hole toward the under-interconnection 2 has been formed, 20 a Ti layer 11 is conformably formed, as shown in Fig. 5a. Next, as shown in Fig. 5b, an aluminum layer 14 is formed at a high temperature. Wherein, part of the aluminum layer reacts with the Ti layer 11, forming a Ti/Al alloy layer 13, and the remainder of the aluminum layer 14 is left unreacted as it is. As a result, the TVAI alloy layer 13 is conformably formed in the alignment 6 mark formation region, and the via hole is filled with Ti/Al alloy layer 13. This prevents a formation of gently sloped edges in the alignment mark formation region.

However, with the process steps as described above, there is the 5 following problem. That is to say, even though the aluminum layer has been conformably formed in the alignment mark formation region by using the above process steps, the unevenness of the surface of the aluminum layer is very high in the case that the barrier metal is used. This can lead to difficulty in keeping the alignment tolerances high for patterning and forming an interconnection such as the aluminum interconnection. SUNMARY OF THE INVENTION Accordingly, an objective of the present invention is to provide a semiconductor device, which has an improved surface of a metal layer such as an aluminum layer in an alignment region. Wherein, the metal layer is formed in an alignment mark formation region at the same time that a via hole is filled with a metal such as aluminum by using the hightemperature/aluminum sputtering process. The improved surface allows an improvement of alignment tolerances for patterning and forming an interconnection such as an aluminum interconnection. Another objective of the present invention is to provide a method of fabricating the above semiconductor device, according to the present invention.

To attain the above objective, according to an aspect of the present invention, a semiconductor device is provided, comprising: a circuit formation region and an alignment mark formation region; an underlying layer formed in 7 the circuit formation region and the alignment mark formation region; an insulating film covering the underlying layer; a contact hole formed in the insulating film in the circuit formation region; an alignment mark formed in the insulating film in the alignment mark formation region; and a barrier metal film formed on the insulating film in a region other than the alignment mark.

According to another aspect of the present invention, a semiconductor device manufacturing method is provided, comprising forming an insulating film; forming an alignment mark in the insulating film; forming a barrier metal film on the insulating; and selectively removing the barrier metal film on the alignment mark.

According to the present invention, the surface state of the conductive layer such as an aluminum layer in the alignment mark formation region is improved. Thus the alignment precision is improved.

BRIEF DESCRIPTION OF DRAWINGS

The above and other objects, features and advantages of the present invention, will become apparent from the following detailed description in the embodiment section, in the embodiment section, when taken in conjunction with the accompanying drawings, wherein:

Figs. la to 1c illustrate process cross sections showing the process steps of manufacturing the conventional semiconductor device; Fig. 2 illustrates a process cross section showing a process step of manufacturing the conventional semiconductor device; 8 Fig. 3a and Fig. 3b, respectively, illustrate a process cross section of the alignment mark formation region in the conventional semiconductor device, and the signal waveform obtained from the mark formation region; Fig. 4a and Fig. 4b, respectively, illustrate a cross section of the mark formation region for the measurement of a misregistration in the conventional semiconductor device, and the signal waveform obtained from the mark formation region; Fig. 5a and Fig. 5b, respectively, illustrate process cross sections showing the process steps of manufacturing the conventional semiconductor device; io Fig. 6 illustrates a cross section showing a semiconductor device, according to the first embodiment of the present invention; Figs. 7a to 7g illustrate process cross sections showing the process steps of manufacturing the semiconductor device, according to the first embodiment of the present invention; Fig. 8a and Fig. 8b, respectively, illustrate a cross section of the alignment mark formation region in the semiconductor, according to the first embodiment of the present invention, and the signal waveform obtained from the mark formation region; Fig. 9a and Fig. 9b, respectively, illustrate a process cross section of the mark formation region for the measurement of a misregistration in the conventional semiconductor device, according to the first embodiment of the present invention, and the signal waveform obtained from the mark formation region; 9 Fig. 10 is a graph showing the reflectance ratio of the surface of the aluminum layer in the semiconductor device, according to the first embodiment of the present invention, in comparison to the conventional aluminum layer; Fig. 11 illustrates a cross section showing a semiconductor, according to the 5 second embodiment of the present invention; and Fig. 12a to Fig. 12c illustrate process cross sections showing the process steps of manufacturing the semiconductor, according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EM]BODMENTS (First embodiment) Hereafter, a semiconductor device, according to a first embodiment of the present invention, will be explained with reference to the drawings.

Fig. 6 illustrates partial cross sections of the semiconductor device, according to the first embodiment of the present invention, whereas Fig. 7 illustrates process cross sections showing the process steps of manufacturing the semiconductor device. A circuit formation region, in which an interconnection is formed, and an alignment mark formation region, which is utilized for making an alignment, are both illustrated in these Figures. Further, the alignment mark formation region is provided in a scribe region of a wafer.

In the process of manufacturing the semiconductor device of the first embodiment, predetermined devices (not shown in the figures) are formed on a silicon substrate (also not shown in the figures). This is followed by a formation of the first inter-layer insulating layer 101 on the resulting surface of the substrate (see Figs. 6 and 7a). A barrier metal layer 103 and a first interconnection 102, which is an under-interconnection, are both formed next and have the same pattern, as illustrated in Fig. 7a The first interconnection 102 is made of Al or alloy which includes Al (AlCu, AlSi, AlSiCu). Next, the second inter-layer insulating layer 104 is formed, so as to cover the two layers 102 and 103. It should be noted that the first interconnection 102 has been formed in the circuit formation region of the semiconductor device, whereas no interconnection is formed in the alignment mark formation region.

Thereafter, as shown in Fig. 7b, in order to form a via hole on top of the first interconnection and within the second inter-layer insulating layer 104, a coating of photo resist is applied to the entire surface of the substrate. A resist pattern 5 is formed next at predetermined places through a pattern exposure process and a development process. At the same time, a resist pattern 5 corresponding to a predetermined concave and convex pattern is also formed in the alignment mark formation region.

Next, as shown in Fig. 7c, using the resist pattern 5 as a pattern mask, the second inter-layer insulating layer 104 is etched through, for example, a dry-etching process, so as to form a via hole 300 and an alignment mark 200 having a concave shape.

Thereafter, as shown in Fig. 7d, a barrier metal (TiN) layer 106 is formed on the entire surface of the wafer by using a reactive sputtering process or other related processes for prevention of outgassing..

As shown in Fig. 7e, a mask layer of photo resist, which exposes the I I alignment mark and an surrounding portion of the alignment mark, is formed. The distance from an edge of the alignment mark to an edge of the mask layer is preferably more than 50pm.

As shown in Fig. 7f, using the resist pattern 107 patterned above as a pattern mask, the barrier metal layer 106 is wet-etched with the assistance of the APM (Ammonium hydroxide Peroxide Mixture), etc.

As shown in Fig. 7g, the resist pattern is then removed and a Ti layer 111, the thickness of which is more than 50A, preferably 300-400A, is deposited on the resulting surface so that the wettability of the aluminum layer to be used as an upper interconnection is improved.

Next, as shown in Fig. 6, using the high-temperature/aluminum sputtering process or other related processes, an aluminum layer 108 is formed. The Ti layer 111 reacts with the aluminum layer 108, forming a Ti/Al alloy layer 109.

The operation of the first embodiment will be described below.

Usually, the wafer alignment, which is made by the stepper, utilizes an optical method. In the case of using the LSA (Laser Step Alignment) method, a light emitted from a laser is applied to an alignment mark formation region and scanned. When a mutual interference between the lights occurs, a pattern of varying intensities of lights or an interference fringe is generated in the alignment mark formation region, thereby allowing virtual coordinates corresponding to their peaks on the wafer to be obtained. The above operation is further done at the other points in the wafer, and an alignment can be made successfully. On the other hand, when using the FIA (Field

12 Image Alignment) method, a light emitted from a halogen lamp, etc. is applied to the alignment mark formation region, and causes a microscopic image to be generated there. This contrast in the image gives virtual coordinates on the wafer. The same procedure as described above is performed at several other 5 points on the wafer so that an alignment can be made successfully.

In this embodiment, as shown in Fig. 8a, only the barrier metal layer 106 in the alignment mark formation region is removed, so that the surface of the aluminum layer 108 in the alignment mark formation region, where no barrier metal layer 106 exists, is kept smooth. Fig. 8b shows a lo signal waveform, corresponding to the configuration as shown in Fig. 8a, which is obtained by using the FIA method. As is apparent from Fig. 8b, the SIN (Signal to Noise) ratio in contrast is improved and the improved signal waveform can be obtained on account of the surface of the aluminum layer in the alignment mark formation region being formed smoothly.

Further, not only the barrier metal film on the alignment mark but also that on the surrounding portion of the alignment mark are removed. Therefore, the good signal waveform can be also obtained in the edge of the alignment mark 300.

The measurement of misregistration is also generally performed using an optical method. For example, a light emitted from a halogen lamp, etc. is applied to the mark formation region for a misregistration measurement, generating a microscopic image. The contrast in the image enables a measurement of the difference in location between the under- layer pattern and the current pattern.

13 Fig. 9a illustrates a cross section in the mark formation region for a misregistration measurement, whereas Fig. 9b illustrates a signal waveform obtained from the mark formation region. Distances Li and L2, as shown in Fig. 9b, are calculated from the signal waveform obtained, and an amount of 5 misregistration, A L, is calculated from the equation: A L = (L1 L2) / 2. Because no barrier metal layer 106 exists on the surface of the hole in the mark formation region for a misregistration measurement, the surface of the aluminum layer is smooth. Consequently a small amount of noise is obtained from the under-layer pattern and is locally superimposed on the signal waveform. Accordingly, the peaks in the signal waveforms are clear, so a precise measurement of the difference from the photo resist pattern 110, which is the current pattern, can be made.

Incidentally, the surface state of the aluminum layer 108, which has been formed by using the high temperature/Aluminum sputtering process or other related processes, depends upon whether or not a barrier metal layer exists under the aluminum layer 108, as shown in the graph of Fig. 10. The Y-coordinate in the graph of Fig. 10 denotes the reflectance ratio on the surface of the aluminum layer, using the premise that the surface reflectance ratio of bare silicon is 100%. The reflectance ratio on the surface of the aluminum layer can be inversely correlated to the roughness of the surface. In other words, the greater the roughness of the surface of the aluminum layer, the more the scattered light increases, and at the same time, the reflectance ratio decreases. Not having a barrier metal layer provides both a high reflectance ratio and a comparatively smooth surface of an aluminum layer. Conversely, 14 the formation of an aluminum layer on a single barrier metal (TiN) layer provides both a low reflectance ratio and a very rough surface on the aluminum layer. It is preferable for the aluminum layer to have a reflectance ratio equal to or greater than 150%. According to the first embodiment of the present invention, a reflectance ratio of approximately 200% is provided. This figure is equivalent to the reflectance ratio on an aluminum layer formed using the conventional process steps, not the high temperature/Aluminum sputtering process.

In summary, according to the first embodiment of the present invention, the reflectance ratio of the surface is improved, allowing an alignment to be done precisely and with ease, as well as a measurement of a possible misregistration. These advantages emanate from the fact that the barrier metal layer is removed in the alignment mark formation region, so as to decrease the roughness of the surface of the aluminum layer into a smooth surface.

As a result of the experimental evaluation of a misregistration measurement error of the semiconductor device conducted according to the first embodiment of the present invention, we have learned that the misregistration measurement error occurring on the semiconductor device, according to the first embodiment of the present invention, has been improved to be approximately 67% of that of conventional semiconductor devices. As described above, with the semiconductor device, according to the present invention, the measurement error decreases, thus the number of rejects decreases. Accordingly, the productivity of the semiconductor device is improved. (Second embodiment) Next, a semiconductor device, according to the second embodiment of the present invention, will be explained below with reference to the drawings.

Fig. 11 illustrates a cross-section of the semiconductor device, according to the second embodiment, whereas Figs. 12a to 12c illustrate the process steps of manufacturing the semiconductor device. In these figures, the same reference numerals as those in Figs. 6 to 9 are attached to the same elements in Figs. 6 to 9.

In the manufacturing process of the semiconductor device, according to the second embodiment, as shown in Fig. 12a, we assume that necessary devices have been formed on a silicon substrate (not shown in the Figure). The first inter-layer insulating layer 101 is then formed on the above resulting surface of the silicon substrate. A barrier metal layer 103 is formed next, on the first inter-layer insulating layer 101, followed by the formation of the first interconnection 102. Next, the second inter-layer insulating layer 104 is formed all over the resulting surface of the previous formation process. It is noted that the first interconnection 102 is formed in the circuit formation region of the substrate, but not formed in the alignment mark formation region.

The process steps up to this point are the same as those in the first embodiment.

In the second embodiment, as shown in Fig. 12a, a barrier metal layer (TiN) 106 is formed on the second inter-layer insulating layer 104 by using the reactive sputtering process for prevention of outgassing.

16 Thereafter, a photo resist pattern (not shown in the Figure) is formed, and the barrier metal layer is wet-etched with the assiststance of the APM, etc. to be partly removed. Then, the removed part of the barrier metal layer 106 is larger than the opening of the photo resist pattern. Next, using the same resist pattern as a pattern mask, the second inter-layer insulating layer 104 is etched through, for example, a dry-etching process, so as to form a via hole 300 and an alignment mark 200 having a concave shape(see Fig. 12b).

As shown in Fig.12c, a Titanium (Ti) layer 111 is depoisited so that the wettability of an aluminum layer used for an upper-interconnection is improved.

Next, as shown in Fig. 11, an aluminum layer 108 is formed next using the high- temperature/Alu minum sputtering process, etc. The Ti layer Ill reacts with the aluminum layer 108 so as to form a Titanium/Aluminum alloy layer 109.

In this embodiment also, the following results, which are the same as those in the first embodiment, are obtained by removing the barrier metal layer in the alignment mark formation region. This causes the roughness of the surface of the aluminum layer 108 in the alignment mark formation region to be decreased and made smooth, thereby improving the reflectance ratio of the surface and allowing an alignment processing to be easily performed at high alignment tolerances. Moreover, a possible misregistration can be precisely measured.

In addition, in this embodiment, a single formation of a photo resist allows both the removal of the barrier metal layer and the formation of an 17 opening pattern in the alignment mark formation region. Thus, the process steps can be simplified.

Up to this point, the TiN layer, which is used as a barrier metal layer, has been described. However, this embodiment is not limited to the TiN layer.

The barrier metal layer can be alternatively made of. a TiN/Ti layer, which is comprised of a Ti layer and a TiN layer on the Ti layer; a TiW layer; a TiON layer; a VIN layer; a Ta layer; or a TaN layer.

Furthermore, in the above description, an aluminum layer is used for the conductive layer. However, an aluminum/silicon layer, an aluminum/copper layer, or an aluminum/silicon/copper layer can be alternatively used for the conductive layer.

Furthermore, in the above embodiment, a via hole in the circuit formation region is filled with a conductive layer at the same time the conductive layer is formed on the surface of the inter-layer insulating layer 104.

In other words, the via hole is filled with the same material as that of the interconnection pattern. Therefore, the following process can be alternatively used in place of the process steps as described above. That is, another conductive filling material or a plug, such as tungsten, can be used to fill the via hole in the circuit formation region, followed by the formation of a barrier metal layer and the conductive layer in forming an upper-interconnection pattern.

Furthermore, a multi-step controlled high temperature sputtering process such as the multi-step controlled high temperature/aluminum 18 sputtering process can be used in place of a high-temperature sputtering process such as the high-temperature/aluminum sputtering process.

Furthermore, in the above embodiment, an alignment mark having a concave shape is used. However, an alignment mark may have a convex shape.

(Result of the invention) As described above, according to the present invention, in order to facilitate the formation of a conductive layer in an alignment mark formation region when a conductive layer is formed on a barrier metal layer in a circuit formation region, the barrier metal layer is removed form the alignment mark formation region. This allows for an improvement of the surface state of the conductive layer, such as an aluminum layer'in the alignment mark formation region, wherein the conductive layer is formed using the high-temperature/aluminurn sputteringprocess. Therefore, the alignment processes are easily performed for patterning both the barrier metal layer and the conductive layer so as to form an upper-connect pattern, thus improving the alignment tolerances.

While the present invention has been described in connection with certain preferred embodiments, it is to be understood that the subject matter encompassed by the present invention is not limited to those specific embodiments. On the contrary, it is intended to include all alternatives, modifications, and equivalents as can be included within the spirit and scope of the following claims.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

Statements in this specification of the objects or results of the invention relate to preferred embodiments of the invention, but not necessarily to all embodiments of the invention falling within the claims.

The description of the invention with reference to the drawings is by way of example only -

The text of the abstract filed herewith is repeated here as part of the specification.

A semiconductor device, according to the present invention, is comprised of 19 a circuit formation region and an alignment mark formation region. In the alignment mark formation region, the second inter-layer insulating layer 104 is formed on the first inter-layer insulating layer 101, and comprises of a hole. On the other hand, in the circuit formation region, a via hole is formed at the junction of the first interconnection 102, which is formed on a barrier metal layer 103, and in the second inter-layer insulating layer 104. Ile barrier metal layer 103 is formed on the first inter-layer insulating layer 101 and the surface of the via hole is covered by this barrier metal layer 106. A layer of Ti/Al alloy 109 and aluminum layer 108 is then formed on the barrier metal layer 106. Conversely, no barrier metal layer 106 is formed on the surface in the hole in the alignment mark formation region.

WHAT IS CLAUVIED IS:

1. A semiconductor device, comprising:

an insulating film; an alignment mark in said insulating film; a barrier metal film formed on said insulating film; wherein said barrier metal film is not formed on said alignment mark.

2. The semiconductor device as claimed in claim 1, wherein said barrier metal film comprises at least one of TiN layer, TiN/Ti layer, TiW layer, TiON layer, WN layer, Ta layer, and TaN layer.

io 3. A semiconductor device, comprising: a circuit formation region and an alignment mark formation region; an underlying layer formed in said circuit formation region and said alignment mark formation region; an insulating film covering said underlying layer; a contact hole formed in said insulating film in said circuit formation region; an alignment mark formed in said insulating film in said alignment mark formation region; and a barrier metal film for prevention of outgassing formed on said insulating film in a region other than said alignment mark. 4. The semiconductor device as claimed in claim 3, further comprising a wiring layer formed on said underlying layer in said circuit formation region, and wherein a bottom portion of said contact hole exposes a portion of said wiring layer.

21 5. The semiconductor device as claimed in claim 3, further comprising a conductive layer formed in said contact hole, on said barrier metal film and on said alignment mark.

6. The semiconductor device as claimed in claim 5, wherein said conductive 5 layer is a metal layer.

7. The semiconductor device as claimed in claim 5, wherein reflectance of said conductive layer higher on said alignment mark than on said contact hole. 8. The semiconductor device as claimed in claim 5, wherein said conductive layer comprises at least one of aluminum layer, aluminum/silicon alloy layer, io aluminum/copper alloy layer, and aluminum/silicon/copper alloy layer.

9. The semiconductor device as claimed in claim 5, further comprising an alloy layer under said conductive layer, said alloy layer made of titanium and a material constituting said conductive layer.

10. The semiconductor device as claimed in claim 3, wherein said alignment mark is provided in a scribe region of a wafer.

11. The semiconductor device as claimed in claim 3, wherein said alignment mark has a concave shape.

12. The semiconductor device as claimed in claim 3, wherein said underlying layer is an interlayer insulating film.

13. The semiconductor device as claimed in claim 3, wherein said barrier metal film comprises at least of. TiN layer, TiN/Ti layer, TiW layer, TiON layer, WN layer, Ta layer, and TaN layer.

14. A semiconductor device manufacturing method, comprising: forming an insulating film; 22 forming an alignment mark in said insulating film; forming a barrier metal film for prevention of outgassing on said insulating; and selectively removing said barrier metal film on said alignment mark.

15. The semiconductor device manufacturing method as claimed in claim 13, further comprising: forming a mask layer which exposes a portion of said barrier metal film in an alignment mark formation region; and wherein said selectively removing said barrier metal film is performed by etching using said mask layer as a mask. 16. The semiconductor device manufacturing method as claimed in claim 15, wherein said forming said barrier metal film is performed before said forming said alignment mark, and wherein said forming said alignment mark and said selectively removing said barrier metal film is performed by etching using said mask layer as a mask 17. The semiconductor device manufacturing method as claimed in claim 16, further comprising: forming a wiring layer under said insulating film in a circuit formation region; and forming a contact hole which exposes a portion of said wiring layer in said insulating layer; wherein said mask layer further exposes a portion of said barrier metal over said wiring layer; and 23 wherein said forming said contact hole is performed by using said mask layer as a mask simultaneously with said forming said alignment mark.

18. The semiconductor device manufacturing method as claimed in claim 17, further comprising forming a conductive layer on said barrier metal film, in 5 said alignment mark and in said contact hole.

19. The semiconductor device manufacturing method as claimed in claim 18, wherein said conductive layer is an aluminum layer, an aluminum/silicon layer, an aluminum/copper layer, or an alum inum/silicon/copper layer.

20. The semiconductor device manufacturing method as claimed in claim 18, 10 further comprising directly depositing a titanium layer on said barrier metal film in said circuit formation region and on said insulating film in said alignment mark formation region.

21. The semiconductor device manufacturing method as claimed in claim 20, wherein said titanium layer reacts. with said conductive layer to form an alloy 15 layer which is made of titanium and material composing said conductive layer under said conductive layer.

22. The semiconductor device manufacturing method as claimed in claim 15, wherein said mask layer exposes said barrier metal film on said alignment mark and said barrier metal film of an surrounding portion of said alignment mark.

23. The semiconductor device manufacturing method as claimed in claim 14, wherein said barrier metal film comprises at least one of Ti layer, TiN/Ti layer, TiW layer, TiON layer, WN layer, Ta layer, and TaN layer.

24. The semiconductor device manufacturing method as claimed in claim 18, 24 wherein said forming said conductive layer is performed by a sputtering method. 25. The semiconductor device manufacturing method as claimed in claim 14, wherein said alignment mark is provided in a scribe region of a wafer. 26. A semiconductor device or a method substantially as herein described with reference to or as shown in any of figures 6 to 12 of the accompanying drawings.