JP3194834B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer capable of speeding up a frequency switching operation when a plurality of frequencies are appropriately switched and output using a phase locked loop circuit.

[0002]

2. Description of the Related Art Recently, a frequency synthesizer has become an extremely important part in configuring a multi-channel radio transceiver. Then, in order to shorten the channel switching time of the wireless transceiver, a method of obtaining a predetermined output frequency by switching the frequency division ratio of the variable frequency divider and the reference oscillator in the PLL loop and the constant of the loop filter has been proposed. It is described in JP-A-4-22222 and JP-A-4-266220.

FIG. 5 is a block diagram showing a schematic configuration of an example of such a conventional frequency synthesizer. In the figure, 1 is a reference oscillator, 2 is a first variable frequency divider for dividing the output of the reference oscillator, 3 is a phase comparator, 4 is a phase comparator 3
A loop filter 5 for removing a high-frequency component of the output of the filter 5 is a voltage-controlled oscillator whose oscillation frequency is controlled in accordance with the output of the loop filter. Reference numeral 6 denotes a second variable frequency divider, which receives a part of the output of the voltage controlled oscillator 5, divides the frequency by N, and inputs the divided frequency to the phase comparator 3. The phase comparator 3 is connected to the first
And the output phases of the second variable frequency dividers 2 and 6 are detected. A control unit 7 controls the first variable frequency divider 2, the loop filter 4, and the second variable frequency divider 6.

Next, the operation will be described. The signal from the reference oscillator is frequency-divided by Nr in the first variable frequency divider 2 and the output signal is frequency-divided by N in the second variable frequency divider 6.
6 are compared by the phase comparator 3. Then, the phase comparison output signal is applied as a control voltage of the voltage controlled oscillator 5 through the loop filter 4 to form a phase locked loop. Therefore, since the phase of the output signal of the voltage controlled oscillator 5 is synchronized with the reference oscillator 1, the frequency division ratio corresponding to the frequency to be set is set in the second variable frequency divider 6 via the control unit 7. Thus, an output signal of a desired frequency can be output from the voltage control generator 5.

When the frequency division ratio corresponding to the frequency to be set is set in the second variable frequency divider 6, the band of the loop filter 4 is temporarily widened, and the first and second variable frequency dividers are set. The frequency division ratios in the devices 2 and 6 are switched to increase the phase comparison frequency in the phase comparator 3 to speed up the phase synchronization pull-in operation. Then, after the pull-in is completed, the band of the loop filter 4 is returned to the original band, and the first band is returned.
By returning the second frequency division ratio to a predetermined value, the phase locked loop characteristic is improved.

[0006]

The conventional frequency synthesizer is configured as described above. In order to speed up the frequency pull-in operation when switching the output frequency, the first and second stages after the reference oscillator 1 are performed. Variable frequency dividers 2 and 6
Is controlled so as to temporarily increase the phase comparison frequency and to expand the band of the loop filter 4. However, the first and second
However, there is a limit to the temporary change of the frequency division number of the variable frequency divider 2 and the expansion of the band of the loop filter 4, so that it is difficult to sufficiently increase the speed.

That is, if the pull-in is performed at a very high frequency first, a considerable difference will remain when the frequency is returned, and high-speed pull-in cannot be performed. In addition, it is inefficient that the output frequency of the reference oscillator 1 is set to a large value and the first frequency divider 2 divides the frequency by a large frequency division ratio in a normal state. Further, since the output frequency of the voltage-controlled oscillator 5, which is the output of the PLL, changes at intervals of the reference frequency, the reference frequency must be lowered in order to finely change the output frequency. In order to maintain the stability of the phase synchronization of the PLL, the time constant of the integrator constituting the loop filter must be increased. As a result, it is necessary until the output frequency of the voltage controlled oscillator 5 becomes stable when the frequency is switched. There is a problem that the time becomes longer, and eventually the responsiveness deteriorates, and it is difficult to speed up the frequency switching.

An object of the present invention is to solve the above-mentioned problems, and to provide a frequency synthesizer capable of greatly increasing the output frequency switching operation and easily obtaining a predetermined frequency.

[0009]

SUMMARY OF THE INVENTION The present invention provides a reference oscillator, a first variable frequency divider for dividing the output of the reference oscillator, a voltage controlled oscillator, and dividing the output of the voltage controlled oscillator. A frequency having a second variable frequency divider, a phase comparator for detecting output phases of the first and second variable frequency dividers, and a loop filter for removing a high-frequency component of the output of the phase comparator In the synthesizer, a first multiplier for multiplying the output of the reference oscillator provided in parallel with a first variable frequency divider for dividing the output of the reference oscillator, an output of the first variable frequency divider, a switching means for switching between the output of the multiplier selectively, a control unit for controlling the pre-Symbol dividing ratio of the first and second variable frequency divider and said switching means, and switches the output frequency Sometimes, the switching is performed by a command from the control unit. Selects the output from the beginning the multiplier by the step, then the frequency division ratio of the first variable frequency divider by sequentially changing with selecting the output from the first variable frequency divider, a phase comparator The comparison frequency input to the oscillator is sequentially switched from a frequency higher than the output frequency of the reference oscillator to a lower frequency.

Further, the present invention provides a reference oscillator, a first variable frequency divider for dividing an output of the reference oscillator, and a first variable frequency divider.
A voltage-controlled oscillator, a second variable frequency divider for dividing the output of a mixer described later, a first phase comparator for detecting output phases of the first and second variable frequency dividers, A first phase-locked loop including a first loop filter that removes a high-frequency component of an output of the phase comparator; a second voltage-controlled oscillator; and a second voltage-controlled oscillator that divides the output of the second voltage-controlled oscillator. 3 variable frequency divider, a second phase comparator for detecting output phases of the reference oscillator and a third variable frequency divider, and a high-frequency component of an output of the second phase comparator is removed. A second loop filter, a second phase-locked loop that obtains an output of a frequency higher than the output of the reference oscillator at the output of the third variable frequency divider, the output of the first voltage-controlled oscillator, and the second A mixer for mixing the output of the second voltage-controlled oscillator and converting the frequency, and the reference oscillator Switching means for switching between an output and an output of the third variable frequency divider and outputting the output to the first variable frequency divider; and a frequency division ratio of the first, second and third variable frequency dividers. And a control unit for controlling the switching unit. When the output frequency is switched, the switching unit first receives the third signal according to a command from the control unit .
The output from the variable frequency divider is selected, and the outputs of the first and third frequency dividers are selected.
The division ratio is sequentially changed, then the reference by said switching means
Wherein selects the output of the oscillator first, the division ratio of the second variable frequency divider is sequentially changed stepwise sequentially lower frequency from a frequency higher than the frequency of the reference frequency frequency comparing a first comparator The configuration is such that the comparison frequency is switched.

Further, the following invention is directed to the second phase locked loop.
Output of a third variable frequency divider in the loop and a second phase ratio
Divides the output of the third variable frequency divider
And a fourth variable frequency divider for supplying to the second phase comparator
Characterized in that it.

Further, the next invention switches the output frequency.
The comparison frequency from low to high
Frequency and the pass band of the loop filter.
It is characterized in that the range can be switched .

[0013]

[0014]

As described above, according to the present invention, when the output frequency is switched, the comparison frequency output from the first and second variable frequency dividers is sequentially switched from a higher frequency to a lower frequency. For this reason, it is possible to perform the step-by-step change at high speed one time at a time, and to realize a high-speed frequency switching operation as a whole.

A first frequency divider for dividing the output of the reference oscillator
A first multiplier for multiplying the output of the reference oscillator is provided in parallel with the variable frequency divider of the above. When switching the output frequency, the comparison frequency input to the phase comparator is stepped from a frequency higher than the output frequency of the reference oscillator. By selectively switching the output of the first variable frequency divider and the output of the multiplier so as to sequentially switch to a lower frequency, the output of the phase comparator can be made very small from the beginning of the switching, The switching operation can be sped up.

According to another aspect of the present invention, an output having a frequency higher than a reference frequency obtained by dividing the output of the voltage controlled oscillator in the second phase locked loop in the two phase locked loops is provided to the first phase locked loop. By using it as a reference signal for the loop, it is possible to further increase the comparison frequency for performing the phase comparison of the first phase locked loop, increase the frequency pull-in operation speed of the phase locked loop, and speed up the output frequency switching operation. it can.

Further, according to the next invention, the fourth variable component
By providing the frequency divider, the frequency of the output of the third variable frequency divider is
Can be high frequency .

Furthermore, by widening appropriately command the bandwidth of the loop filter at the same time position phase comparison stepwise sequentially lower frequency from a higher frequency than the reference frequency from the controller, thereby allowing a more rapid pull-in operation Finally, when the pull-in operation to the set frequency is completed, the band of the loop filter can be set to the optimum value to optimize the loop characteristics.

[0019]

EXAMPLES [Basic Configuration Example will be described an example of the basic configuration of the present invention with reference to FIG. FIG. 1 shows the basic structure of a frequency synthesizer according to the present invention.
It is a block diagram showing an example . In the figure, 11 is a reference oscillator, 12 is a first variable frequency divider for dividing the output of the reference oscillator, 13 is a phase comparator, 14 is a loop filter for removing high-frequency components of the output of the phase comparator 3, Reference numeral 15 denotes a voltage controlled oscillator whose oscillation frequency is controlled according to the output of the loop filter. 16 is a second variable frequency divider,
A part of the output of the voltage controlled oscillator 15 is input and
The frequency is divided and input to the phase comparator 13. Phase comparator 13
Compares the output phases of the first and second variable frequency dividers 12,16. A control unit 17 controls the first variable frequency divider 2 and the second variable frequency divider 6.

Next, the operation of the basic configuration example will be described. The basic operation of pulling in the frequency of the phase-locked loop including the reference oscillator 11, the phase comparator 13, the loop filter 14, the voltage controlled oscillator 15, and the second variable frequency divider 16 is the same as that of the conventional example.

As a procedure for switching the output frequency, first, the frequency division ratio of the first variable frequency divider 12 is set to a low value, for example, 1. At this time, the phase comparison frequency becomes the output frequency of the reference oscillator 11, and the settable frequency of the phase locked loop is an integral multiple of the reference oscillator 11. Therefore, the frequency division ratio of the second variable frequency divider 16 is set by a command from the control unit 17 so that the frequency (f1) becomes the value closest to the set frequency among the frequencies that can be set under this condition.

Next, at the timing when the pull-in to the value f1 close to the set frequency is completed, the frequency division ratio of the first variable frequency divider 12 is set to a value higher than the above-mentioned set value. Then, as described above, the frequency division ratio of the second variable frequency divider 16 is set so as to have a value (f2) closest to the set frequency among the frequencies that can be set at this time.

Further, at the timing when the pull-in to the value f2 closest to the set frequency is completed, the first variable frequency divider 12
Is set to a value higher than the above-mentioned set value, and a value (f3) closest to the set frequency among the settable frequencies at this time.
The frequency division ratio of the second variable frequency divider 16 is set so that

Such a frequency change is sequentially repeated, and finally the frequency division ratio of the first variable frequency divider 12 and the second
Is set to a predetermined value, and the output frequency of the phase period loop is set to the set frequency.

As described above, in the frequency synthesizer of the present basic configuration example , the frequency dividing ratio of the variable frequency divider 12 for dividing the output of the reference oscillator 11 is made variable, and the set frequency is first set with the phase comparison frequency increased. The procedure of performing high-speed pull-in to nearby frequencies, sequentially lowering the phase comparison frequency to a frequency closer to the set frequency, and finally pulling to a predetermined set frequency, as in the conventional example, makes the loop filter 14 The target frequency can be reached in a short time without performing control to expand the band of
Significant speed-up of the pull-in is achieved as compared with the conventional example .

[ First Embodiment] FIG. 2 is a block diagram of a first embodiment of the present invention. In the present embodiment, in addition to the configuration of the basic configuration example shown in FIG. 1, a multiplier 18 for multiplying the output of the reference oscillator 11 and a switch for switching between the outputs of the first variable frequency divider 12 and the multiplier 18 19 is provided to control the frequency division ratio of the first variable frequency divider 12 and the second variable frequency divider 16 in accordance with a command from the control unit 17 and to control switching of the changeover switch 19. Is configured.

The procedure for switching the output frequency is as follows. First, the output of the multiplier 18 is selected by the changeover switch 19, and the phase comparison frequency is set to an integral multiple of the output frequency of the reference oscillator 11. The second variable frequency divider 1 has a value (f1) closest to the set frequency among them.
6 is set.

Next, when the pull-in to the value f1 close to the set frequency is completed, the output of the first variable frequency divider 12 is selected by the changeover switch 19, and the frequency division of the first variable frequency divider 12 is performed. Set the ratio to a small value. Then, as described above, a value (f2) closest to the set frequency among the frequencies that can be set at this time.
The frequency division ratio of the second variable frequency divider 16 is set so that

Further, at the time when the pull-in to the frequency f2 is completed, the frequency division ratio of the first variable frequency divider 12 is set to a value higher than the above-mentioned set value. Then, as described above, a value (f) closest to the set frequency among the settable frequency waves at this time is used.
The frequency division ratio of the second variable frequency divider 16 is set so as to satisfy 3). Such a frequency change is sequentially repeated, and finally the frequency division ratio of the first variable frequency divider 12 and the frequency ratio of the second variable frequency divider 16 are set to predetermined values, and the phase locked loop is controlled. Set the output frequency to the set frequency.

In this embodiment, by using the multiplier 18 for multiplying the output of the reference oscillator 11 and the variable frequency divider 16 together, the phase comparison frequency can be initially higher than the output frequency of the reference oscillator 11, and Since the frequency is sequentially lowered and the frequency is set to the set frequency, a higher-speed pull-in is possible.

[0031] In Example 2 Example 1 has been to perform the retraction of sequentially changing to set the frequency f to a frequency lower phase comparison frequency from a frequency higher than the reference frequency, in the present embodiment, at the same time By controlling the band of the loop filter 14 to be variable by the control unit 7, a high-speed pull-in operation is possible, and the band of the loop filter 14 is set to an optimum value when the pull-in to the set frequency is finally completed. This makes it possible to optimize the loop characteristics.

Third Embodiment FIG. 3 is a block diagram of a third embodiment of the present invention. In the figure, a reference oscillator 11, a first variable frequency divider 12, a first
The configurations of the phase comparator 13, the first loop filter 14, and the first voltage-controlled oscillator 15 are the same as those of the second embodiment, and a second variable frequency divider 16 is added to form a first phase locked loop. Make up. 20 is a second phase comparator, 2
1 is a second loop filter for removing high-frequency components of the output of the phase comparator, 22 is a second voltage-controlled oscillator, and 23 is a third variable component for dividing the output of the second voltage-controlled oscillator 22 A frequency divider 24 for dividing the output of the third variable frequency divider
, And these constitute a second phase-locked loop. The first variable frequency divider 12, the second variable frequency divider 16, and the fourth variable frequency divider 24 are configured so that the control unit 17 can control the frequency division ratio.

Further, 25 is a first voltage controlled oscillator 15
And the output of the second voltage controlled oscillator 22 is mixed to convert the frequency, and the output is input to the second variable frequency divider 16. A changeover switch 26 is provided between the reference oscillator 11 and the first variable frequency divider 12, and outputs the output of the reference oscillator 11 and the third variable frequency as a reference signal of the first phase locked loop. Either of the outputs of the frequency divider 23 can be selected and input by switching with the output signal of the control unit 17.

Next, the operation will be described. In the present embodiment, there are two phase locked loops of a first phase locked loop including a first voltage controlled oscillator 15 and a second phase locked loop including a second voltage controlled oscillator 22. In the phase locked loop, the frequency obtained by subtracting the output of the second voltage controlled oscillator from the output of the first voltage controlled oscillator 15 is taken out as the output from the mixer 25, and the frequency is divided by the second variable frequency divider 16. Input to the first phase comparator 13.

The procedure for switching the output frequency is as follows. First, the output of the third variable frequency divider 23 is selected by the changeover switch 26, and this output is used as the reference frequency. A value close to the set frequency (f
The frequency division ratio of the second variable frequency divider 16 is set so as to satisfy 1). Here, the frequency division ratio of the third variable frequency divider 23 and the fourth variable frequency divider 24 is set so that the output of the third variable frequency divider 23 becomes higher than the output frequency of the reference oscillator 11. Is set.

Next, when the pull-in to the value f1 close to the set frequency is completed, the output of the reference oscillator 11 is selected by the changeover switch 26, and the frequency division ratio of the first variable frequency divider 12 is reduced to a small value. Set. Then, as described above, a value (f2) closest to the set frequency among the frequencies that can be set at this time.
The frequency division ratio of the second variable frequency divider 16 is set so that

Further, at the time when the pull-in to the value f2 close to the set frequency is completed, the frequency division ratio of the first variable frequency divider 12 is set to a value higher than the above-mentioned set value. Then, similarly to the above, the frequency division ratio of the second variable frequency divider 16 is set so as to be a value (f3) closest to the set frequency among the frequencies that can be set at this time.

Such a frequency change is sequentially repeated, and finally the frequency division ratio of the first variable frequency divider 12 and the second
Is set to a predetermined value, and the output frequency of the phase locked loop is set to the set frequency.

In this embodiment, by using the output of the third variable frequency divider 23 in the second phase locked loop as the reference frequency of the first phase locked loop, the phase comparison frequency The frequency can be higher than the output frequency, and a faster pull-in operation is possible.

Fourth Embodiment FIG. 4 is a block diagram showing a fourth embodiment of the present invention.
In the configuration of the present embodiment, the band of the loop filters 14 and 21 can be controlled by the control unit 17 in the configuration of the fourth embodiment.

In the third embodiment, the phase comparison frequency is sequentially changed from a high frequency to a low frequency by using the output of the variable frequency divider of the second phase locked loop as the reference frequency of the first phase locked loop. Although the pull-in to the set frequency is performed, in the present embodiment, at the same time, the band of the loop filter 14 is appropriately expanded to enable a higher-speed pull-in, and finally the pull-in to the set frequency is completed. At this point, the band of the loop filter 14 is set to the optimum value, and the loop characteristics can be optimized.

[0042]

As described above, in the frequency synthesizer according to the present invention, the frequency division ratio of the frequency divider for dividing the output of the reference oscillator is made variable, and the phase comparison frequency is reduced step by step from a higher frequency. By pulling in to the set frequency, the speed of the pull-in operation to the set frequency can be increased.

By using both a multiplier for multiplying the output of the reference oscillator and a variable frequency divider, the phase comparison frequency is gradually lowered from a frequency higher than the reference frequency to a set frequency. The speed of the pull-in operation can be further increased.

[0044] Further, by widening appropriate band of the loop filter and at the same time stepwise sequentially lower the phase comparison frequency from a frequency higher than the reference frequency command from the control unit, while allowing a more rapid pull-in operation, Finally, when the pull-in operation to the set frequency is completed, the band of the loop filter can be set to an optimum value to optimize the loop characteristics.

Further, according to the next invention, by using the output of the variable frequency divider of the second phase locked loop as the reference frequency of the first phase locked loop, the phase comparison frequency can be calculated from the output frequency of the reference oscillator. Higher, to enable a faster pull-in operation, and to gradually lower the phase comparison frequency from a frequency higher than the output frequency of the reference oscillator, and at the same time, to appropriately widen the band of the loop filter to further increase the phase comparison frequency. High-speed pull-in operation is possible.

Further, according to the next invention, the band of the loop filter is set to the optimum value when the pull-in operation to the set frequency is finally completed, so that the loop characteristics can be optimized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a frequency synthesizer according to a basic configuration example of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the frequency synthesizer according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of the frequency synthesizer according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the frequency synthesizer according to the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a conventional frequency synthesizer.

[Explanation of symbols]

11 Reference Oscillator, 12 First Variable Frequency Divider, 13 Phase Comparator, 14 Loop Filter, 15 Voltage Controlled Oscillator, 16 Second Variable Frequency Divider, 17 Controller, 18 Multiplier, 19 Changeover Switch, 20th Switch 2 phase comparators,
21 loop filter, 22 second voltage controlled oscillator,
23 third variable frequency divider, 24 fourth variable frequency divider, 2
5 Mixer, 26 changeover switch.

Claims (4)

(57) [Claims] 1. A reference oscillator and an output of the reference oscillator.
A first variable frequency divider for frequency division, a voltage controlled oscillator,
A second variable frequency divider for dividing the output of the voltage controlled oscillator;
A phase for detecting an output phase of the first and second variable frequency dividers
A comparator and a high-frequency component of the output of the phase comparator are removed.
Frequency synthesizer with loop filter
In parallel with the first variable frequency divider that divides the output of the reference oscillator.
First multiplier for multiplying the output of a reference oscillator provided
The output of the first variable frequency divider and the output of the multiplier
Switching means for selectively switching between,  Frequency division ratios of the first and second variable frequency dividers and the switching
And a control unit for controlling the output means.
By the switching means,
Select output, then select output from first variable divider
And this first variableDividerChange the dividing ratio of
The reference frequency input to the phase comparator.
Lowers gradually from higher frequency than oscillator output frequency
Frequency synthesizer characterized by switching to a new frequency
Isa. 2. A reference oscillator, a first variable frequency divider for dividing an output of the reference oscillator, a first voltage controlled oscillator, and a second variable frequency divider for dividing an output of a mixer described later. A first phase comparator for detecting output phases of the first and second variable frequency dividers, and a first loop filter for removing a high-frequency component of the output of the phase comparator. A third phase-locked loop, a second voltage-controlled oscillator, a third variable frequency divider for dividing the output of the second voltage-controlled oscillator, and the reference oscillator and a third variable frequency divider. A second phase filter for detecting an output phase; and a second loop filter for removing a high-frequency component of the output of the second phase comparator. A second phase-locked loop for obtaining an output having a higher frequency than the output of the first voltage-controlled oscillator. A mixer for mixing the output of the second voltage-controlled oscillator to perform frequency conversion, and switching between the output of the reference oscillator and the output of the third variable frequency divider to output to the first variable frequency divider A switching unit; and a control unit for controlling the frequency division ratios of the first, second, and third variable frequency dividers and the switching unit. When the output frequency is switched, a command from the control unit is issued. First, the switching means first sets the third possible state.
Select the output from the variable frequency divider and divide the first and third frequency dividers
The ratio is sequentially changed, and then the reference oscillation is performed by the switching means.
The frequency of the first and second variable frequency dividers is sequentially changed, and the frequency to be compared by the first comparator is gradually lowered from the frequency higher than the frequency of the reference frequency. A frequency synthesizer configured to switch the comparison frequency. 3. A third phase locked loop according to claim 2, wherein
Between the output of the variable frequency divider and the second phase comparator
And divides the output of the third variable frequency divider to produce a second phase ratio
Having a fourth variable frequency divider for supplying to the comparator
The frequency synthesizer according to claim 2. 4. When the output frequency is switched, a comparison frequency is used.
The number is switched step by step from a higher frequency to a lower frequency
And switchable pass band of loop filter
Any one of claims 1-3 characterized by comprising
The frequency synthesizer according to 1.