JP3194404U - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device which can be manufactured at low cost and can obtain a trench gate type switching element (power MOSFET, IGBT) with reduced feedback capacitance. On the bottom surface of a groove, a bottom electrode is formed between the left and right gate electrodes to be separated (insulated) from the left and right gate electrodes. Since the interlayer insulating layer 30 is locally left on both sides of the groove 25, the central portion of the groove 25 has a large concave shape on the lower side and a convex shape on the upper side on both sides of the groove 25. For this reason, the unevenness of the base on which the emitter electrode 72 is formed becomes severe, and this unevenness is reflected on the surface of the emitter electrode 72, and many fine unevennesses are formed. [Selection] Figure 6

Description

  The present invention relates to a structure of a trench gate type semiconductor device that performs a switching operation.

As a switching element (power semiconductor element) that performs a switching operation of a large current, a power MOSFET or an insulated gate bipolar transistor (Insulated Gate)
Bipolar Transistor (IGBT) etc. are used. In such a switching element, a trench gate type in which an oxide film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is used.

FIG. 9 is a cross-sectional view showing an example of the configuration of such a trench gate type power MOSFET (semiconductor device 110). In FIG. 9, in the semiconductor substrate 80, an n ⁻ layer 82 and a p ⁻ layer 83 are sequentially formed on an n ⁺ layer 81 serving as a drain layer. Semiconductor substrate 8
On the surface side of 0, a groove (trench) 85 penetrating the p ⁻ layer 83 is formed. A plurality of grooves 85 (four in the illustrated range) are formed in parallel to extend in the direction perpendicular to the paper surface in FIG. An oxide film 86 is uniformly formed on the inner surface of each groove 85, and then the gate electrode 87.
Is formed so as to fill the groove 85.

Further, on the surface side of the semiconductor substrate 80, n ⁺ layers 88 serving as source regions are formed on both sides of the groove 85. A source electrode (first main electrode) 89 is formed on the surface of the semiconductor substrate 80. On the other hand, a drain electrode (second main electrode) 90 is formed on the entire back surface of the semiconductor substrate 80 in contact with the n ⁺ layer (drain layer) 81. On the other hand, since the interlayer insulating layer 91 is formed so as to cover the groove 85 on the surface side of the semiconductor substrate 80, the source electrode 8.
9 contacts both the n ⁺ layer 88 and the p ⁻ layer 83 and is insulated from the gate electrode 87. On the surface side outside the range shown in FIG. 9, for example, all the gate electrodes 87 are connected on the end side in the extending direction (perpendicular to the paper surface) of the groove 85 and are connected to a common gate wiring. Further, the source electrode 89 is formed on the entire surface within the range shown in FIG. 9, but on the surface side, the gate wiring and the source electrode 89 are formed separately. For this reason, each trench 85 has a gate wiring (
A channel is formed in the p ⁻ layer 83 on the side surface of the trench 85 by the voltage applied to the gate electrode 87), and operates as an n-type MOSFET between the n ⁻ layer 82 and the n ⁺ layer 88.
SFET is turned on. That is, the switching of current between the source electrode (first main electrode) 89 and the drain electrode (second main electrode) 90 can be controlled by the voltage applied to the gate electrode 87. Since the MOSFETs formed for each groove 85 are all connected in parallel, a large current can flow between the source electrode 89 and the drain electrode 90.

Although FIG. 9 shows the structure of the power MOSFET, the same structure can be applied to the IGBT. In this case, for example, the n ⁺ layer 81 can be replaced with a p ⁺ layer (collector layer), the source electrode 89 can be replaced with an emitter electrode, and the drain electrode 90 can be replaced with a collector electrode.

In order to operate the power MOSFET at high speed, the feedback capacitor Crss and the input capacitor Cis
It is necessary to reduce s. In the structure of FIG. 9, the feedback capacitance Crss is the gate electrode 8.
7 and the capacitance between the drain electrode 90 and the input capacitance Ciss is the sum of the capacitance between the gate electrode 87 and the source electrode 89 and the feedback capacitance Crss. Here, in the structure of FIG. 9, since there is a capacitance through the oxide film 86 at the bottom of the trench 85, it is difficult to reduce the capacitance Crss between the gate electrode 87 and the drain electrode 90. Although it is clear that Crss can be reduced by increasing the thickness of the oxide film 86, MOSFE other than the operating speed is obtained.
Since the characteristic of T greatly depends on the thickness of the oxide film 86, the thickness of the oxide film 86 is usually set so that a desired characteristic can be obtained except for the operation speed. For this reason, unlike the interlayer insulating layer 91, the oxide film 86 is thinly formed by thermal oxidation with particularly good interface characteristics with the semiconductor layer (p ⁻ layer 83, etc.). In this case, it is difficult to reduce Crss.

In order to solve such a problem, Patent Document 1 describes a structure in which the oxide film 86 is particularly thick only at the bottom of the groove 85. Further, in Patent Document 2, a first semiconductor layer and a first oxide film having the same configuration as the gate electrode 87 and the oxide film 86 are provided at the bottom of the trench 85, and the gate electrode 87 and the oxide film described above are provided thereon. A configuration in which 86 is formed is described.

According to these structures, the feedback capacitance Crss can be reduced. On the other hand, in these structures, since the oxide film 86 on the p ⁻ layer 83 (side surface) on the side surface of the trench 85, which is a portion where the channel is formed in the MOSFET, is thinned, the power with good characteristics is also obtained except for the operation speed. A MOSFET can be obtained.

JP 2003-158268 A JP 2006-93506 A

However, in the technique described in Patent Document 1, since the oxidation proceeds uniformly in the thermal oxidation process, it is not possible to form a thick oxide film locally only on the bottom surface of the groove while keeping the oxide film on the side surface of the groove thin. It is actually difficult. For this reason, in order to form a locally thick oxide film,
For example, it is necessary to perform etching for locally leaving the formed oxide film and then perform thermal oxidation again, or to repeat such a process a plurality of times, which complicates the manufacturing process.

In the technique disclosed in Patent Document 2, the structure having the well-known trench gate structure on the first semiconductor layer and the first oxide film provided at the bottom of the groove has a step for forming the structure in the groove. It was necessary separately and the manufacturing process was complicated.

Thus, since the manufacturing process becomes complicated, it is difficult to manufacture the semiconductor devices described in Patent Documents 1 and 2 at low cost. That is, it has been difficult to inexpensively manufacture a trench gate type switching element (power MOSFET, IGBT) having a reduced feedback capacitance Crss.

  The present invention has been made in view of such problems, and an object thereof is to provide a device for solving the above problems.

In order to solve the above problems, the present invention has the following configuration.
In the semiconductor device of the present invention, a groove is formed on the surface side of the semiconductor substrate, a gate electrode is provided in contact with the oxide film formed on the inner surface of the groove, and a first main body formed on the surface side of the semiconductor substrate is provided. The operation current flowing between the electrode and the second main electrode formed on the back surface side of the semiconductor substrate is switched by a voltage applied to the gate electrode, and includes a plurality of the grooves provided with the gate electrode. In the semiconductor device, the gate electrode is divided and formed on both side surfaces of the groove inside the groove, and the first main electrode is an interlayer insulation formed on the gate electrode. A plurality of trenches are formed through a layer, and are separated from the gate electrode and electrically connected to the first main electrode on a portion of the oxide film where the gate electrode is not formed on the bottom surface of the trench. Is equipped with a bottom electrode, a bonding pad to which the bonding wires are connected, characterized in that it is formed in a plurality of said grooves are formed region on the first main electrode.
The semiconductor device of the present invention is characterized in that the width of the groove is larger than the depth of the groove.
In the semiconductor device of the present invention, a recess is formed on the surface of the first main electrode in the central portion of the groove in plan view and in the portion between the two adjacent grooves in plan view. Features.
In the semiconductor device according to the present invention, the concave portion in the central portion of the groove in plan view is formed deeper than the concave portion in a portion between two adjacent grooves in plan view.

Since the present invention is configured as described above, it can be manufactured at low cost, and a trench gate type switching element (power MOSFET, IGBT) with reduced feedback capacitance can be obtained.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing (continuation) which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 1A is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. It is a figure which shows the structure in the groove | channel in the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the form at the time of performing wire bonding in the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the form at the time of performing wire bonding in the conventional semiconductor device. It is sectional drawing which shows especially the structure of the surface shape of the semiconductor device which concerns on embodiment of this invention in detail. It is sectional drawing which shows the structure of the conventional trench gate type semiconductor device.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is a trench gate type power MOSFET in which on / off of a channel is controlled by a gate voltage and current switching is controlled. The gate electrode is formed in a plurality of grooves (trench) formed in parallel to the surface of the semiconductor substrate, and the gate electrodes are connected in parallel. Each gate electrode is formed inside the trench after an oxide film is formed on the surface in the trench.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device (power MOSFET) 10. The semiconductor device 10 is a trench gate type element having a configuration in which a gate electrode is formed in a groove (trench) formed in a semiconductor substrate 20. In FIG. 1, this semiconductor substrate 2
In 0, an n ⁻ layer 22 and a p ⁻ layer 23 are sequentially formed on an n ⁺ layer 21 serving as a drain layer. On the surface side of the semiconductor substrate 20, a groove (trench) 25 penetrating the p ⁻ layer 23 is formed. A plurality of grooves 25 (two in FIG. 1) are formed in parallel to extend in the direction perpendicular to the paper surface in FIG. An oxide film 26 is uniformly formed on the inner surface (side surface and bottom surface) of the groove 25. However, like the technique described in Patent Document 1, the oxide film 26 is thin on the side surface,
It may be thick at the bottom.

On the surface side of the semiconductor substrate 20, n ⁺ layers 27 are formed on both sides of the groove 25.
A drain electrode (second main electrode) 40 electrically connected to the n ⁺ layer (drain layer) 21 is formed on the entire back surface of the semiconductor substrate 20.

The oxide film 26 is removed on the surface of the semiconductor substrate 20 away from the trench 25. FIG. 1 shows a structure in which two grooves 25 are arranged. Hereinafter, a structure corresponding to a single groove 25 will be described. In this semiconductor device 10, the structure in the groove 25 is particularly shown in FIG.
This is different from the semiconductor device 110 shown in FIG.

First, the gate electrodes 28 are respectively provided along the p ⁻ layers 23 on the left and right side wall portions of the trench 25, and are formed separately on the left and right at the bottom surface of the trench 25. However, each of the left and right gate electrodes 28 is connected outside the illustrated range (for example, the end in the longitudinal direction of the groove 25). The gate electrode 28 is made of, for example, conductive polycrystalline silicon doped at a high concentration.

On the other hand, on the bottom surface of the groove 25, as viewed from above, the bottom electrode separated (insulated) from the left and right gate electrodes 28 between the left and right gate electrodes 28 as shown in FIG. 29 is formed. Since the oxide film 26 is also formed on the bottom surface of the groove 25, the bottom electrode 29 is also insulated from the n ⁻ layer 22 below it. In this state, an interlayer insulating layer 30 is formed in the trench 25 so as to cover the left and right gate electrodes 28 and to separate the bottom electrode 29 and the gate electrodes 28 on both sides thereof.

In this state, a source electrode (first main electrode) 35 is formed so as to cover the surface of the semiconductor substrate 20. With the above configuration, the source electrode 35 is connected to the p ⁻ layer 23 and the n ⁺ layer 27 on the surface of the semiconductor substrate 20 as in the semiconductor device 80 having the configuration of FIG. The bottom electrode 29 on the bottom surface of the groove 25 is also connected by the through hole. The source electrode 35 and the gate electrode 28 are insulated by the interlayer insulating layer 30.

As with the semiconductor device 110 of FIG.
Are connected to a common gate wiring at the end in the extending direction. The gate wiring and the source electrode 35 are separated. Therefore, the potentials of the source electrode (first main electrode) 35, the drain electrode (second main electrode) 40, and the gate wiring (gate electrode 28) are controlled, and the source electrode 35, Switching of current between the drain electrodes 40 can be controlled.

In this structure, the gate electrode 28 is not formed on the bottom surface side of the groove 25 but is divided on both sides, so that the capacitance Crss between the gate electrode 28 and the drain electrode 40 is reduced. Furthermore, since the bottom electrode 29 is set to the same potential (ground potential) as the source electrode 35, the capacitance Crss (feedback capacitance) between the gate electrode 28 and the drain electrode 40 is reduced.

Further, in a general trench gate type device, when the width of the groove 25 is wide (for example, when the width is 1 to 20 μm), the depletion layer on the bottom side of the groove 25 is difficult to expand. In many cases, the breakdown voltage of the entire device is lowered at this portion. On the other hand, the groove 2 is formed by providing the bottom electrode 29 between the left and right gate electrodes 28 as described above.
Even when the width of the groove 5 is wide, the depletion layer on the bottom side of the groove 25 spreads favorably, so that the breakdown voltage can be improved. In the case of an IGBT having the above structure, holes are accumulated at the bottom of the groove, particularly in the case of a wide groove of 1 to 20 μm, more preferably 3 to 15 μm. Is particularly preferable.

In the structure of FIG. 1, since the oxide film 26 is uniformly formed inside the groove 25, the oxide film 26 can be formed by a single thermal oxidation process. Also, the gate electrode 28 and the bottom electrode 29 can be formed simultaneously by patterning the same polycrystalline silicon layer.

Below, this manufacturing method is demonstrated concretely. 2 (a)-(h), FIG. 3 (i)-
FIG. 4N is a process cross-sectional view illustrating the manufacturing process of the semiconductor device 10. Here, only the structure related to one groove 25 is shown.

First, as shown in FIG. 2A, the surface (where the groove 25 is to be formed in the semiconductor substrate 20 in which the n ⁻ layer 22 and the p ⁻ layer 23 are sequentially formed on the n ⁺ layer 21 ( In the p ⁻ layer 23), an n ⁺ layer 27 having a width wider than that of the trench 25 is formed by ion implantation.

Next, as shown in FIG. 2B, a groove 25 is formed in the region where the n ⁺ layer 27 is formed (groove forming step). The groove 25 can be formed, for example, by dry etching the semiconductor substrate 20 using a photoresist as a mask. The trench 25 has a depth that penetrates the p ⁻ layer 23 and reaches the n ⁻ layer 22.

Next, the structure of FIG. 2B is thermally oxidized to form an oxide film 26 on the entire surface of the semiconductor substrate 20 including the inside of the trench 25 (oxidation step). Thereafter, the oxide film 26 in the region away from the trench 25 is removed by etching. As a result, as shown in FIG. 2C, the oxide film 26 remains only in and around the trench 25 (bottom surface, side surface). Here, the oxide film 2
When the thickness 6 is uniform in the groove 25, the oxide film 26 can be formed by one thermal oxidation.

Next, a polycrystalline silicon (gate electrode material) 50 doped with a high concentration so as to have conductivity is formed on the entire surface by a CVD method (gate electrode formation step). At this time, FIG.
As shown in d), the polycrystalline silicon is formed under such film forming conditions that the inside of the trench 25 is not filled with the polycrystalline silicon 50 and the thickness of the polycrystalline silicon 50 is substantially uniformly covered on the side and bottom surfaces of the trench 25. 50 films are formed.

Next, the deposited polycrystalline silicon 50 is patterned (gate electrode patterning step). 2E to 2H are diagrams for explaining this process in detail. First, FIG. 2 (e)
As shown in FIG. 2, after the photoresist layer 100 is applied and formed on the entire surface, exposure and development using a mask are performed, and the photoresist layer 100 is patterned as shown in FIG. Here, it is generally not easy to expose and develop the photoresist layer 100 including the step portion and pattern it with high accuracy through the top and bottom of the step because of the limitation of the depth of focus at the time of exposure. Absent. However, as shown in the figure, since the patterning is performed only inside the groove 25, the patterning shown in FIG. 2F is performed by focusing the bottom surface of the groove 25 at the time of exposure. It can be done easily.

Thereafter, as shown in FIG. 2G, the polycrystalline silicon 50 is dry-etched (anisotropic etching) to selectively remove the polycrystalline silicon 50 particularly in the trench 25, and the gate electrode 28 is removed. And the bottom electrode 29 are formed separately. Thereafter, as shown in FIG. 2H, the photoresist layer 100 is removed. As a result, the gate electrode 2 in FIG.
8. A bottom electrode 29 is formed. Note that the polycrystalline silicon 50 is patterned so that a part of the polycrystalline silicon 50 remains as a wiring material even outside the illustrated range (for example, the end side in the extending direction of the groove 25).

Thereafter, as shown in FIG. 3I, an insulating layer (SiO ₂ ) 60 is formed on the entire surface by CVD (interlayer insulating layer forming step). At this time, like the polycrystalline silicon 50, the groove 2
An insulating layer 60 is formed inside 5.

Next, the formed insulating layer 60 is patterned (interlayer insulating layer patterning step).
. FIGS. 3J to 3M are diagrams for explaining this process in detail. First, as shown in FIG. 3J, a photoresist layer 100 is applied and formed in the same manner as in FIG. After that, FIG.
As shown in (k), the photoresist layer 100 is similarly patterned so that the insulating layer 60 is exposed on the outside of the groove 25 and on the bottom electrode 29 in the groove 25. Also in the pattern in this case, since the portion with the small processing line width is inside the groove 25, this patterning can be easily performed by adjusting the focal point at the time of exposure to the bottom surface of the groove 25.

Thereafter, by performing dry etching of the insulating layer 60, the insulating layer 60 remains as the interlayer insulating layer 30 as shown in FIG. Thereafter, the photoresist 100 is removed as shown in FIG.

Thereafter, as shown in FIG. 3 (n), the source electrode 35 is formed on the front surface and the drain electrode 4 is formed on the back surface.
By forming 0 (electrode forming step), the semiconductor device 10 of FIG. 1 is manufactured. In addition,
In the region shown in FIG. 3 (n), the source electrode 35 is formed on the entire surface, but actually, unlike the drain electrode 40, the source electrode 35 is not formed on the entire surface of the semiconductor device 10. . Actually, the groove 25 extends in a direction perpendicular to the paper surface in FIGS. 2 and 3, and the gate electrode 28 is patterned so as to be drawn out on the surface side so as not to contact the source electrode 35 at the end. Thereby, each of the gate electrode 28, the source electrode 35, and the drain electrode 40 functions as an electrode terminal.

In the configuration of FIG. 1, since the source electrode 35 and the bottom electrode 29 are in direct contact, the bottom electrode 29 has the same potential as the source electrode 35. Here, the bottom electrode 29 is actually the groove 25.
However, the bottom electrode 29 itself does not serve as a current path. For this reason, the source electrode 35 and the elongated bottom electrode 29 do not need to be in uniform contact with each other in the extending direction of the groove 25, and these contact portions can be set as appropriate.

FIG. 4A shows a plan view of the configuration in such a case as viewed from above. Here, the description of the source electrode 35 and the interlayer insulating layer 30 is omitted, and the opening 301 of the interlayer insulating layer 30 on the bottom electrode 29 is described. 4A is a cross-sectional view in the AA direction in FIG. 4A, and FIG. 4C is a cross-sectional view in the BB direction. In this example, the openings 301 (that is, where the source electrode 35 and the bottom electrode 29 are connected) are arranged in a staggered arrangement. However, for example, the openings 301 are not provided in the central portion of the chip, but only at the ends of the chip. An opening 301 may be provided. Such setting can be performed by the mask pattern in the interlayer insulating layer patterning step (FIG. 3K). The shape of the interlayer insulating layer 30 (insulating layer 60) can be appropriately set as long as the gate electrode 28 and the bottom electrode 29 can be insulated.

Next, the positional relationship between the gate electrode 28 and the bottom electrode 29 will be described. In the configuration of FIG. 1, the positional relationship between the gate electrode 28 and the bottom electrode 29 on the bottom surface of the trench 25 affects the characteristics of the semiconductor device 10. FIG. 5 is an enlarged view of the internal structure of the groove 25, where the distance between the gate electrode 28 and the bottom electrode 29 is D, and the amount of protrusion of the gate electrode 28 toward the bottom electrode 29 in the groove 25 is X.

For example, when the distance D is increased, the width of the depletion layer formed immediately below the gate electrode 28 is narrowed on the bottom electrode 29 side, and the breakdown voltage between the source electrode 35 and the drain electrode 40 is reduced. For this reason,
This breakdown voltage can be controlled by the distance D between the gate electrode 28 and the bottom electrode 29.

Further, if the protrusion amount X of the gate electrode 28 is large, the feedback capacitance Crss becomes large.
For this reason, Crss can be adjusted by the protrusion amount X.

According to the above structure and manufacturing method, D and X are both determined by the pattern (lithographic mask pattern) of the photoresist layer 100 in the gate electrode patterning step (FIG. 2F). For example, in general, in a power MOSFET, when a breakdown occurs between the source electrode 35 and the drain electrode 40 in order to protect the element, this portion is determined to occur in a specific region on the chip. In this case, it is possible to easily reduce the breakdown voltage of the active region (cell region) on the chip by using a mask pattern in which D is widened at this specific location. On the other hand, by reducing D, Crss can also be reduced. That is, the withstand voltage and Crss distribution in the surface of the chip can be controlled only by the lithography mask pattern in the gate electrode patterning step. In the lithography shown in FIG. 2 (f), D and X can be controlled with high accuracy by focusing on the bottom surface of the groove 25 at the time of exposure. On the other hand, when the same control is performed in the structure described in Patent Document 1, it is necessary to change the thickness of the oxide film in the chip, which further complicates the manufacturing process.

Note that the cross-sectional shape of the bottom electrode 29 (the etching shape of the polycrystalline silicon 50 in FIG. 2G can be controlled by dry etching conditions. As a result, for example, the bottom electrode 29 has a forward taper shape (a shape that expands downward). In this case, the interlayer insulating layer 30 is formed on the gate electrode 28.
And the bottom electrode 29 are easily embedded, and the insulation between them can be improved. Conversely, when the bottom electrode 29 has a reverse taper shape (a shape that widens upward), the contact area between the source electrode 35 and the bottom electrode 29 can be increased, and the contact resistance between them can be reduced. can do.

As described above, there is a portion where the polycrystalline silicon (gate electrode material) 50 remains as a wiring outside the trench 25 (the surface of the semiconductor substrate 20), but this wiring pattern is thicker than D and X. Therefore, even when the focus at the time of exposure is adjusted to the bottom surface of the groove 25, patterning of the wiring pattern is easy. That is, even when D and X are controlled with high accuracy as described above, patterning of the polycrystalline silicon (gate electrode material) 50 in the semiconductor device 10 can be easily performed. In the interlayer insulating layer patterning step, there are actually places where the insulating layer 60 remains in places other than the grooves 25. The pattern in this place is compared with the pattern in the groove 25 (opening 301). Since it is thick, the patterning is similarly easy.

As described above, the semiconductor device 10 can be manufactured by a simple manufacturing process, and the characteristics can be controlled by the mask pattern at the time of lithography.

In order to form the above structure in the groove 25, in the semiconductor device 10 described above, the width of the groove 25 is preferably wide. For this reason, it is preferable to make the width of the groove 25 larger than its depth.

In the above example, the bottom electrode 29 is formed between the gate electrodes 28 formed by being divided on both side surfaces in the groove 25. However, even when the bottom electrode 29 is not formed, the feedback capacitance Crss.
It is clear that is reduced. Even in such a case, a manufacturing method similar to the above can be applied except that the lithography mask pattern in the gate electrode patterning step is changed.

As described above, in this semiconductor device 10, due to the structure related to the single groove 25,
There is an effect that Crss can be reduced. In actual semiconductor devices,
Similar to the structure of FIG. 9, a plurality of the structures of FIG. 1 are formed in parallel. In the structure of FIG.
Thus, when a plurality of such structures are formed in parallel, the reliability can be particularly improved. This will be described below.

In an actual semiconductor device (IGBT or the like), a plurality of the structures in FIG. 1 are formed in parallel, and wirings outside the chip are connected thereon. FIG. 6A is a cross-sectional view of a semiconductor device (IGBT) 120 having four structures similar to those in FIG. 1 in parallel. Here, instead of the n ⁺ layer 21 in the semiconductor device (power MOSFET) of FIG. 1, a semiconductor substrate 70 provided with a p ⁺ layer 71 serving as a collector layer is used. The source electrode 35 on the front surface is an emitter electrode (first main electrode) 72, and the drain electrode 40 on the back surface is a collector electrode (second main electrode) 73. When the semiconductor device 120 is mounted, the chip on which the semiconductor device 120 is formed is bonded to a lead frame or a substrate, and the collector electrode 73 is electrically connected to the lead frame or the substrate on the back side of the chip. Is done. On the other hand, the emitter electrode 72 is electrically connected on the surface side of the chip. Therefore, as shown in FIG. 6A, a bonding pad 74 made of a metal material is partially formed on the emitter electrode 72. As shown in FIG. 6B, one end of a wire-like bonding wire 75 is bonded to the bonding pad 74 at the time of mounting. The other end of the bonding wire 75 is connected to a terminal outside the chip.

One end of the bonding wire 75 is crimped with an ultrasonic wave applied,
Bonded to the bonding pad 74. The bonding pad 74 is made of a thick metal (such as Al) so as not to adversely affect the semiconductor substrate 20 immediately below the bonding pad 74 during this bonding.
The bonding wire 75 is composed of a thin Al or Au wire. For this reason,
In order to increase the reliability of the semiconductor device 120, the bonding pad 74 and the emitter electrode 7 are used.
2. It is necessary that peeling does not easily occur between the bonding pad 74 and the bonding wire 75.

Here, in this semiconductor device 120, the cross-sectional shape before forming the emitter electrode 72 is the same as the shape shown in FIG. Here, since the interlayer insulating layer 30 is locally left on both sides of the groove 25, the central portion of the groove 25 has a large concave shape on the lower side and a convex shape on the upper side on both sides of the groove 25. . For this reason, the unevenness of the base on which the emitter electrode 72 is formed becomes severe, and this unevenness is reflected on the surface of the emitter electrode 72, and many fine unevennesses are formed. Due to the unevenness, the bonding pad 74 is pinned to the emitter electrode 72. Similarly, unevenness reflecting the unevenness of the emitter electrode 72 is formed on the surface of the bonding pad 74, and this unevenness also has an effect of pinning the bonding wire 75 to the bonding pad 74.

In contrast, a bonding pad 74 is formed on the conventional structure shown in FIG.
FIG. 7 shows a cross-sectional view when the bonding wire 75 is connected thereon. In this structure, since the gate electrode 87 is formed so as to fill the groove 85, only the unevenness due to the interlayer insulating layer 91 exists on the base of the source electrode 89 (corresponding to the emitter electrode 72). For this reason, compared with the structure of FIG. 6, the interval of the unevenness | corrugation in a horizontal direction is long, the density of an unevenness | corrugation becomes small, and the depth of an unevenness | corrugation becomes shallow, and the said pinning effect becomes small. For this reason, the bonding pads 74 and the bonding wires 75 are easily peeled off.

That is, high reliability is obtained in the bonding of the bonding wires 75 and the like of the semiconductor device 120 shown in FIG.

A detailed cross-sectional shape of the emitter electrode 72 in this structure is shown in FIG. Emitter electrode 72
Since the unevenness is determined by the surface shape of the base immediately before the emitter electrode 72 is formed, the concave portion is largely concave at the center portion of the groove 25 and convex upward at both sides of the groove 25. For this reason, the emitter electrode 72 is depressed downward in the middle portion of the adjacent groove 25 and largely depressed downward in the central portion of the groove 25. The height of the emitter electrode 72 is highest on both sides of the groove 25 where the interlayer insulating layer 30 remains. In FIG. In the central part of 25 is shown as b. In this semiconductor device 120, a recess having a recess amount a and a recess having a recess amount b are formed together, whereas in the conventional structure of FIG. 7, a recess having a small recess amount (the recess amount in FIG. only the concave part a) is formed. That is, in the structure of FIG. 8, the number of the concave portions can be increased and deepened.

Further, the thermal expansion coefficients of silicon constituting the semiconductor substrate 70 and the main component (for example, aluminum) of the metal material constituting the emitter electrode 72 formed in a wide area on the surface thereof are greatly different. Therefore, in the structure of FIG. 6, warpage or stress due to the difference in the thermal expansion coefficient occurs in the state of the wafer before the division for each chip or the state of the chip after the division when the semiconductor device 120 is manufactured. To do. If the wafer warps during the manufacturing process, it may be difficult to fix the wafer by suction in the manufacturing equipment. If warpage or stress occurs when the product is divided into chips and used as a product, This causes problems such as chip peeling from the lead frame and deterioration of characteristics.

On the other hand, in the semiconductor device 120 described above, b> a in FIG.
A particularly deep groove is formed in the emitter electrode 72 in the central portion of 5. The emitter electrode 72 made of a metal material is easily deformed (stretched) in the horizontal direction by the groove. For this reason, the emitter electrode 72 easily expands and contracts in accordance with the thermal expansion of the semiconductor substrate 70 during thermal expansion, and the generation of the warp and stress is alleviated.

That is, in the semiconductor device 120 having a plurality of the structures shown in FIG. 1, warpage and stress generated in the wafer or chip can be suppressed, and high reliability can be obtained.

In the above configuration, it is clear that the same effect can be obtained even if the conductivity type (p-type, n-type) is reversed. It is obvious that the above-described structure and manufacturing method can be realized regardless of the material constituting the semiconductor substrate, the gate electrode, and the like, and the same effect can be obtained.

  Moreover, the resin sealing body which coat | covers this is formed in said semiconductor device by well-known transfer mold molding. At this time, it is desirable to perform transfer molding so that the resin for forming the resin sealing body flows in a direction in which a plurality of irregularities formed on the surface of the bonding pad 74 extends. By doing in this way, the inside of the unevenness | corrugation formed in the surface of the bonding pad 74 can be favorably filled with resin, and it can suppress that a void generate | occur | produces in a resin sealing body.

  In FIG. 6A, the bonding wire 75 connected between the emitter electrode 72 and the terminal outside the chip has a plurality of irregularities formed on the surface of the bonding pad 74 in the direction in which the bonding wire 75 extends. It is desirable to connect so as to be parallel to the direction in which the film extends. By doing so, when transfer molding is performed so that the resin flows in the direction in which the unevenness extends, the bonding wire 75 is unlikely to be flown by the resin, and the bonding wire 75 is disconnected or the bonding pad 74 and the bonding wire are Peeling is less likely to occur between 75 and 75.

10, 110 Semiconductor device (power MOSFET)
20, 70, 80 Semiconductor substrate 21, 27, 81, 88 n ⁺ layer 22, 82 n ⁻ layer 23, 83 p ⁻ layer 25, 85 groove (trench)
26, 86 Oxide film 28, 87 Gate electrode 29 Bottom electrode 30, 91 Interlayer insulating layers 35, 89 Source electrode (first main electrode)
40, 90 Drain electrode (second main electrode)
50 Polycrystalline silicon (Gate electrode material)
60 Insulating layer (SiO ₂ )
71 p ⁺ layer 72 emitter electrode (first main electrode)
73 Collector electrode (second main electrode)
74 Bonding pad 75 Bonding wire 100 Photoresist layer 120 Semiconductor device (IGBT)
301 opening

Claims (8)

A groove is formed on the front surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, a first main electrode formed on the front surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A semiconductor device comprising a plurality of the grooves provided with the gate electrode, wherein an operating current flowing between the second main electrode formed on the side is switched by a voltage applied to the gate electrode;
The gate electrode is divided and formed on both side surfaces of the groove inside the groove, and the first main electrode is formed with a plurality of the interlayer insulating layers formed on the gate electrode. Formed over the groove,
A bottom electrode separated from the gate electrode and electrically connected to the first main electrode on the oxide film in a portion where the gate electrode is not formed at the bottom of the groove;
A semiconductor device, wherein a bonding pad to which a bonding wire is connected is formed on the first main electrode in a region where a plurality of the grooves are formed.   The semiconductor device according to claim 1, wherein a width of the groove is larger than a depth of the groove.   The concave portion is formed on the surface of the first main electrode in a central portion of the groove in a plan view and a portion between two adjacent grooves in a plan view. 2. The semiconductor device according to 2.   4. The semiconductor device according to claim 3, wherein the recess in the central portion of the groove in plan view is formed deeper than the recess in a portion between two adjacent grooves in plan view. A groove is formed on the front surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, a first main electrode formed on the front surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A semiconductor device comprising a plurality of the grooves provided with the gate electrode, wherein an operating current flowing between the second main electrode formed on the side is switched by a voltage applied to the gate electrode;
The first main electrode is formed to cover the plurality of grooves through an interlayer insulating layer formed on the gate electrode, and the surface of the first main electrode is on the surface side of the semiconductor substrate. A semiconductor device comprising a groove facing the groove formed in the semiconductor device. A groove is formed on the front surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, a first main electrode formed on the front surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A semiconductor device comprising a plurality of the grooves provided with the gate electrode, wherein an operating current flowing between the second main electrode formed on the side is switched by a voltage applied to the gate electrode; A bonding pad to which a bonding wire is connected is formed on the first main electrode in a region where a plurality of the grooves are formed, and a groove is provided on the surface of the bonding pad. Semiconductor device.   A plurality of the grooves are formed in parallel on the surface of the semiconductor substrate, and the width of the groove in plan view is larger than the width of the semiconductor substrate between two adjacent grooves in plan view. The semiconductor device according to claim 5 or 6. The semiconductor device according to claim 5, wherein a width of the groove is larger than a depth of the groove.