JP3193098B2 - Image processing apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method, for example, an image processing apparatus and method for adding predetermined information to an image.

[0002]

2. Description of the Related Art In recent years, as the performance of color copiers and color printers has been improved, there has been a risk of forgery of originals (hereinafter referred to as "specific originals") for which copying using these is prohibited. In order to prevent such illegal copying, an attempt has been made to prevent illegal copying by registering an image pattern of a specific document in a color copying machine, a color printer, or the like, and identifying the specific document by image recognition.

[0003] Conventionally, it has been difficult to identify the device used for the illegal copy or the person who made the illegal copy from the illegally copied matter. Therefore, a technique of adding information or the like that can specify a copying machine or a copying person to a copied image is being studied. For example, among the output color components of the copying machine (for example, YMCK), the image signal of the color (for example, Y) component which is most difficult for the human eyes to recognize is subjected to modulation for adding a constant value, and the serial number of the copying machine, etc. This is a technique for adding a pattern representing.

[0004]

However, the above-described conventional example has the following problems. That is, the image patterns that can be registered are limited, and it is practically impossible to register the image patterns of all the specific originals. On the other hand, when information such as a copying machine or a person to be copied can be added to an output image, a change in the tint of the output image is minimized, even if the information is added in a color that is most difficult for human eyes to recognize. Although it is necessary, when comparing the output image with the information and the original, there is a problem that the overall color is slightly different.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to add predetermined information to an image while suppressing image quality deterioration.

[0006]

The present invention has the following configuration as one means for achieving the above object. The image processing method according to the present invention, when modulating a plurality of pixel data adjacent to the original image data at a predetermined position to add predetermined information to the original image, the plurality of pixel data are complementary to each other after the modulation. The modulation is performed so that Further, when adding predetermined information to the image data using the unit modulation area including the first and second areas having a predetermined positional relationship, the first and second areas after modulation are mutually It is characterized in that these regions are modulated so as to be complementary.

An image processing apparatus according to the present invention comprises a generating means for generating predetermined information and a plurality of pixel data adjacent to the original image data at a predetermined position so as to add the predetermined information to the original image. Modulation means, wherein the plurality of pixel data are modulated so as to be complementary to each other after the modulation. An image processing apparatus for adding predetermined information to image data by using a unit modulation area including first and second areas having a predetermined positional relationship, wherein the generation means generates the predetermined information And modulation means for modulating the first and second regions after modulation so that the regions are complementary to each other.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings. In the following embodiments, a copying machine is shown as an application example of the present invention, but the present invention is not limited to this, and other devices such as a printer and a printer interface may be used without departing from the spirit of the present invention. It is also possible to apply the present invention to an apparatus. In addition, the specific manuscript includes not only those whose copying is prohibited by law, such as banknotes and securities, but also everything up to specific uses such as confidential documents.

[0009]

First Embodiment [Overview of Apparatus] FIG. 1 is an example of an overview of an apparatus according to a first embodiment of the present invention. In FIG. 1, 220
An image scanner 1 reads a document at a resolution of, for example, 400 dpi (dots / inch) and performs digital signal processing. Reference numeral 2202 denotes a printer which prints out an image corresponding to the document image read by the image scanner 2201 on paper in full color.

In the image scanner 2201, 22
Reference numeral 00 denotes a mirror pressure plate, and the original 22 on the original platen glass 2203
04 is illuminated by a lamp 2205,
The light is led to 2208, forms an image on a three-line sensor 2210 by a lens 2209, is decomposed into full-color information, red (R), green (G), and blue (B) components, and the light intensity of each component Signal processing unit 2
Sent to 211. The lamp 2205 and the mirror 22
06 is the speed V, and the mirrors 2207 and 2208 are the speed V /
2, electrical scanning (main scanning) of the three-line sensor 2210
By mechanical movement perpendicular to the direction,
The entire surface of the document is scanned (sub-scanning), and the read document image is sent to the signal processing unit 2211.

In the signal processing section 2211, the read image signal is temporarily stored in an image memory and then electrically processed, so that magenta (M), cyan (C), yellow (Y), black (K) ) And is sent to the printer 2202. In addition, image scanner 220
1, four reading operations are performed on the image data read by one original scanning, and one component among M, C, Y, and K is generated by image processing, respectively.
The data is sent to the printer 2202, and one printout is completed by a total of four readings and processes.

The M, C, Y, and K image signals sent from the image scanner 2201 are transmitted to the laser driver 22.
12 is sent. The laser driver 2212 modulates and drives the semiconductor laser 2213 according to the sent image signal. The laser beam passes through a polygon mirror 2214, an f-θ lens 2215, and a mirror 2216, and passes through the photosensitive drum 22.
17 is scanned.

Reference numeral 2218 denotes a rotary developing unit which includes a magenta developing unit 2219, a cyan developing unit 2220, and a yellow developing unit 22.
21; a black developing section 2222; the four developing sections alternately contact the photosensitive drum 2217 to develop the electrostatic latent image formed on the photosensitive drum with toner; Reference numeral 2223 denotes a transfer drum which winds a sheet supplied from a sheet cassette 2224 or 2225 and transfers an image developed on the photosensitive drum 2217 to the sheet.

After the four colors M, C, Y, and K are sequentially transferred in this manner, the sheet passes through the fixing unit 2226, and is discharged after the toner is fixed on the sheet. [Image scanner] FIG. 2 shows an image scanner 2201.
FIG. 3 is a block diagram showing a configuration example of FIG. In FIG.
10-1 to 3 are CCD sensors (solid-state imaging devices) having R, G, and B spectral sensitivity characteristics, which are incorporated in the three-line sensor 2210 shown in FIG. For example, an 8-bit signal is output. Therefore,
R, G, and B colors are 0 to 25 in accordance with the respective light intensities.
It is divided into five stages.

Since the CCDs 1210-1 to 3 in this embodiment are arranged at a fixed distance, the delay elements 1
Using 401 and 1402, the spatial shift is corrected. Reference numerals 1403 to 1405 denote logarithmic converters configured as a look-up table using a ROM or a RAM, and convert image data sent from the three-line sensor 2210 from a luminance signal to a density signal. Reference numeral 1406 denotes a well-known masking / UCR (under color removal) circuit. Although not described in detail, M, C, Y, and K signals for output are output at each read operation by three input signals. Then, a predetermined bit length such as 8 bits is output in a frame sequential manner.

A known spatial filter circuit 1407 corrects the spatial frequency of the output signal. Reference numeral 1408 denotes a density conversion circuit which corrects the density characteristics of the printer 2202, and is configured by the same ROM or RAM as the logarithmic converters 1403 to 1405. A pattern adding circuit 1410 adds a pattern to an output image. On the other hand, 1411
Denotes a CPU, which controls the present embodiment, and 1412, an I / O
The port is connected to the CPU 1411.

Here, the masking / UCR circuit 1406
The signal CNO separately input to the pattern addition circuit 1410 is a 2-bit output color selection signal, an example of which is shown in Table 1, and is generated from the CPU 1411 via the I / O port 1412, and is used to determine the order of the four transfer operations. Control, masking / UCR circuit 1406 and pattern adding circuit 1410
The operating conditions of are switched.

[0018]

[Table 1] [Pattern Adding Method] First, an example of a pattern adding method in the present embodiment will be described.

FIG. 3 is a diagram for explaining an example of an additional pattern according to the present embodiment. In the figure, 4 × 4 pixels included in an area 301 are modulated so that the gradation of the image signal is, for example, + α, and 2 × 4 pixels included in the areas 302 and 303 are, for example, The gradation is modulated so as to be −α, and the pixels outside the regions 301 to 303 are not modulated. The 8 × 4 pixels included in the areas 301 to 303 are set as unit dots of the additional pattern. in this way,
The reason for using 8 × 4 pixels as one unit of the additional pattern is that the printer 2202 of the present embodiment uses two pixels in a known image area.
This is because the 00 line processing is performed, and if the unit of the additional pattern is 1 pixel, the additional pattern may be difficult to read.

FIG. 4 and FIG. 5 are diagrams showing an example of the add-on line of the present embodiment. In FIG. 4, reference numeral 401 denotes an add-on line, for example, having a width of 4 pixels. 401a to 401
e is a unit dot shown in FIG. 3, for example, 8 × 4
Pixel. The unit dots 401a to 401e are arranged at a substantially constant period of d1 (for example, 128 pixels) in the main scanning direction.

Further, in FIG. 5, reference numerals 501 to 510 denote add-on lines having a width of, for example, 4 pixels, and are arranged at a substantially constant period of d2 (for example, 16 pixels) in the sub-scanning direction. Although details will be described later, for example, one add-on line indicates 4-bit information, and the add-on lines 502 to 50
The eight add-onlines 9 can be combined to represent a 32-bit additional information. The add-on lines are repeatedly formed in the sub-scanning direction. For example, add-ons 501 and 509 shown in FIG. 5 represent the same information.

FIGS. 6 and 7 show an example of a method of expressing information by add-on-line. In FIG. 6, reference numerals 601 and 602 denote add-on lines, and both add-on lines are adjacent to each other in the sub-scanning direction. Also, 601a, 601b and 602a are unit dots, and the adjacent add-online unit dots are at least d3 (for example, 32) in the main scanning direction in order to prevent adjacent ad-online unit dots from approaching and conspicuous. Pixel).

The data represented by the unit dot is determined by the phase difference between the unit dot 602a and the unit dot 601a. FIG. 6 shows an example representing 4-bit information. In FIG. 6, the unit dot 602a represents data "2". For example, the unit dot 602a
Is at the left end, data "0" is written in the unit dot 602a.
Indicates the data 'F' if at the right end.

In FIG. 7, among the set of add-on lines representing all additional information, FIG. 7A shows the first add-on line Line0, and FIG. 7B shows the fourth add-online Line3. As shown in FIG. 7, Line 0 has dots 702a at intervals of d4 (for example, 16 pixels) to the right of all the original unit dots 701a to 701d.
702d are added, and dots 705a to 705d are added to Line 3 at intervals of d5 (for example, 32 pixels) to the right of all the original unit dots 704a to 704d. This additional dot is for each ad online,
It is a marker for clarifying the number of the ad online. Note that the reason why the markers are added to the two add-on lines is that the upper and lower sides in the sub-scanning direction can be determined even from the output image.

Further, for example, a pattern to be added is added only with the Y toner by utilizing the fact that the human eyes have a low discriminating ability with respect to a pattern drawn with the Y toner. Also, the dot interval of the additional pattern in the main scanning direction,
The repetition interval of all additional information in the sub-scanning direction needs to be determined so that all information is reliably added to a thin and uniform area where dots can be reliably identified in a specific original document. . As a rule of thumb, information may be added with a pitch that is less than half the width of a thin and uniform area so that the dots can be reliably identified in the target specific document.

[Pattern Adding Circuit] Next, an example of the pattern adding circuit of this embodiment will be described. 8, 9,
FIG. 10 is a block diagram showing a configuration example of the pattern adding circuit 1410. In the figure, a sub-scanning counter 819 outputs a main-scanning synchronization signal HSYNC to a main-scanning counter 814.
Then, the pixel synchronization signal CLK is repeatedly counted with a width of 7 bits, that is, 128 cycles. Sub-scanning counter 8
AND gate 820 connected to 19 outputs Q2 and Q3
Outputs H when both bits 2 and 3 of the sub-scanning counter 819 are H. That is, AND gate 8
The output 20 is H for a period of 4 lines every 16 lines in the sub-scanning direction, and this is set as an add-on enable signal.

The gate 822 receives the output of the AND gate 820 and the upper three bits (Q4 to Q6) of the sub-scanning counter 819. The enable signal LINE0 of the add-on line 0 is supplied to the gate 821. Therefore, the enable signal LI of the line 3 of the add-on line
NE3 is generated. On the other hand, an initial value is loaded into the main scanning counter 814 by HSYNC, which will be described later in detail, and the gates 815 to 817 are connected to the main scanning counter 8.
14 high-order 4 bits (Q3 to Q6) are input. AND
The output of the gate 815 is a section of 8 pixels every 128 pixels,
H, which is used as a dot enable signal. The gates 816 and 817 are connected to signals LINE0 and LINE, respectively, in addition to the upper 4 bits of the main scanning counter 814.
E3 is input to generate enable signals for the marks of line 0 and line 3, respectively. These dot and mark enable signals are combined by an OR gate 818. Further, the output of the OR gate 818 and the output of the AND gate 820 are ANDed by the AND gate 824, and the dot becomes H only on the add-on line. And a mark enable signal.

The output of the AND gate 824 is supplied to the F / F 82
8, synchronized with the pixel synchronization signal CLK,
In the D gate 830, a logical product is performed with a 2-bit output color selection signal CNO. The bit 0 of the output color selection signal CNO is negated by the inverter 829 and input to the AND gate 830, and the bit 1 of the output color selection signal CNO is input to the AND gate 830 as it is, so that the signal CNO = "10". That is, when the Y color image is printed, the dot and mark enable signals become valid.

Further, the output of the AND gate 824 is also connected to the clear terminal CLR of the counter 825,
The counter 825 counts the pixel synchronizing signal CLK only when the AND gate 824 is at H, that is, when the add-on dot is enabled. Bits 1 and 2 output from the counter 825 are input to the Ex-NOR gate 826. The output of the Ex-NOR gate 826 becomes L during the period of 4 CLK which is the middle of the add-on dot period (8 CLK). The output of Ex-NOR gate 826 is F
/ F827 to be synchronized with the pixel synchronization signal CLK and output as the signal MINUS. Signal MINUS is L
At this time, the dot of the add-on line is modulated to + α.

The F / F 827 is used to remove the whiskers of the signal MINUS and to match the phase with the add-on dot enable signal. Signal MIN
US is input to the selection terminal S of the selector 838. A
The ND section 832 receives, for example, an 8-bit modulation amount α from the register 831 and the output of the AND gate 830. At the time of the add-on dot timing, AN
Since the output of the D gate 830 becomes H, the AND unit 832
Outputs the modulation amount α at the time of the add-on dot timing. Therefore, for pixels other than the add-on dot, the modulation amount output from the AND circuit 832 is 0.
Is not modulated.

An adder 833 and a subtractor 835 input an image signal V of, for example, 8 bits to a terminal A. The modulation amount α output by the AND unit 832 to the terminal B, the output of the adder 833 is input to the OR circuit 834, and the output of the subtractor 835 is input to the AND circuit 837. Note that the OR circuit 834 calculates the addition result V + of the addition circuit 833.
When α overflows and the carry signal CY is output, the calculation result is forced to, for example, 255. Also,
The AND circuit 837 calculates the subtraction result V−α of the subtraction circuit 835.
Is underflowed and a carry signal CY is output, the operation result is forcibly set to, for example, 0 by the carry signal CY inverted by the inverter 836.

The two calculation results V + α and V-α are supplied to the selector 8
38, and is supplied to the selector 8 according to the signal MINUS.
38. With the above circuit configuration, the dot modulation shown in FIG. 3 is performed. The main scanning counter 8
The value to be loaded into 14 is generated as follows. First, the F / F 813 and the counter 809 are reset by the sub-scanning synchronization signal VSYNC, so that the initial value of the main scanning counter 814 is set to 0 in the first add-on.

Here, the signal ADLIN input to the clock terminal of the counter 809 and the F / F 813 synchronizes the output of the AND gate 820, which is an add-on enable signal, with the main scanning synchronization signal HSYNC by the F / F 823. Signal. The selector 810 is connected to the select terminal S
In response to, for example, a 3-bit signal input to the register, one of registers 801 to 808 in which, for example, a 4-bit value of each of the eight add-ons is set is selected.
Outputs the value set in the selected register.

The select signal of the selector 810 is the signal A
It is generated by a counter 809 that counts DLIN. At the first add-on-line timing, since the counter 809 is cleared by the sub-scanning synchronization signal VSYNC, the select signal is 0. Therefore, the selector 810 selects the register 801. And the signal A
When DLIN rises, the count value of counter 809 advances by one, and selector 810 selects register 802. Thereafter, the selector 810 repeatedly selects the registers 803 to 808 sequentially in synchronization with the signal ADLIN.

The output of the selector 810 is supplied to an adder 811
Is added to the output of the adder 812, input to the F / F 813, latched at the falling edge of the signal ADLIN, and input to the main scanning counter 814. Note that the output of the F / F 813 is sent to the main scanning counter 814 and also input to the terminal B of the adder 812, and the terminal A of the adder 812.
Is added to a constant value, for example, 8 inputted to the adder 8
It is sent to 11. This is an offset value for providing an interval between the add-on dot position and the immediately preceding add-on dot position in the sub-scanning direction.

[Copy Result] FIG. 11 is a diagram showing an example of a copy result according to the present embodiment, but shows only an example of arrangement of unit dots of add-on line. In FIG. 11, 90
Reference numeral 1 denotes a specific document image, for example. The unit dot of the add-on line is indicated by a triangle.

As described above, according to this embodiment,
By expressing the serial number unique to the copying machine or a code obtained by encoding the serial number in an additional pattern, if the present embodiment is used for illegal copying, etc.
By examining the illegal copy, the copying machine used for the illegal copy can be specified. Furthermore, when adding a pattern to an output image, by combining complementary image signal modulations in a small area, and preserving the density as a whole,
It is possible to reduce the deterioration of the image quality without changing the color.

When microscopic observation is performed by complementary image signal modulation, an additional pattern can be easily found, and the additional information can be more reliably decoded.

[0039]

Second Embodiment Hereinafter, a second embodiment according to the present invention will be described. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. The external appearance of the apparatus according to the second embodiment is substantially the same as that shown in FIG. 1 of the first embodiment, and a detailed description thereof will be omitted.

FIG. 12 shows an image scanner 22 of this embodiment.
FIG. 2 is a block diagram showing an example of the configuration of No. 01. 12 differs from the image scanner 201 of the first embodiment shown in FIG. 2 in that a specific document determination circuit 1409 is added. Here, the specific document determination circuit 140
9 determines the possibility that the image data being read contains image data of a specific document, and outputs the determination result as a 2-bit determination signal H. That is, if the possibility that at least one of a plurality of specific originals is being read is the strongest, H = '11 'is output, and if it is the least, H = '00' is output.

An output color selection signal CNO is input to the determination circuit 1409, and the determination standard is switched for each of the four transfer operations to determine a different specific document. Further, although details will be described later, the CPU 141
The pattern adding circuit 1410 changes the pattern adding process in accordance with the 2-bit pattern level selection signal PS output by 1.

[Timing Chart] FIG. 13 is an example of a main scanning timing chart in this embodiment. In the figure, VSYNC is a sub-scanning synchronization signal, which is a signal indicating a sub-scanning image output section. HSYNC is a main scanning synchronization signal that synchronizes the start of main scanning.

CLK is a pixel synchronization signal, which is a basic clock for various image processing in this embodiment. On the other hand, CLK
Numeral 4 denotes a signal obtained by dividing CLK by 4, and is a basic clock in the judgment circuit 1409. SEL is a timing signal used in the thinning circuit 1301 shown in FIG.

The signal CLK4 and the signal SEL are shown in FIG.
This is generated by a frequency dividing circuit 1310 shown in FIG. That is, an inverter 1451, a 2-bit counter 1452, an inverter 1453, and an AND gate 1454.
And the 2-bit counter 1452 has the HSYN
After being cleared (initialized) by C, CLK is counted and the count value is output in two bits. The upper bit D1 is output as CLK4 and the lower bit D0 is output.
Is the logical product of the inverted signal and the upper bit D1.
Output as L.

FIG. 14A shows a thinning circuit 1 having a configuration example.
Reference numeral 301 denotes an F / F 1455 for holding data with CLK.
1457 and 1461 to 1463, selector 1458
／ 1460, F / F 146 holding data at CLK4
4-1466, as shown in FIG.
From among the R (or G, B) signals transferred by CLK,
An R '(or G', B ') signal synchronized with CLK4 can be obtained at a rate of 1/4.

[Determining Means] FIG. 15 is a block diagram showing a configuration example of the determining circuit 1409. In FIG.
Reference numeral 01 denotes a thinning circuit as shown in FIG.
In order to reduce the processing load of the determination circuit 1409, image data in which some data of the input image is thinned out is output.

Reference numeral 1310 denotes a lookup table LUT.
In order to match colors with a plurality of types of specific documents, for example, a ROM is used to check the color distribution of, for example, eight types of specific documents, and to determine the color of the input image and the color of the specific document image. Information for determining whether or not the taste matches is stored. To the LUT 1310, the output color selection signal CNO is input to the upper 2 bits of the address terminal, and to the lower 15 bits, the upper 5 bits of the RGB image signal of each color thinned out by the thinning circuit 1301 are input.

The LUT 1310 outputs the output color selection signal C
In response to NO, whether or not the color of the pixel matches the color in, for example, eight types of specific originals is simultaneously output in association with the 8-bit data, and the specific original is output in four transfer operations. For example, a total of 32 types of determinations are made. Reference numerals 1303-1 to 130-8 denote color determination circuits each including the same hardware, each including an integrator 1304, registers 1305 to 1307, and a comparison unit 1308, each of which may include a specific document image in an input image. The output is a two-bit signal.

Reference numeral 1309 denotes a maximum value circuit which outputs the maximum value of the judgment output of the color judgment circuits 1303-1 to 130-8 as a 2-bit judgment signal H. That is, a determination result of the largest possible original among a plurality of specific originals is output. [Integrator] FIG. 16 is a block diagram showing a configuration example of the integrator 1304.

Reference numerals 1501 and 1505 denote F / F, CL
Data is held at the rise of K4. A multiplier 1502 receives two 8-bit signals (A, B) and outputs an 8-bit signal (A × B / 255) as a multiplication result. Fifteen
Numeral 03 is also a multiplier, which receives a 1-bit signal (A) and an 8-bit signal (B), and outputs an 8-bit signal (A) as a multiplication result.
× B) is output.

Reference numeral 1504 denotes an adder which receives two 8-bit signals (A, B) and outputs an 8-bit signal (A) as an addition result.
+ B) is output. As a result, integrator 1304, 2
The relationship between the value input signal x _i and the 8-bit output signal y _i is expressed by the following equation. y _i = (α / 255) y _i-1 + βx _i-1 (1) In the above equation, α and β are constants set in advance, and are integrated according to the magnitudes of these values. The characteristics of the vessel 1304 are determined.

For example, FIG. 17 shows an example of input and output of the integrator 1304 when α = 247 and β = 8. That is, with respect to the input x _i as shown in FIG. 17 (a), FIG. 1
An output y _i as shown in FIG. 7 (b) is output. In FIG. 17, an input x such as 701 and 702 that is “1” despite being almost “0” before and after
Inputs x _i such as _i and 703 that are “0” despite being almost “1” before and after are considered to be noise. The input x _i is integrated by an integrator 1304, and y _i is calculated by a comparator 1308 according to threshold values R1 to R3 set in registers 1305 to 1307 as shown in 704 to 706 in FIG. By converting to a value, the above-described noise can be removed.

[Comparator] FIG. 18 is a block diagram showing a configuration example of the comparison unit 1308. 1601 to 1603 are comparators, 1604 is an inverter, and 1605 is AND
Gates 1606 and 1607 are OR gates. The threshold values R1 to R3 are set in the registers 1305 to 1307 in a relationship of R1>R2> R3.

That is, comparing section 1308 outputs “11” when R1 <(input), “10” when R2 <(input) ≦ R1, “01” when R3 <(input) ≦ R2,
If (input) ≦ R3, output '00'. [Pattern Adding Circuit] FIGS. 19, 20 and 21 are block diagrams showing examples of the structure of the pattern adding circuit 1409.

The difference between the pattern adding circuit of the second embodiment shown in FIGS. 19, 20, and 21 and the pattern adding circuit of the first embodiment shown in FIGS. 8, 9, and 10 is that the modulation amount α is stored. That is, there are four registers in the first embodiment and four registers in the second embodiment. Therefore, in the second embodiment, the selector 1705 selects the modulation amounts α1 to α4 stored in the four registers.

Referring to FIGS. 19, 20 and 21, 170
Reference numerals 1 to 1704 denote registers which store different amounts of modulation amounts α1 to α4, respectively. Reference numeral 1705 denotes a 4-input / 1-output selector which selects one of the modulation amounts α1 to α4 stored in the registers 1701 to 1704 according to the pattern level selection signal PS output from the CPU 1411,
Output to D gate 832.

Here, the modulation amount is α1 <α2 <α3 <α4
And the selector 1705 determines that PS =
Α1 for '00', α2 for PS = '01 ',
Α3 when PS = “10”, α when PS = “11”
4 is output. Therefore, the output V ′ of the selector 838 is
When PS = `00`, V ± α1 when PS =` 01`, V ± α3 when PS = `10`, PS ± 3
In the case of = '11 ', it is modulated to V ± α4.

That is, the modulation amount α is changed in accordance with the possibility that the specific image is included in the input image, and a pattern is added to the normal output image so as to be hardly discernable by human eyes. Is more likely to be present, a more specific pattern is added to the output image. [Flowchart] FIG. 22 is a flowchart showing an example of the flow relating to the setting of the pattern level selection signal PS performed by the CPU 1411.

First, at the start of copying, in step S11, the CPU 1411 initializes the pattern level selection signal PS to "00". Subsequently, in step S12, the CPU 1411 compares the determination signal H with the pattern level selection signal PS. If the comparison result is PS <H, the CPU 1411 sets the value of the determination signal H to the pattern level selection signal PS in step S13, and returns to step S12 if PS ≧ H.

That is, the maximum value of the determination signal H from the start of copying to the present is determined by the pattern level selection signal P
Set to S. As described above, according to the present embodiment, in addition to the same effects as those of the first embodiment, the additional pattern of the output image that does not include the specific document can be more difficult to be identified by human eyes. Image quality degradation of the output image can be minimized.

Accordingly, the present embodiment is particularly effective when color reproducibility is important, for example, for color copying in relation to design. Further, when image data on the host computer is printed by a color copying machine or the like via an external interface, for example, in CG (computer graphics) printing, image quality deterioration in an achromatic region can be minimized.

In the first embodiment, the additional pattern represents a device-specific serial number or a code obtained by encoding or encoding the serial number. However, the present invention is not limited to this. Instead, the additional pattern may represent information that can specify the device, for example, the date of manufacture of the device, the lot number of the device, the version of the device, and the like, and the additional pattern represents the information that can specify the device. Instead, it may be information that can specify a person who has used the device. For example, in order to limit the number of users, devices that require an ID card to be inserted and devices that require an ID number to be used are already known, but in these devices, the additional pattern is The ID number may be a recognized ID number or a code obtained by encoding or encoding the same ID number, and may include a date and time when copying is executed or a code obtained by encoding or encoding the same date and time.
The present invention may be applied to a system including a plurality of devices or to an apparatus including a single device.

It is needless to say that the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0064]

As described above, according to the present invention,
By modulating the image data complementarily, it is possible to add predetermined information to the image while suppressing deterioration of the image quality.

[Brief description of the drawings]

FIG. 1 is an example of an outline view of an apparatus according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration example of an image scanner.

FIG. 3 is a diagram illustrating an example of an additional pattern.

FIG. 4 is a diagram showing an example of an add-on line;

FIG. 5 is a diagram showing an example of an ad online,

FIG. 6 is a diagram showing an example of a method of expressing information by add-on-line,

FIG. 7 is a diagram showing an example of a method of expressing information by add-on-line,

FIG. 8 is a block diagram showing a configuration example of a pattern adding circuit;

FIG. 9 is a block diagram illustrating a configuration example of a pattern adding circuit;

FIG. 10 is a block diagram illustrating a configuration example of a pattern adding circuit.

FIG. 11 is a diagram showing an example of a copy result;

FIG. 12 is a block diagram illustrating a configuration example of an image scanner according to a second embodiment of the present invention;

FIG. 13 is an example of a main scanning timing chart;

FIG. 14 is a block diagram showing a configuration example of a thinning circuit and a frequency dividing circuit;

FIG. 15 is a block diagram illustrating a configuration example of a determination circuit;

FIG. 16 is a block diagram illustrating a configuration example of an integrator.

FIG. 17 is a diagram showing an example of input and output of an integrator;

FIG. 18 is a block diagram illustrating a configuration example of a comparison unit.

FIG. 19 is a block diagram illustrating a configuration example of a pattern adding circuit.

FIG. 20 is a block diagram illustrating a configuration example of a pattern adding circuit;

FIG. 21 is a block diagram illustrating a configuration example of a pattern adding circuit.

FIG. 22 is a flowchart illustrating an example of setting a pattern level selection signal.

Claims (16)

(57) [Claims] When modulating a plurality of pixel data adjacent to original image data at a predetermined position so as to add predetermined information to an original image, the plurality of pixel data are complementary to each other after the modulation. An image processing method characterized by modulating. 2. The method according to claim 1, wherein the modulation is performed by subtracting a predetermined value from a part of the plurality of pixel data and adding the predetermined value to another part of the plurality of pixel data. Item 1. The image processing method according to Item 1. Wherein the modulation image processing method according to claim 2, characterized in that the human eye is performed <br/> image data of hardly recognized color. 4. The apparatus according to claim 1, wherein the predetermined information is used to specify an apparatus.
2. The image according to claim 1,
Image processing method. 5. The predetermined information includes a person who has used the device.
Claim 1 characterized in that it is information for specifying
Image processing method described . 6. The method according to claim 1, wherein the predetermined information is included in the original image.
It is information for specifying the added date and time
2. The image processing method according to claim 1, wherein: 7. The method according to claim 6, wherein the predetermined information is periodically added to the original image.
The image according to claim 1, wherein the image is added to the image.
Image processing method. 8. A generator for generating predetermined information, and an original image at a predetermined position for adding the predetermined information to an original image.
Modulating means for modulating a plurality of pixel data adjacent to image data
And the plurality of pixel data are complementary to each other after modulation.
An image processing apparatus characterized by being modulated as follows. 9. A method according to claim 1, wherein the first and second positions are in a predetermined positional relationship.
Image data using the unit modulation area including the
When adding predetermined information, the first and second
Modulate two regions so that they are complementary to each other
An image processing method comprising: 10. The method according to claim 1, wherein the modulation is performed on pixels in the unit modulation area.
A predetermined value is subtracted from a part of the data, and the
The predetermined value is added to another part of the pixel data.
10. The image processing method according to claim 9, wherein
Law. 11. The color modulation which is difficult for human eyes to recognize.
11. The method according to claim 10, wherein
Image processing method described. 12. The apparatus according to claim 11, wherein the predetermined information includes information for identifying an apparatus.
10. The image processing method according to claim 9, wherein the information is information for use in the image processing. 13. The predetermined information is a person who has used the apparatus.
Claim, characterized in that information for specifying a 9
The image processing method described in 1 . 14. Information of the plant constant, it is the original image
10. The image processing method according to claim 9 , wherein the information is information for specifying a date and time added to the image. 15. The method according to claim 15, wherein the predetermined information includes a period in the original image.
10. The image processing method according to claim 9 , wherein the image processing method is added . 16. A method according to claim 16, wherein said first position is in a predetermined positional relationship.
Image data using the unit modulation area including the
An image processing apparatus for adding predetermined information to the image data, wherein the generation means for generating the predetermined information and the first and second areas after modulation are complementary to each other.
Modulating means for modulating those areas in such a way that
An image processing apparatus characterized by the above-mentioned.