JP3367959B2 - Image processing apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method capable of making a judgment on a specific original such as a bill or securities.

[0002]

2. Description of the Related Art In recent years, as the performance of color copiers and color printers has improved, crimes of illegally using them to forge bills, securities, etc. have increased. When a crime of this kind occurs, it is almost impossible to identify which device has made a copy, or the person who made a copy, based on the copied product.

In order to prevent such a crime, data of an image pattern corresponding to the above-mentioned specific original is registered in the color copying machine or the color printer itself, and the image recognition circuit identifies it to forcibly make an illegal copy. Prohibitions are being considered.

However, such a counterfeiting prevention circuit has a drawback in that all banknotes and securities cannot be registered because the number of image patterns that can be registered is limited.

In a color copying machine or a color printer having an external interface, such a counterfeiting prevention circuit may not function. For example, if the image data on the external interface has a specification in which the three primary color data of red (R), green (G), and blue (B) are sent at the same time, the forgery prevention circuit can operate, but cyan (C), magenta (M), yellow (Y), and black (K), if the data specifications are matched to the individual characteristics of the printer, there are multiple types of color-reproducible combinations, so the determination is made. Since a plurality of image patterns are required, the determination for preventing forgery becomes very difficult, and the number of images that can be determined decreases. Furthermore, when the image data of each color component is sent frame by frame,
Image data must be stored in a memory for image determination, which causes a problem that the cost of the device becomes high and a large amount of money is required for the forgery prevention determination.

Further, assuming that the problem of the image signal from the external interface has been solved, a specific original document,
For example, even if recognition is performed by limiting the number of bills and securities to the number that can be recognized, a picture that closely resembles a registered bill will be erroneously determined to be a bill, and a dirty bill will be recognized. It was unavoidable to make an erroneous decision that it was not a bill.

Therefore, it is important to add means for preventing forgery to the device itself, but there is a limit to detection, so
When a document that should not be originally copied is copied, it is important to identify the copying machine or the person who copied the copy. Based on this background, the applicant of the present invention is studying a technique for adding information such as a copy machine or information that can identify a person who made a copy, to a document image. The technique is to use the output color component (eg, magenta, cyan, yellow, black) of the copying machine, which is the least noticeable to the human eye, as the serial number of the copying machine. Modulating the image signal of the output color component (for example, adding a constant value) in the form of numbers or symbols such as is repeated at regular intervals.

[0008]

However, in the above-mentioned conventional example, the modulation of the image signal must be minimized even though yellow is the output color component that is the most invisible to the eye. In particular, when a color copying machine is used for design purposes, it is troublesome to see patterns that are not on the original. Also, when copying an original, even if the original has a uniform color, the image signal is not always uniform due to variations in the sensitivity of the scanner, etc. Since it is possible to directly output CG (computer graphics) when printing out, there may be a sufficient uniform area at the image signal level. At this time, when the yellow component is modulated, the additional pattern becomes conspicuous particularly in a light gray or light blue uniform portion.

Further, in the method of expressing a pattern in a unit in which a number or a code is collected and repeating the pattern in this unit at a constant interval to form an overall additional pattern, each pattern is small and conspicuous. Also, since the human eye is more likely to recognize a regular pattern such as the above-mentioned additional pattern than a randomly arranged pattern, if the pattern is arranged on the lattice, it becomes rather conspicuous. . Therefore, if the degree of modulation of the image signal is reduced, the additional pattern cannot be read depending on the specific original.

Therefore, in all output images, it is difficult to discriminate when visually observed, and a condition having the opposite direction that it can be discriminated surely in a target copy such as a bill by some method is satisfied. It is necessary to consider solutions such as modulation methods and patterns.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide an image processing apparatus and method capable of suppressing deterioration of an image and embedding predetermined information in the image.

[0012]

In order to achieve the above object, the image processing apparatus of the present invention has the following configuration.
That is, an image processing apparatus that outputs image data corresponding to a plurality of different colors, and that is an apparatus that has performed image output.
Alternatively, in order to add information for identifying a person to the image data, a plurality of density-modulated dots are arranged with a phase difference in the main scanning direction between adjacent lines based on the information.
Of the plurality of lines are controlled to be arranged at predetermined intervals in the sub-scanning direction, and the predetermined lines of the plurality of lines are controlled so as to include a mark for indicating which part of the information the information represents. And an addition unit that adds the dots and marks to the image data according to the arrangement control of the control unit when processing image data corresponding to a color that is difficult for the human eye to identify among the plurality of different colors. Output means for outputting the result added by the adding means.

In order to achieve the above object, the image processing method of the present invention has the following configuration. That is, it is an image processing method in an image processing apparatus that outputs image data corresponding to a plurality of different colors .
In order to add information identifying a device or a person to the image data, density-modulated dots are arranged with a phase difference in the main scanning direction between adjacent lines based on the information.
Place controlled at predetermined intervals a plurality of lines in the sub-scanning direction, a predetermined line of the plurality of lines is controlled so as to include a mark for indicating whether the line represents which portion of the information of said information When processing the image data corresponding to the control step and the color that is difficult for human eyes to identify among the plurality of different colors, the dots and marks are added to the image data according to the arrangement control of the control step. It is characterized by comprising an adding step and an output step of outputting a result added in the adding step.

[0014]

In the above structure, the device or the device that outputs the image
In order to add information to identify the person to the image data,
Phase in the main scanning direction between adjacent lines based on the information of
Multiple lines in which density-modulated dots are arranged with a difference
Position control in the sub-scanning direction at a predetermined interval, and
The predetermined line of the Inn is the line
Include a mark to indicate which part of the information is represented
Difficult to control and identify to the human eye out of multiple different colors
Layout when processing image data corresponding to a certain color
Add dots and marks to image data according to control
Works like.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In the following embodiments, an example of a copying machine is shown as an application example of the present invention, but the present invention is not limited to this, and it goes without saying that it can be applied to various other apparatuses. <First Embodiment> [Apparatus Overview] FIG. 2 is a side sectional view showing the internal structure of a copying machine according to the first embodiment of the present invention. In FIG. 2, reference numeral 201 denotes an image scanner section, which is a section for reading an original at a resolution of 400 dpi (dot / inch) and performing digital signal processing. Also, 2
A printer unit 02 includes an image scanner unit 201.
The image corresponding to the original image read by
It is a part that prints out in full color on paper with a resolution of dpi.

In the image scanner unit 201, 20
Reference numeral 0 denotes a mirror surface pressure plate, and an original 204 on an original platen glass (hereinafter referred to as “platen”) 203 is illuminated by a lamp 205, guided to mirrors 206, 207 and 208, and a lens 209 is used to detect a 3-line sensor. (Hereafter, "CC
An image is formed on 210) (referred to as “D”) and is sent to the signal processing unit 211 as full color information red (R), green (G), and blue (B) components. The lamp 205 and the mirror 206 have a speed v, and the mirrors 207 and 208 have a speed 1 /.
By mechanically moving in the direction perpendicular to the electrical scanning (main scanning direction) of the CCD 210 at 2v, the entire surface of the document is scanned (sub scanning).

In the signal processing section 211, the read image signal is electrically processed and decomposed into magenta (M), cyan (C), yellow (Y) and black (Bk) components, and the printer section. Send to 202. In addition, M, C, and
One component of Y and Bk is sent to the printer unit 202, and a total of four document scans completes one printout.

The M, C, Y and Bk image signals sent from the image scanner unit 201 are supplied to the laser driver 2.
Sent to 12. The laser driver 212 modulates and drives the semiconductor laser 213 according to the sent image signal. The laser light is the polygon mirror 214 and the f-θ lens 2
15, the photosensitive drum 217 is scanned via the mirror 216.

Reference numeral 218 denotes a rotary developing device, which has a magenta developing section 219, a cyan developing section 220, and a yellow developing section 22.
The first developing unit 222 includes a black developing unit 222 and four developing units alternately contact the photosensitive drum 217 to develop the electrostatic development formed on the photosensitive drum 127 with toner. Reference numeral 223 denotes a transfer drum, which winds the paper supplied from the paper cassette 224 or 225 around the transfer drum 223, and transfers the image developed on the photosensitive drum to the paper.

In this way, after the four colors M, C, Y and Bk are sequentially transferred, the paper passes through the fixing unit 226, the toner is fixed on the paper, and then the paper is ejected. [Image Scanner] FIG. 1 is a block diagram showing the arrangement of the image scanner unit 201 according to the first embodiment. In the figure, 210-1, 210-2, and 210-3 are CCD (solid-state image sensor) sensors having spectral sensitivity characteristics of red (R), green (G), and blue (B), respectively. 8-bit output 0 to 2 after conversion
55 signals are output.

Since the CCD sensors 210-1, 210-2, 210-3 used in this embodiment are arranged at a fixed distance, the delay elements 101 and 1 are provided.
At 02, the spatial deviation is corrected.

Reference numerals 103, 104 and 105 denote log converters, which are constituted by a look-up table ROM or RAM and convert a luminance signal into a density signal. Reference numeral 106 is a masking and UCR (undercolor removal) circuit. In the masking / UCR circuit 106, the magenta (M), cyan (C), yellow (Y), and black (Bk) signals for output are output by the input three signals at each reading operation. The data is sequentially output with a predetermined bit length, for example, 8 bits.

A spatial filter circuit 107 corrects the spatial frequency of the output signal. A density conversion circuit 108 corrects the density characteristics of the printer unit 202, and has a ROM or a RAM like the log converters 103 to 105.

Reference numeral 111 is a microcomputer (hereinafter referred to as "CPU") that controls the apparatus, and 110 is an input / output port (hereinafter referred to as "I / I") connected to the CPU 111.
"O port").

The CNO signal is a 2-bit output color selection signal and is a control signal indicating the order of four reading operations. FIG. 28 is a diagram showing the relationship between the CNO signal and the print output according to the first embodiment. The CNO signal is the CPU
It is generated from 111 via the I / O port 110 and switches the operating condition of the masking / UCR circuit 106.

Reference numeral 109 denotes a pattern addition circuit, which is a portion for adding a pattern of a color which is difficult for human eyes to identify to the copied image. [Pattern Adding Circuit] FIG. 3 is a block diagram showing the structure of the pattern adding circuit 309 according to the first embodiment. In the figure, 301 is a sub-scanning counter, 302 is a main scanning counter, and 303 is a lookup table RAM.
(Hereinafter referred to as “LUT”), 304 is an AND gate, 3
05 is a flip-flop, 306 is an inverter, 307
Is an AND gate, 308 is a register, 309 is an AND gate, and 310 is an adder.

Here, the sub-scanning counter 301 repeatedly counts the main scanning synchronizing signal HSYNC and the main scanning counter 302 repeatedly counts the pixel synchronizing signal CLK with a 7-bit width, that is, 128 cycles. Further, the LUT 303 is a random access memory (hereinafter referred to as “RAM”) in which a pattern to be added is held, and the lower 5 bits to the least significant bit of the count value of each of the sub scanning counter 301 and the main scanning counter 302 are stored. The removed 4 bits are input. Only one bit is referred to for the output of the LUT 303, and this one bit is supplied to the main scanning counter 301 and the sub scanning counter 302 by the AND gate 304.
ANDed with the upper 2 bits of each. This result is
It is synchronized with the CLK signal in the flip-flop 305, ANDed with both the 2-bit CNO signal “0” and the CNO signal “1” in the AND gate 307, and then sent to the AND gate 309. This is CN
This signal is valid only when O = 2, that is, when the image is currently printed in yellow.

Here, the level (modulation amount) of the pattern to be added is stored in the register 308 in advance, and AND
The gate 309 becomes effective only when CNO = 2 (on the yellow side), and the adder 3 is added to the image data V.
It is added at 10.

It should be noted that the additional pattern is added only by the yellow toner so that it is difficult for the human eye to identify it. However, this has a weak identification ability with respect to the pattern drawn by the human eye with the yellow toner. This is what was used.

FIG. 4 is a diagram for explaining an additional pattern according to the first embodiment.

The LUT 303 holds a dot pattern as shown in FIG. 4, that is, an additional pattern. One square in FIG. 4 corresponds to one bit held in the LUT 303, where white indicates 0 and black indicates 1. The horizontal direction corresponds to the lower 4 bits of the address, and the vertical direction corresponds to the upper 4 bits of the address, and the additional pattern is composed of 256 bits. A line in which the upper 4 bits of the address on the left side of FIG. 4 are 0 (the uppermost 1 line) is a mark indicating the reference position. Further, the 6 lines of the upper 4 bits of the address which are shaded on the left side of FIG. 4 and whose upper 4 bits are 2, 3 and 8, 9, E, and F are lines on which dots are placed and are used every two lines. Each of these two lines represents 16 kinds of information by hitting one or two 2 × 2 bit dots at a determined position as shown on the right side of FIG. That is, each 2 lines is 4
Represents bit information. Since there are three of these two lines under the mark, it is possible to represent combined 12-bit information. For example, "BB" is not separated from each other and is separated from each other.
This is to prevent the additional pattern from becoming conspicuous by connecting dots vertically or diagonally when two lines of dot arrangement such as “B” and “123” are continuous.

The LUT 303 shown in FIG. 3 has a CPU
It is provided so that data can be written from (not shown), and information for identifying the source of the copy document, such as information for identifying the copying machine, is written in the state of being converted into additional pattern data. Be done.

Further, since the data excluding the least significant 1 bit of the main scanning counter 302 and the sub-scanning counter 301 of FIG. 3 is input to the LUT 303, 1 on the LUT 303 is input.
The bits correspond to 2 × 2 4 pixels on the copy. This is because the printer unit 202 of the present embodiment performs known 200-line processing in the image area, for example, and it may be difficult to read by adding a pattern on a pixel-by-pixel basis. [Copy Result] FIG. 5 is a diagram showing an example of the copy result according to the first embodiment, and FIG. 6 is a diagram for explaining the effect of the first embodiment.

First, in FIG. 5, reference numeral 501 denotes an added pattern, and the contents held in the LUT 303 are added as an image. In the example shown in FIG. 5, the pattern meaning “3FC” is set to 3 so that it is difficult for human eyes to identify the pattern.
128 pixels added in a pattern of 2 pixels x 32 pixels
It is repeated every 128 lines of pixels and sub-scanning. Therefore, by setting this as a serial number unique to the machine or as a pattern in which the serial number is encoded, the copied device can be limited by validating the copy. Furthermore,
In the present embodiment, the pitch for adding the pattern is set to every 128 pixels (or lines) in the main scan, but since the resolution is 400 dpi (dot / inch) in this embodiment, the pattern should be added about every 8 mm. become. This is an interval at which the additional pattern can be easily read on the watermark of the bill and the surrounding margins.

In the method using the additional pattern described above, as shown in FIG. 6 (b), rather than the method of modulating the image signal by using the numerical values as they are, as in this embodiment, With the method using a pattern as shown in FIG. 6A, it is possible to reduce the number of pixels to be modulated and make the additional pattern less noticeable.

As described above, according to the first embodiment, a specific additional pattern for limiting the device or the like in a copy is composed of a mark indicating a position reference and one or more dots. By recording the pattern with the copy, the number of pixels to be modulated is reduced and the additional pattern is made less conspicuous, so that the deterioration of the image quality can be reduced. Furthermore, since converting an additional pattern into a pattern of dot arrangement is a kind of encryption, this pattern is converted into a third pattern.
It also has the effect that it is difficult for a person to intentionally operate it. <Second Embodiment> Now, in the above-mentioned first embodiment, attention has been paid to preventing image quality deterioration due to a pattern for specifying the origin of a copy, but the present invention is not limited to this. A second embodiment is also included in which the possibility that the original document to be copied is a specific original document for which copying is prohibited is determined based on the perspective and the level (modulation amount) of the additional pattern is changed according to the determination result. .

The second embodiment will be described below.

FIG. 7 is a block diagram showing the arrangement of the image scanner unit 201 of the second embodiment. Device overview is first
2 of the second embodiment, the same numbers are used for circuits having similar configurations and functions, and description thereof is omitted.
Therefore, the difference from the block diagram (FIG. 1) of the image scanner unit 201 of the first embodiment is that the determination circuit 7 for the specific document is used.
This is the point where 04 is added. Further, a ROM 710 storing programs for operating the CPU 703 and a RAM 711 used as a work area for various programs are illustrated. The ROM 710 stores, for example, a program according to the flow chart shown in FIG.

Here, the specific manuscript judgment circuit 704 judges in advance that at least one of a plurality of specific manuscripts (banknotes, securities, etc.) is being read, and the judgment signal H is multivalued. It is output in 2 bits (4 levels from 0 to 3). That is, when at least one of the plurality of specific originals is most likely to be read, H = 3 is output, and H = 2 and H = 1 as the possibility decreases.
Is output, and H = 0 is output when it is the lowest. Also,
In the present embodiment, the CNO signal described above is also input to the determination circuit 704. The determination circuit 704, according to the CNO signal,
As will be described later, the determination reference can be switched corresponding to each of the four reading operations, and determination can be made for a plurality of different specific originals.

Further, the pattern addition process can be changed according to the 2-bit pattern level selection signal PS designated by the CPU 111. This will also be described later. [Determination Circuit] FIG. 8 shows a determination circuit 704 according to the second embodiment.
3 is a block diagram showing the configuration of FIG. In the figure, 801
Is a thinning-out circuit, which is a circuit for thinning out data in order to reduce the load on the circuit of the determination circuit 704 itself. Reference numeral 802 denotes a color matching / lookup table ROM (hereinafter referred to as “L
UT ”), and color matching is performed between the read original image and the images of a plurality of types of specific originals (copy prohibition documents such as banknotes and securities) prepared in advance. This LUT
In 802, the tint distributions of 32 types of specific originals are checked in advance, and the determination result of whether or not the tint of the pixel matches the tint of the specific originals is held.

That is, to the LUT 802, the CNO signal which is a frame sequential signal is input to the upper 2 bits of the address, and the upper 5 bits of the thinned RGB image signals are input to the lower 15 bits. As shown in FIG. 28, each CN
For each of the values 0 to 3 of the O signal, whether or not the tint of the pixel matches the tint of the eight types of specific originals is output at the same time in correspondence with 8-bit data. Therefore, a total of 32 types of specific documents will be determined.

803-1.803-2, ..., 803-8
Is a tint determination circuit configured by the same hardware, and includes an integrator 804, registers 805, 806, and 80.
7 and a comparator module 808. Each tint determination circuit determines the possibility that a specific document exists in the document with 2 bits. A maximum value circuit 809 outputs the maximum value of the determination results (output values) of the tint determination circuits 803-1 to 803-8. That is, the maximum value circuit 809 outputs the determination result as the determination signal H for the original document that is most likely to be present in the read original image image among the eight types of specific original documents in one reading.

Reference numeral 810 denotes a frequency dividing circuit, which will be described later, but generates and outputs SEL and CLK 'by the input CLK and HSYNC. [Timing Chart] FIG. 9 is a circuit diagram showing a configuration of a thinning circuit according to the second embodiment, FIG. 10 is a circuit diagram showing a configuration of a frequency dividing circuit according to the second embodiment, and FIG. 4 is a timing chart of signals in the main scanning direction according to the embodiment of FIG.

The VSYNC signal is a sub-scanning section signal,
It is a signal indicating the image output section of the sub-scan. HSYNC is a main scanning synchronization signal and is a signal for synchronizing the start of main scanning. CLK is an image transfer clock, and is a basic clock for various image processes in this embodiment.

On the other hand, CLK 'is the CLK signal divided by 1/4 and serves as a basic clock in the decision circuit 704. The SEL signal is a timing signal used in the thinning circuit 801 described later. CLK 'and SEL are generated by the frequency dividing circuit 810 shown in FIG.

The frequency dividing circuit 810 is composed of an inverter 921, a 2-bit counter 922, an inverter 923, and an AND gate 924, as shown in FIG.
The 2-bit counter 922 is an HS which is a main scanning synchronization signal.
After being cleared (initialized) by the YNC signal, CLK
The signal is counted, and the count value is output with 2 bits (D0, D1). The upper bit D1 is output as the CLK 'signal, and the logical product of the inverted signal of the lower bit D0 and the upper bit D1 is output as the SEL signal.

As shown in FIG. 9, the thinning circuit 801 is a flip-flop 9 for holding data by the CLK signal.
01,902,903 and 907,908,909,
Selectors 904, 905, 906, flip-flops 910, 911, 912 for holding data by CLK 'signal
It is composed of According to this thinning-out circuit 801, FIG.
As shown in FIG. 2, the R (or G, B) signal transferred by the CLK signal is thinned out at a rate of 1/4, and R '(or G', B ') synchronized with CLK' is taken. You can get a signal. [Integrator] FIG. 11 is a block diagram showing the configuration of the integrator 804 according to the second embodiment, and FIGS.
FIG. 6 is a diagram showing inputs and outputs of an integrator 804 according to the embodiment of FIG.

In FIG. 11, 1001 and 1005
Is a flip-flop that holds data at the rising timing of the CLK 'signal. Reference numeral 1002 denotes a multiplier which inputs an 8-bit 2-input signal (A, B) and outputs an 8-bit signal (A × B / 255) as a multiplication result. 1003 is also a multiplier, which inputs a 1-bit input signal (A) and an 8-bit input signal (B), and outputs an 8-bit output signal (A × B) as a multiplication result.

An adder 1004 inputs an 8-bit 2-input signal (A, B) and outputs an 8-bit signal (A + B) as an addition result.

[0050] As a result, in the present integrator, the output signal y _i of 8 bits for binary input signal x _i is expressed by the following formula (1). That is, y _i = (α / 255) · y _i-1 + β · x _i-1 (1) Here, α and β are preset constants, and the various characteristics of the integrator are determined by the magnitude of these values. For example, when α = 247 and β = 8, the input x _i−1 as shown in FIG.
The output y _i as shown in is output.

Here, inputs such as 1201 and 1202 are "1" even though the surroundings are almost "0", and surroundings are almost "1" like the point 1203. Nevertheless, the input that seems to be “0” is noise.
Is considered to be. This is processed by the integrator, and appropriate threshold values such as R1, R2, and R3 are set in the registers 805, 806, and 807 of FIG. 8, and the output y _i of the integrator is quaternized by this. It is possible to remove noise. [Comparator Module] FIG. 15 is a block diagram showing the configuration of the comparator module 808 according to the second embodiment. In the figure, 1301, 1302 and 1303 are comparators,
1304 is an inverter, 1305 is an AND gate, 13
Reference numerals 06 and 1307 denote OR gates, respectively. The thresholds R1 (see FIG. 8), R2 (see FIG. 8) in the register 805, and R3 (see FIG. 8) in the register 807 are preset. R1>R2> R
There is a relationship of 3.

With the above configuration, as a result, the determination result is quantized into 2 bits and output. That is, when R1 <(input), 11 (binary) is output, when R2 <(input) ≦ R1, 10 (binary) is output, and when R3 <(input) ≦ R2, 01 (binary) is output. Binary) is output, and if (input) ≦ R3, 00 (binary) is output. [Pattern Adding Circuit] FIG. 16 is a block diagram showing the structure of the pattern adding circuit 701 according to the second embodiment. The input signal of 8-bit width of the AND gate 309 is different from the block diagram (FIG. 3) of the pattern adding circuit 109 of the first embodiment. In FIG. 16, reference numeral 1405 is a 4 to 1 selector, and 1401, 1402, 1403 and 1404 are registers. Registers 1401, 1402, 1403, 1
The values P1, P2, P3, and P4 are held in advance in 404, and any one of P1 to P4 is selected according to the pattern level selection signal PS designated by the CPU 703, and addition is performed via the AND gate 309. A pattern is added to the input signal V by the device 310 and V'is output. Therefore, CNO = 2, that is, the pattern held in the LUT 303 while being currently printed in yellow is repeatedly read and added to the signal V to be output.

Here, it is set such that P <P2 <P3 <P4, and the selector 1405 has: when s = 00 (binary number), Y = A, and when s = 01 (binary number), Y =
When B and s = 10 (binary number), Y = C and s = 11 (2
When PS = 00 (binary), V '= V + P1, P because P is set so that Y = D
When S = 01 (binary number), V ′ = V + P2, PS = 1
When 0 (binary number), V '= V + P3, PS = 11 (2
The pattern is added so that V ′ = V + P4 in the case of a decimal number.

By varying the level of the pattern to be added according to the possibility that a specific original document exists in the input image, the pattern is recorded on a normal copy so that it is almost invisible to human eyes. . In particular, by making the level variable, the higher the possibility that a specific document exists,
A pattern can be added clearly. [Flowchart] FIG. 17 shows the CPU 70 of the second embodiment.
3 is a flowchart illustrating a setting procedure of a pattern level selection signal PS in the control by 3).

First, immediately after the start of copying, in step S1501, the pattern level selection signal PS is set to "0". Next, in step S1502, the current judgment level H and the value of PS are compared, and if H is larger, the value of H is set in PS in step S1503. Otherwise, the process returns to step S1502. That is, the maximum value from the copy start to the present is set in PS according to the history of the determination signal H.

As described above, according to the second embodiment, in the case of a document which may be copied, the modulation amount of the image signal can be reduced, so that it can be made even more inconspicuous. . <Third Embodiment> Next, a third embodiment will be described.

In this embodiment, when a reproduction image is generated by superimposing the additional pattern on the original image, a dot array in which the additional pattern is dispersed is used. In the third embodiment as well, the configuration of the entire copying machine is the same as that of the first embodiment described with reference to FIGS.
Since it is the same as, the description will be omitted. [Pattern Addition Circuit] First, the method of the addition pattern of this embodiment will be described.

FIG. 20 is a diagram showing an additional pattern according to the third embodiment, FIG. 21 is a diagram for explaining an add-on line according to the third embodiment, and FIG. 22 is a unit for an additional pattern according to the third embodiment. FIG. 23 is a diagram for explaining an example of adding an additional pattern according to the third embodiment, and FIG. 24 is a diagram for explaining a method for adding a mark according to the third embodiment.

As shown in FIG. 20, the additional pattern of this embodiment has dots as a unit by modulating (for example, + α) the image signals of 16 pixels of 4 × 4 pixels in total. This is because the printer unit of the color copying machine performs, for example, 200 line processing in the image area, and it may be difficult to read by adding a pattern on a pixel-by-pixel basis. As shown in FIG. 21, an arrangement in which these dots are arranged at regular intervals of 8 mm (128 pixels) in the main scanning direction is called an add-on line. The add-on lines are arranged at equal intervals in the sub-scanning direction at intervals of 1 mm (16 pixels). As will be described later, one add-on line represents 4-bit information, and eight add-on lines represent all additional information (32 bits), which is repeated in the sub-scanning direction (see FIG. 2).
2). As shown in FIG. 23, information is added to each add-on line by the phase difference of the dot position when compared with the add-on line just before that. However, in order to prevent the dots from approaching and becoming conspicuous, do not hit near the dot of the previous add-on line. Also, 8 add-on lines (Line0 to Line7) that represent all additional information
A dot is added to the right of each dot in the first add-on line (Line 0) and the fourth add-on line (Line 3). As shown in FIG. 24, in Line 0, a dot is added 1 mm to the right of the original dot position, and in Line 3, a dot is added 2 mm to the right. This is a mark for clarifying which part of all the additional information each add-online represents. If the add-on line to add the mark is one, the upper and lower sides in the sub-scanning direction cannot be determined from the copy, so the dot of the mark is added to the two add-on lines. Here, the pattern to be added is added only with the yellow toner so that it is difficult for the human eye to identify, but this is because the human eye has a weak identification ability with respect to the pattern drawn with the yellow toner. Is used.

Next, the pattern adding circuit of this embodiment will be described.

18 and 19 are block diagrams showing the structure of the pattern adding circuit according to the third embodiment. In the figure, 1319 is a sub-scanning counter, and 1314 is a main-scanning counter. Here, the sub-scanning counter 1319 sends the main-scanning synchronization signal HSYNC to the main-scanning counter 1314.
Then, the pixel synchronization signal CLK has a 7-bit width, that is, 1
It counts repeatedly in 28 cycles. AND gate 132
The output of 0 is bits 2 and 3 of the sub-scanning counter 1319.
Is high when both are high. That is, the sub-scanning direction 16
It becomes H for 4 lines for each line. This is the enable signal for the add-on line. Also, this AND gate 13
20 and the upper 3 bits of the sub-scanning counter 1319 are input to the gates 1322 and 1321.
NE0 and LINE3 are generated. This is a signal which becomes H at the time of Line 0 and Line 3 in the add-on line. On the other hand, the main scan counter 1314 is loaded with an initial value by HSYNC. Since the AND gate 1315 receives the upper 5 bits of the main scanning counter 1314 as an input, its output becomes H for 4 pixels for every 128 pixels. This is the dot enable signal. Also, the gate 13
Reference numerals 16 and 1317 denote the upper 5 bits of the main scanning counter 1314 and the outputs LINE0 and L of the gates 1322 and 1321.
INE3 and the input, each of the online Li
An enable signal for dots of the marks ne0 and Line3 is generated. These dot and mark enable signals are combined by the OR gate 1318. This OR
The output of the gate 1318 is high even if it is not online.
Therefore, the AND gate 1324 is set to L except the add-on line. This AND gate 13
The output of 24 is synchronized with the CLK signal in the flip-flop 1325, and 2 in the AND gate 1327.
After being ANDed with both CNO signals "0" and "1" of the bit, it is sent to AND gate 1329. This is a valid signal only when CNO = 2, that is, currently being printed in yellow. In the AND circuit 1329,
Register 1 only when the output of AND gate 1327 is H
Through the value of 328, zero is output when the output of the AND gate 1327 is L. The output of the AND circuit 1329 is input to the adder circuit 1330 and added with the image signal V to obtain the output V ′. The adder circuit 1330 is an 8-bit adder, which outputs zero when the result is less than 0 and outputs 255 when the result exceeds 255.

The load value of the main scanning counter 1314 is generated as follows. First, the flip-flop 1313 and the counter 1309 are reset by VSYNC. Therefore, in the first add-on line, zero is set as the initial value of the main scanning counter 1314. Here, the clock input ADL of the flip-flop 1313
IN is an add-on enable signal AND
The output of the gate 1320 is set to H by the flip-flop 1323.
This signal is synchronized with SYNC. Flip flop 1
The output of 313 is input to the load value of the main scanning counter 1314 and also to the adder 1312. The adder 1312 adds a constant value of 8. This is an offset value for preventing the dot from being hit in the immediate vicinity of the dot position of the immediately preceding add-on line. Then, the output of the adder 1312 is input to the adder 1311. The output of the selector 1310 is connected to the other input of the adder 1311. This selector 1310 selects one of the registers 1301 to 1308 in which the value of each of the eight add-on lines is set. The select signal of the selector 1310 is the counter 130.
The counter 1309 is initially VSY.
Since it is reset by NC, register 1301
Is selected. Then, the value of the counter 1309 is incremented by 1 by the rise of the signal ADLIN, and the selector 131
0 outputs the value of the register 1302. The value and the output of the adder 1312 are added by the adder 1311. Then, it is latched by the flip-flop 1313 at the fall of the signal ADLIN and used as the initial value of the main scanning counter 1314. After that, the initial value of the main scanning counter is set while the constant 8 and the register value of the next add-on line are added for each add-on line. [Copy Result] FIG. 25 is a diagram showing an example of a copy result when a general pattern is added. In the figure, 19
A unit pattern is indicated by 01. The entire pattern is formed by repeating such a unit pattern that is collected in a small grid.

FIG. 26 is a diagram showing an example of the copy result according to the third embodiment. In this embodiment, since the dot pattern is dispersed, it is clearly inconspicuous. In addition,
The patterns shown in FIGS. 25 and 26 are machine-specific serial numbers or encoding serial numbers,
If the copy is verified, the copy device can be limited.

As described above, it is possible to make the additional pattern less conspicuous by dispersing the dots as shown in FIG. 26, rather than repeating the small unit pattern as shown in FIG. <Fourth Embodiment> Now, the above-described third embodiment is referred to as the second embodiment.
It may be applied to the image scanner portion of FIG. 7 described in the embodiment.

Therefore, the pattern adding circuit will be described in detail. [Pattern Adding Circuit] FIG. 27 is a block diagram showing the structure of the pattern adding circuit according to the fourth embodiment. Block diagrams of the pattern adding circuit of the third embodiment (FIGS. 18 and 1).
9) is the same as the input signal of 8-bit width of the AND gate 329, and since it is the same, the description of the same configuration and the illustration of the portion corresponding to FIG. 19 are omitted.

In FIG. 27, 1705 is a 4 to 1 selector, and 1701, 1702, 1703 and 1704 are registers. Registers 1701, 1702, 170
3, 1704 hold values P1, P2, P3, P4 in advance, and any one of P1 to P4 is selected according to the pattern level selection signal PS designated by the CPU, and the AND gate is selected. After 1329, adder 1
A pattern is added to the input signal V by 330,
V'is output.

Here, the operation of the selector 1705 according to the relationship among P1, P2, P3, and P4 is the same as that of the second embodiment, and therefore its explanation is omitted.

Also in the fourth embodiment, in the input image,
By varying the level of the pattern to be added according to the possibility of the existence of the specific original, the pattern is almost invisible to human eyes in a normal copy, and the specific original is highly likely to exist. I see, the pattern is added clearly. <Fifth Embodiment> The present invention is not limited to the above-described first to fourth embodiments. For example, as the specific pattern to be added, the manufacturing number peculiar to the device or a coded version thereof is added, but it is not limited to this as long as it is information for limiting the device. For example, it may be information for limiting the device such as the manufacturing date of the device, the lot number of the device, and the version of the device. <Sixth Embodiment> In the first to fifth embodiments described above, the copying apparatus is limited, but the present invention is not limited to this, and the copying person is limited. It may be. For example, a device that requires insertion of an ID (identification) card for limiting the user or a device that requires input of an ID number is already known when using the device. In the device, the recognized ID number or the encoded ID number may be added as a specific pattern. <Seventh Embodiment> In the first to fifth embodiments described above, the copying apparatus is limited, and in the sixth embodiment, the person is specified. The present invention is not limited to this, and the copied date or the encoded date may be added as the specific pattern.

Further, it is needless to say that, of the first to seventh embodiments, an embodiment in which two or more are combined is possible.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0071]

According to the present invention as described above, according to the present invention, image
Information that identifies the device or person who performed the image output should be conspicuous.
Can be added to the image like any other, and the added information
Has the effect of being able to identify with certainty .

[Brief description of drawings]

FIG. 1 is an image scanner unit 201 according to a first embodiment.
3 is a block diagram showing the configuration of FIG.

FIG. 2 is a side sectional view showing the internal structure of the copying machine according to the first embodiment of the present invention.

FIG. 3 is a pattern adding circuit 1309 according to the first embodiment.
3 is a block diagram showing the configuration of FIG.

FIG. 4 is a diagram illustrating an additional pattern according to the first embodiment.

FIG. 5 is a diagram showing an example of a copy result according to the first embodiment.

FIG. 6 is a diagram for explaining the effect of the first embodiment.

FIG. 7 is a block diagram showing a configuration of an image scanner unit 201 according to a second embodiment.

FIG. 8 is a block diagram showing a configuration of a determination circuit 704 according to a second embodiment.

FIG. 9 is a circuit diagram showing a configuration of a thinning circuit according to a second embodiment.

FIG. 10 is a circuit diagram showing a configuration of a frequency dividing circuit according to a second embodiment.

FIG. 11 is a block diagram showing the configuration of an integrator 804 according to the second embodiment.

FIG. 12 is a timing chart of signals in the main scanning direction according to the second embodiment.

[Fig. 13]

FIG. 14 is a diagram showing inputs and outputs of an integrator 804 according to the second embodiment.

FIG. 15 shows a comparator module 808 according to the second embodiment.
3 is a block diagram showing the configuration of FIG.

FIG. 16 is a pattern adding circuit 701 according to the second embodiment.
3 is a block diagram showing the configuration of FIG.

FIG. 17 is a flowchart illustrating a setting procedure of a pattern level selection signal PS in the control by the CPU 703 of the second embodiment.

FIG. 18

FIG. 19 is a block diagram showing a configuration of a pattern adding circuit according to a third embodiment.

FIG. 20 is a diagram showing an additional pattern according to the third embodiment.

FIG. 21 is a diagram illustrating add-on lines according to the third embodiment.

FIG. 22 is a diagram illustrating a unit of an additional pattern according to the third embodiment.

FIG. 23 is a diagram illustrating an example of adding an additional pattern according to the third embodiment.

FIG. 24 is a diagram illustrating a method of adding marks according to the third embodiment.

FIG. 25 is a diagram showing an example of a copy result when a general pattern is added.

FIG. 26 is a diagram showing an example of a copy result according to the third embodiment.

FIG. 27 is a block diagram showing a configuration of a pattern adding circuit according to a fourth embodiment.

FIG. 28 is a diagram showing a relationship between a CNO signal and print output according to the first embodiment.

[Explanation of symbols]

101, 102 Delay element 103-105 Log converter 106 Masking / UCR circuit 107 Space filter 108 Density conversion circuit 201 Image scanner section 202 Printer section 203 Original table glass 204 Original 205 Lamp 206-208 Mirror 210-1 to 210-3 CCD sensor 212 Laser driver 213 Semiconductor laser 214 Polygon mirror 215 f-θ lens 216 Mirror 217 Photosensitive drum 218 Rotating developing device 219 Magenta developing section 220 Cyan developing section 221 Yellow developing section 222 Black developing section 223 Transfer drum 224, 225 Paper cassette 226 Fixing unit 228 Unit 301 Sub-scanning direction counter 302 Main-scanning direction counter 303 LUTs 304, 307, 309 AND gate 305 Flip-flop 306 a Butter 308 Register 310 Adder 701 Pattern addition circuit 702 I / O 703 CPU 710 ROM 711 RAM 801 Decimation circuit 802 LUT 803-1 to 803-8 Color determination circuit 804 Integrator 805 to 807 Register 808 Comparator module 809 Maximum value Circuit 810 Dividing circuit 901 to 903, 907 to 912, 1001, 1005
Flip-flops 904 to 906 Selector 922 2 Bit counter 924 AND gates 1002 and 1003 Multiplier 1004 Adders 1301 to 1303 Comparator 1304 Inverters 1306 and 1307 OR gates

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 1/40 H04N 1/40 Z (56) References JP-A 61-285578 (JP, A) JP-A 63-53100 ( JP, A) JP-A-1-316782 (JP, A) JP-A-2-284189 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 1/38 -1/393 B41J 3/00-3/22 G06T 1/00 G03G 21/00

Claims (6)

(57) [Claims] 1. An image processing apparatus for outputting image data respectively corresponding to a plurality of different colors, which is based on the information so as to add information for specifying a device or a person who has performed the image output to the image data. Adjacent to
Density modulation with a phase difference in the main scanning direction between lines
Place controls a plurality of lines arranged dots in the sub-scanning direction at predetermined intervals, the predetermined line of said plural lines is the La
Image data-in corresponding to the control means and is difficult to identify the human eye of the plurality of different colors colors which part controls to include marks to indicate representing the information of said information When processing the image data, the dot data and the mark
The image processing apparatus characterized by comprising adding means for adding click, and output means for outputting the result of addition by said adding means. 2. The image processing apparatus according to claim 1, wherein the second control unit repeatedly controls the arrangement of the dot rows to add a plurality of pieces of information to the image data. 3. The image processing apparatus according to claim 1, wherein the information includes an output date. 4. An image processing method in an image processing apparatus for outputting image data respectively corresponding to a plurality of different colors, wherein information for identifying a device or a person who has output an image is added to the image data. Adjacent based on the above information
Density modulation with a phase difference in the main scanning direction between lines
Place controlled at predetermined intervals a plurality of lines arranged dots in the sub-scanning direction, a predetermined line of said plurality of lines, the
Image data line corresponding to the control process and is difficult to identify the human eye of the plurality of different colors colors which part controls to include marks to indicate representing the information of said information When the image data is processed, the dot data and the marker are added to the image data according to the arrangement control of the control step .
Image processing method characterized by comprising the additional step of adding over click, and an output step of outputting the result of addition by said adding step. 5. The image processing method according to claim 4, wherein the second control step repeatedly controls the arrangement of the dot rows in order to add a plurality of pieces of the information to the image data. 6. The image processing method according to claim 4 , wherein the information includes an output date.