JP3192673B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3192673B2
JP3192673B2 JP07728091A JP7728091A JP3192673B2 JP 3192673 B2 JP3192673 B2 JP 3192673B2 JP 07728091 A JP07728091 A JP 07728091A JP 7728091 A JP7728091 A JP 7728091A JP 3192673 B2 JP3192673 B2 JP 3192673B2
Authority
JP
Japan
Prior art keywords
film
capacitor
polysilicon film
polysilicon
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07728091A
Other languages
Japanese (ja)
Other versions
JPH05110022A (en
Inventor
淳一 宮野
昌義 伊野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP07728091A priority Critical patent/JP3192673B2/en
Publication of JPH05110022A publication Critical patent/JPH05110022A/en
Application granted granted Critical
Publication of JP3192673B2 publication Critical patent/JP3192673B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は半導体素子の製造方法
に係り、詳しくはDRAMセルのように半導体基板上に
キャパシタを形成する方法に関し、特にキャパシタの下
部電極を製造する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a capacitor on a semiconductor substrate such as a DRAM cell, and more particularly, to a method for manufacturing a lower electrode of a capacitor.

【0002】[0002]

【従来の技術】1990年春季応用物理学会 原稿予稿
集 P583 29a−SB−4に開示されるように、
ポリシリコン膜は、非結晶から多結晶に遷移する温度領
域で成膜することにより、膜表面の凹凸が大きくなる。
この温度領域で成膜したポリシリコン膜をDRAMセル
のキャパシタ下部電極に使用することにより、620℃
で成膜した場合に比較し、容量が約30%増加する。
2. Description of the Related Art As disclosed in the 1990 Spring Society of Applied Physics manuscripts, P583 29a-SB-4,
The polysilicon film is formed in a temperature region where the transition from the amorphous state to the polycrystalline state occurs, so that the unevenness of the film surface becomes large.
By using the polysilicon film formed in this temperature region for the lower electrode of the capacitor of the DRAM cell, 620 ° C.
The capacity is increased by about 30% as compared with the case where the film is formed by the above method.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、非結晶
から多結晶に遷移する温度領域で成膜された粗面ポリシ
リコン膜はポーラス(多孔質)な膜(膜として透き間の
ある非常に粗な膜)なので、後洗浄時に下地に対するダ
メージ、更には該ポリシリコン膜のハガレが生じるとい
う問題点がある。すなわち、前記粗面ポリシリコン膜で
キャパシタの下部電極を形成する場合、まず前記粗面ポ
リシリコン膜を成膜し、これにAsをイオン注入し、この
AsをN2アニールで全体に拡散させた後、ポリシリコン膜
をパターニングして下部電極を形成するが、前記N2アニ
ール時、熱処理装置内に侵入した酸素によりポリシリコ
ン膜の表面に50Å程度の酸化膜が形成される。そこ
で、パターニング工程前に、この酸化膜を除去するため
に5%HF(フッ酸)で20〜30秒の後洗浄を行うが、
この時、粗面ポリシリコン膜はポーラス(多孔質)な膜
なのでHFが浸透し、下地の酸化膜がエッチングされてし
まうのである。また、下地の酸化膜がエッチングされる
と、リフトオフにより上層の粗面ポリシリコン膜がハガ
レることになる。
However, a rough-surface polysilicon film formed in a temperature region where a transition is made from amorphous to polycrystalline is a porous (porous) film (a very coarse film having a gap as a film). Therefore, there is a problem in that the underlying film is damaged during the post-cleaning and that the polysilicon film is peeled off. That is, when forming the lower electrode of the capacitor with the rough polysilicon film, first, the rough polysilicon film is formed, and As is ion-implanted into the rough polysilicon film.
After the As is diffused into the whole by N 2 annealing, the polysilicon film is patterned to form a lower electrode. At the time of the N 2 annealing, the surface of the polysilicon film is about 50 ° An oxide film is formed. Therefore, before the patterning step, post-cleaning is performed with 5% HF (hydrofluoric acid) for 20 to 30 seconds to remove the oxide film.
At this time, since the rough polysilicon film is a porous film, HF penetrates and the underlying oxide film is etched. Also, when the underlying oxide film is etched, lift-off causes the upper rough polysilicon film to be peeled off.

【0004】この発明は上記の点に鑑みなされたもの
で、下地に対するダメージ、膜のハガレを防止してキャ
パシタ容量を大きくとれるキャパシタ下部電極を形成す
ることができる半導体素子の製造方法を提供することを
目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a method of manufacturing a semiconductor device capable of forming a capacitor lower electrode capable of increasing a capacitor capacity by preventing damage to a base and peeling of a film. With the goal.

【0005】[0005]

【課題を解決するための手段】この発明では、表面の凹
凸が大きい粗面ポリシリコン膜と、膜質が緻密なシリコ
ン膜(透き間のないシリコン膜)とを任意の順序で半導
体基板上に積層して形成し、この2層からキャパシタの
下部電極を形成する。
According to the present invention, a rough-surfaced polysilicon film having large surface irregularities and a silicon film having a dense film quality (a silicon film having no gap) are laminated on a semiconductor substrate in an arbitrary order. The lower electrode of the capacitor is formed from these two layers.

【0006】[0006]

【作用】上記この発明においては、後洗浄時の下地に対
するHFの浸透が、膜質が緻密なシリコン膜により防止さ
れる。したがって、下地のエッチング、その結果として
の2層膜のハガレが防止される。また、粗面ポリシリコ
ン膜が上層に位置する場合は該粗面ポリシリコン膜の表
面の凹凸により、一方膜質が緻密なシリコン膜が上層に
位置する場合は、下層の前記粗面ポリシリコン膜の表面
の凹凸の影響を受けての前記緻密なシリコン膜の表面の
凹凸により、キャパシタ下部電極の表面積を大きく得る
ことができる。したがって、キャパシタ容量の増大を図
ることができる。
According to the present invention, the penetration of HF into the substrate during the post-cleaning is prevented by the silicon film having a dense film quality. Therefore, etching of the base and, as a result, peeling of the two-layer film are prevented. When the rough polysilicon film is located in the upper layer, the roughness of the surface of the rough polysilicon film is increased. On the other hand, when the dense silicon film is located in the upper layer, the lower polysilicon film is formed of the lower layer. The surface area of the capacitor lower electrode can be increased by the unevenness of the surface of the dense silicon film affected by the unevenness of the surface. Therefore, the capacitance of the capacitor can be increased.

【0007】[0007]

【実施例】以下この発明の実施例を図面を参照して説明
する。図1はこの発明の第1の実施例を示す断面図であ
る。この図において、1はシリコン基板であり、まずこ
の基板1の表面に温度950℃の酸化により酸化膜2を
1000Å成膜する。次に、その酸化膜2上に、100
%SiH4ガスを原料ガスにした減圧CVD法にて、圧力0.
2Torr, 温度570℃で膜表面の凹凸の大きな粗なポリ
シリコン膜3を1000Å、キャパシタ下部電極下層膜
として成膜する。続いてその上に、同じく100%SiH4
ガスを原料ガスにした減圧CVD法にて、圧力0.2Tor
r, 温度620℃で膜質の緻密なポリシリコン膜4を5
00Å、キャパシタ下部電極上層膜として成膜する。そ
の後、ポリシリコン膜3,4にn型不純物をイオン注入
し、さらにそのn型不純物がポリシリコン膜3,4の全
体に拡散するようにN2中で熱処理する。この時、熱処理
装置内に侵入した酸素によりポリシリコン膜4の表面に
50Å程度の酸化膜が形成される。そこで次に5%HFで
20〜30秒の後洗浄を行い、前記酸化膜を除去する。
この時、ポリシリコン膜3が透き間のある非常に粗な膜
であっても、この第1の実施例では上層の膜質が緻密な
ポリシリコン膜4によってHFの酸化膜2への浸透が防止
され、該酸化膜2のエッチングが防止され、該エッチン
グに基づくポリシリコン膜3,4のハガレも防止され
る。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. In this figure, reference numeral 1 denotes a silicon substrate. First, an oxide film 2 is formed on the surface of the substrate 1 by oxidation at a temperature of 950 ° C. at 1000 °. Next, on the oxide film 2, 100
% SiH 4 gas as the source gas under reduced pressure CVD method.
At 2 Torr and at a temperature of 570 ° C., a rough polysilicon film 3 having large irregularities on the film surface is formed at 1000 ° as a lower layer film of a capacitor lower electrode. Then, on top of that, 100% SiH 4
Pressure of 0.2 Torr by low pressure CVD method using gas as raw material gas
r, at a temperature of 620 ° C., 5
At 00 °, a film is formed as an upper layer film of the capacitor lower electrode. Thereafter, an n-type impurity is ion-implanted into the polysilicon films 3 and 4, and a heat treatment is performed in N 2 so that the n-type impurity is diffused into the entire polysilicon films 3 and 4. At this time, an oxygen film of about 50 ° is formed on the surface of the polysilicon film 4 due to oxygen that has entered the heat treatment apparatus. Then, post-cleaning is performed for 20 to 30 seconds with 5% HF to remove the oxide film.
At this time, even if the polysilicon film 3 is a very coarse film having a gap, in the first embodiment, the upper layer film quality of the polysilicon film 4 prevents the penetration of HF into the oxide film 2. This prevents the oxide film 2 from being etched, and prevents the polysilicon films 3 and 4 from peeling off due to the etching.

【0008】次に、ポリシリコン膜3,4をパターニン
グしてキャパシタの2層構造の下部電極を形成する。そ
の後、該下部電極の表面を含む全面にキャパシタ絶縁膜
として、SiH2Cl2 ガスとNH3 ガスを原料ガスに用いた減
圧CVD法にて、圧力0.15Torr,温度650℃でシリ
コン窒化膜5を形成する。さらにその上にキャパシタ上
部電極膜として、SiH4ガスを原料ガスとする減圧CVD
法にて、圧力0.2Torr,温度620℃でポリシリコン膜
6を1000Å成膜する。そして、そのポリシリコン膜
6にn型不純物をイオン注入し、該不純物が全体に拡散
するように熱処理した後、該ポリシリコン膜6をパター
ニングすることによりキャパシタの上部電極を形成す
る。さらにその上部電極と同一パターンにシリコン窒化
膜5もパターニングする。以上でキャパシタが完成す
る。このキャパシタにおいては、ポリシリコン膜3の表
面の凹凸の影響を受けてポリシリコン膜4の表面(2層
構造下部電極の表面)が凹凸となり、該下部電極の表面
積を大きくとることができるので、キャパシタ容量の増
大を図れる。
Next, the polysilicon films 3 and 4 are patterned to form a lower electrode having a two-layer structure of the capacitor. Thereafter, a silicon nitride film 5 was formed on the entire surface including the surface of the lower electrode as a capacitor insulating film at a pressure of 0.15 Torr and a temperature of 650 ° C. by a reduced pressure CVD method using SiH 2 Cl 2 gas and NH 3 gas as source gases. To form Further thereon, as a capacitor upper electrode film, reduced pressure CVD using SiH 4 gas as a source gas.
The polysilicon film 6 is formed at a pressure of 0.2 Torr and a temperature of 620 ° C. by 1000 °. Then, an n-type impurity is ion-implanted into the polysilicon film 6, and a heat treatment is performed so that the impurity is diffused all over. Then, the polysilicon film 6 is patterned to form an upper electrode of the capacitor. Further, the silicon nitride film 5 is also patterned in the same pattern as the upper electrode. Thus, the capacitor is completed. In this capacitor, the surface of the polysilicon film 4 (the surface of the lower electrode having the two-layer structure) becomes uneven due to the influence of the unevenness of the surface of the polysilicon film 3, and the surface area of the lower electrode can be increased. The capacity of the capacitor can be increased.

【0009】図2はこの発明の第2の実施例を示す。こ
の第2の実施例では、膜表面の凹凸の大きな粗なポリシ
リコン膜3と、膜質が緻密なポリシリコン膜4の形成順
序を第1の実施例と逆にしたものであり、酸化膜2上に
まずキャパシタ下部電極下層膜として膜質が緻密なポリ
シリコン膜4を形成し、その上にキャパシタ下部電極上
層膜として粗面ポリシリコン膜3を形成する。
FIG. 2 shows a second embodiment of the present invention. In the second embodiment, the order of forming the coarse polysilicon film 3 having large unevenness on the film surface and the polysilicon film 4 having the dense film quality are reversed from those of the first embodiment. First, a dense polysilicon film 4 is formed as a capacitor lower electrode lower layer film, and a rough polysilicon film 3 is formed thereon as a capacitor lower electrode upper layer film.

【0010】このようにしても、ポリシリコン膜3の表
面に形成された薄い酸化膜を5%HFで除去する際の酸化
膜2へのHFの浸透は膜質の緻密なポリシリコン膜4で防
止でき、かつ粗面ポリシリコン膜3の表面の凹凸でキャ
パシタ下部電極の表面積を大きくとることができる。こ
の第2の実施例において、ポリシリコン膜3,4の形成
順序以外はすべて第1の実施例と同一である。
[0010] Even in this case, the penetration of HF into the oxide film 2 when the thin oxide film formed on the surface of the polysilicon film 3 is removed with 5% HF is prevented by the dense polysilicon film 4. In addition, the surface area of the capacitor lower electrode can be increased by the unevenness of the surface of the rough polysilicon film 3. The second embodiment is the same as the first embodiment except for the order in which the polysilicon films 3 and 4 are formed.

【0011】なお、上記第1,第2の実施例において
は、膜質が緻密なシリコン膜として、100%SiH4ガス
を原料ガスとした減圧CVD法にて、圧力0.2Torr,温
度620℃でポリシリコン膜を500Å成膜したが、ア
モルファスシリコン膜を形成してもよい。アモルファス
シリコン膜の場合は、一例としては、上記と同一ガス、
同一CVD法により圧力0.2Torr,温度500℃でアモ
ルファスシリコン膜を500Å成膜させる。
In the first and second embodiments, a dense silicon film is formed at a pressure of 0.2 Torr and a temperature of 620 ° C. by a low pressure CVD method using 100% SiH 4 gas as a source gas. Although the polysilicon film is formed at 500 °, an amorphous silicon film may be formed. In the case of an amorphous silicon film, for example, the same gas as above,
An amorphous silicon film is formed at a pressure of 0.2 Torr and at a temperature of 500 ° C. by the same CVD method at a temperature of 500 °.

【0012】[0012]

【発明の効果】以上詳細に説明したようにこの発明の製
造方法によれば、表面の凹凸が大きい粗面ポリシリコン
膜と膜質が緻密なシリコン膜の2層でキャパシタの下部
電極を形成するようにしたので、後洗浄時における下地
に対するダメージ、膜のハガレを防止でき、かつキャパ
シタ容量の増加を図ることができる。
As described above in detail, according to the manufacturing method of the present invention, the lower electrode of the capacitor is formed by the two layers of the rough polysilicon film having large surface irregularities and the dense silicon film. Accordingly, it is possible to prevent damage to the base and peeling of the film during the post-cleaning, and increase the capacitance of the capacitor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の半導体素子の製造方法の第1の実施
例を示す断面図である。
FIG. 1 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

【図2】この発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化膜 3 ポリシリコン膜 4 ポリシリコン膜 5 シリコン窒化膜 6 ポリシリコン膜 Reference Signs List 1 silicon substrate 2 oxide film 3 polysilicon film 4 polysilicon film 5 silicon nitride film 6 polysilicon film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭64−42161(JP,A) 特開 平2−1154(JP,A) 特開 平3−263370(JP,A) 特開 平3−272165(JP,A) 特開 平4−280463(JP,A) 特開 平5−67730(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-64-42161 (JP, A) JP-A 2-1154 (JP, A) JP-A 3-263370 (JP, A) JP-A 3- 272165 (JP, A) JP-A-4-280463 (JP, A) JP-A-5-67730 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 27/108 H01L 21 / 822 H01L 21/8242 H01L 27/04

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上に表面の凹凸が大きい粗面
ポリシリコン膜と、膜質が緻密なシリコン膜とを任意の
順序で積層して形成し、その後、HFの洗浄を行ない、
その後、キャパシタ絶縁膜を形成し、前記キャパシタ絶
縁膜上に上部電極を形成することを特徴とする半導体素
子の製造方法。
1. A semiconductor device comprising: a semiconductor substrate having a rough surface polysilicon film having large surface irregularities and a dense silicon film laminated on the semiconductor substrate in an arbitrary order;
Thereafter, a capacitor insulating film is formed, and an upper electrode is formed on the capacitor insulating film.
JP07728091A 1991-03-18 1991-03-18 Method for manufacturing semiconductor device Expired - Fee Related JP3192673B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07728091A JP3192673B2 (en) 1991-03-18 1991-03-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07728091A JP3192673B2 (en) 1991-03-18 1991-03-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05110022A JPH05110022A (en) 1993-04-30
JP3192673B2 true JP3192673B2 (en) 2001-07-30

Family

ID=13629457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07728091A Expired - Fee Related JP3192673B2 (en) 1991-03-18 1991-03-18 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3192673B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620958A (en) * 1992-04-10 1994-01-28 Internatl Business Mach Corp <Ibm> Formation of rough silicon surface and its application
KR100365935B1 (en) * 1995-12-20 2003-03-15 주식회사 하이닉스반도체 Method for forming storage node in semiconductor device
KR100235938B1 (en) * 1996-06-24 1999-12-15 김영환 A fabrication method of semicircle silicon
TW385544B (en) * 1998-03-02 2000-03-21 Samsung Electronics Co Ltd Apparatus for manufacturing semiconductor device, and method of manufacturing capacitor of semiconductor device thereby
JP2010153893A (en) * 2002-01-29 2010-07-08 Renesas Technology Corp Semiconductor memory

Also Published As

Publication number Publication date
JPH05110022A (en) 1993-04-30

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