JP3191803B2 - Signal processing apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DCT (Disc
The present invention relates to a signal processing apparatus and method for a digital VTR that encodes and records a video signal with high efficiency by rete cosine transfer (transform).

[0002]

2. Description of the Related Art A digital VTR for digitizing a video signal and recording it on a magnetic tape has been developed. Since the transmission band of the digital video signal is very wide, it is difficult to record the digital signal directly on a magnetic tape. Therefore, such a digital VTR
In this technology, a digital video signal is band-compressed to a band that can be recorded on a magnetic tape by using a high efficiency coding technique.
As one of such high-efficiency coding processing techniques, DC
A T-transform has been proposed.

In a digital VTR that performs high-efficiency encoding processing using DCT conversion, for example, a digital video signal in a time domain of a DCT block composed of (8 × 8) pixels is converted into data in a frequency domain by DCT conversion. Since the video signal has a correlation, when the video signal is converted into data in the frequency domain, most of the signal is a low frequency component. Then, a coefficient having a large power is collected at a low frequency, and the power becomes smaller as the frequency increases.

[0004] The data converted into the frequency domain by the DCT transform is further encoded using a variable length code such as a Huffman code, so that the number of bits is reduced. Then, in order to deal with errors, when data is recorded on a magnetic tape, an error correction encoding process is performed using, for example, a Reed-Solomon code.

[0005]

In such a digital VTR, coefficient data obtained by DCT is quantized and then variable-length coded. When the variable length coding is performed in this manner, the number of data changes for each frame. However, if the number of data is different for each screen (frame), the delimiter does not match between the digital color signal of each frame and the track on the tape, so that it is difficult to perform an editing process or the like. Therefore, by switching a plurality of quantization steps at the time of quantization, the number of data in each frame is made substantially constant. However, when the quantization step is switched so that the number of data becomes constant, for example, in a portion such as the sky in the background, there is little change in the pattern, so that D
The value of the coefficient data of each frequency component by the CT conversion becomes small, and is converted into a small number of bits when the variable length coding is performed. In this case, since the value of the coefficient data of each frequency component by the DCT transform becomes large, a coarse quantization step is selected. Therefore, it has been proposed to perform shuffling such that the time series of coefficient data and the spatial position are uncorrelated in one frame when performing the variable-length encoding process.

In the conventional shuffling processing, attention is paid only to randomly selecting each data in one frame, and no interpolation processing by clogging or scratching of the head is considered at all. That is,
In such a digital VTR, when a clog occurs in the head, a reproduced signal of one channel can hardly be obtained. Also, if there is dust or scratches on a guide or the like that supports the tape, an error occurs continuously in the longitudinal direction of the tape. Performing random shuffling makes it difficult to perform interpolation processing when such a defect occurs.

Therefore, an object of the present invention is to solve the problem even when clogging or scratching occurs in the head.
An object of the present invention is to provide a signal processing device and a signal processing method in which shuffling is performed so that interpolation processing can be easily performed.

[0008]

SUMMARY OF THE INVENTION This invention provides a signal processing apparatus in a digital image, dividing means for dividing the digital image signal input into a plurality of blocks, Digitally
Video signal in the vertical direction.
Divide by the number of racks, divide by integer in the horizontal direction, and
Encoding a dividing means for dividing the sub-area consisting of click, the shuffling means for shuffling in the collect from discrete sub-area has a multiple digital image signal on a block basis, the shuffled digital image signal This is a signal processing device having an encoding unit.

According to the present invention, in a method for processing a digital image signal, an input digital image signal is divided into a plurality of blocks, and the digital image signal is divided into one block in a vertical direction.
Divided by the number of recording tracks of the frame image signal and adjusted in the horizontal direction.
The number divided and is divided into sub-areas comprising a plurality of blocks, and shuffling as collect digital image signal from the discrete sub-area has a multiple in blocks, so as to encode the shuffled digital image signal This is a signal processing method.

[0010]

Since the signals from the two heads are shuffled so that the positions on the screen are different from each other between the two frames, interpolation processing is easy even when clogging or scratching occurs in the heads.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. In the present invention, first, after removing a redundant portion in an input signal and extracting only an effective portion,
By performing high-efficiency coding by T (Discrete Cosine Transform) conversion, data compression is reduced to about 1/9 as a whole. That is, the transmission rate of the input video signal is
For example, 216 MBPS. By removing the redundant portion from this, the transmission rate becomes, for example, 122 MBPS.
Is reduced to Further, the transmission rate is reduced to about 1/5, for example, 25 MBPS, by the high-efficiency coding by the DCT transform.

The DCT transform is an orthogonal transform code.
For example, when data of an (8 × 8) DCT block as shown in FIG. 3 is subjected to DCT conversion, it is converted into frequency domain data as shown in FIG. Here, the X axis is a horizontal frequency component, and the Y axis is a vertical frequency component. On the X axis, the frequency becomes higher toward the right side, and on the Y axis, the frequency becomes higher toward the lower side. Data at the left end of the uppermost row (314.91 data in this example)
Is the DC component data. Since the screen of one frame has a correlation, the level of the DC component becomes a large value and the level of the high-frequency component in the horizontal and vertical directions becomes extremely small when the DCT is performed in this manner. By allocating an appropriate number of bits (variable-length coding) to such DCT-transformed coefficient data according to visual characteristics, the amount of information can be significantly reduced.

FIG. 1 shows the configuration of a recording system of a digital VTR to which the present invention is applied, and FIG. 2 shows the configuration of a reproducing system. In FIG. 1, input terminals 1A, 1B,
1C, for example, a digital luminance signal Y of the NTSC system,
Color difference signals U and V are supplied. The digital luminance signal Y and the color difference signals U and V have a sampling frequency of the luminance signal Y of, for example, 13.5 MHz, a sampling frequency of the color difference signals U and V of, for example, 6.75 MHz, and a quantization bit number of 8 bits. So-called (4: 2: 2)
This is the component signal of the system.

The digital luminance signal Y and the color difference signals U and V are supplied to an effective information extracting circuit 2. The effective information extraction circuit 2 reduces the amount of information by removing redundant components as much as possible from the input video signal and extracting only components necessary as information. That is,
The information amount of the color difference signals U and V is smaller than the information amount of the luminance signal Y, and the accuracy of the color difference signal does not appear remarkably as compared with the luminance signal. Further, it is not necessary to transmit the horizontal synchronization signal and the signal during the horizontal blanking period, and the vertical synchronization signal and the signal during the vertical blanking period as information. Therefore, the effective information extraction circuit 2 thins out the U and V samples of the color difference signal by half. Thereby, as shown in FIG. 5, the number of samples of the color difference signals U and V becomes １ ／ of the number of samples of the luminance signal Y. Further, the vertical synchronization signal and the signal of the vertical blanking period are removed, and as shown in FIG.
Only 480 lines (for 704 lines) are extracted.

In FIG. 1, the output of the valid information extracting circuit 2 is supplied to blocking circuits 3A, 3B and 3C. The blocking circuits 3A, 3B, and 3C form DCT blocks for compressing the amount of information by DCT transform. As shown in FIG. 7, the DCT block is composed of (8 × 8) pixel data of eight pixels in the horizontal direction and eight pixels in the vertical direction. The number of bits of each pixel data is 8 as described above.
Is a bit. DCT transform is performed later in units of this DCT block.

In FIG. 1, the blocking circuits 3A, 3A
The outputs of B and 3C are supplied to the macroblock synthesis circuit 4. The macroblock synthesizing circuit 4 forms a macroblock by collecting pixel data of the luminance signal Y and the color difference signals U and V at the same position.
By configuring such a macroblock, shuffling and interpolation processing can be easily performed.

As described above, in this example, (4: 2:
2) The digital luminance signal Y and the color difference signals U and V of the system are input, and the effective information extraction circuit 2 samples the color difference signal sample by one.
/ 2 has been thinned out. Therefore, the number of pixels of the luminance signal Y is four times the number of pixels of the color difference signals U and V. Therefore, as shown in FIG. 8, one macroblock is configured from four pixel data of a luminance signal and one pixel data of each of the color difference signals U and V at the same position.

In FIG. 1, a macroblock synthesis circuit 4
Is supplied to the shuffling circuit 5. Shuffling is performed by the shuffling circuit 5.

The output of the shuffling circuit 5 is supplied to a DCT conversion circuit 6. The DCT conversion circuit 6 performs DCT conversion for each DCT block. In this example, DC
The data after the T conversion is processed by dividing the data into a DC component and other AC components. This is because, when DCT is performed, the DC component has a large value, and the DC component has the most important value. That is, the DC component after DCT conversion is transmitted as it is. The other components are quantized by the quantizer 8, variable-length coded by the variable-length code encoder 9, and data-compressed.

At this time, data for five macroblocks is temporarily stored in the buffer memory 7, and for example, the quantization step of the quantizer 8 is switched so that the information amount becomes substantially equal in each frame. Then, information of the selected quantization step and additional information such as the range of the transmission area are transmitted together.

That is, the data for five macroblocks obtained by the DCT conversion circuit 6 is stored in the buffer memory 7 and supplied to the quantizer 10. Also, D
The DC data obtained from the CT circuit 6 is sent to the framing and error correction circuit 15 in 9 bits. The quantizer 10 weights each data according to visual characteristics. That is, since the high frequency component is visually inconspicuous, division is performed in a large quantization step, and the low frequency component is divided in a small quantization step. further,
As the quantization steps in the quantizer 10, as shown in FIG. 9, 32 kinds of steps identified by the quantization numbers (0 to 31) are prepared. The area number in FIG. 9 assigns one area to the four data of the DCT block as shown in FIG.

Each DCT obtained by the DCT conversion circuit 6
The data of the block (8 × 8) is divided by the quantizer 10 by a set of quantization steps shown in FIG.
Then, the fractional part of the divided data is
Rounded. When such a rounding process is performed, a truncation process is performed in a hatched area in FIG. 10, and a rounding process is performed in other portions.

For example, if the data as shown in FIG. 11 is obtained by the DCT conversion circuit 6, and QNo = 9 (see FIG. 9) is selected as a set of quantization steps of the quantizer 10, Each data shown in FIG. 11 is divided by the quantization step of each area shown in FIG. 12 to obtain data as shown in FIG. This data is sent to the transmission area determination circuit 11, where the transmission area (H, V) is determined. The transmission area (H, V) indicates a boundary at which data in the horizontal direction and the vertical direction is followed by 0. For example, in the case of FIG. 13, the transmission area is “4” in the horizontal direction and “5” in the vertical direction. For example, when the transmission area (H, V) is (4, 5), the 6-bit (10)
0101) is transmitted.

This data is used as the code amount calculation circuit 12
Sent to The code amount calculation circuit 12 calculates the code amount when performing variable length coding using, for example, a Huffman code while referring to the Huffman table 13 (FIG. 14). When variable-length coding is performed, each coefficient data has the number of bits as shown in FIG. Then, the quantizer selecting circuit 14 determines whether or not the code amount for the five macroblocks in the buffering unit is equal to or smaller than a predetermined amount. This predetermined amount corresponds to the set transmission rate of the digital VTR. If the data amount is not less than the predetermined amount, the set of quantization steps of the quantizer 10 is changed, and the code amount is obtained again. By changing the set of the quantizers 10, the data amount can be reduced to a predetermined amount or less.

When the code amount becomes equal to or less than a predetermined value, the same set of quantization steps as those of the quantizer 10 are applied to the quantizer 8. Then, data for 5 macroblocks is quantized by the quantizer 8 from the buffer memory 7 and supplied to the variable length encoder 9. Then, the variable-length code encoder 9 performs variable-length coding using, for example, a Huffman code. The output of the variable length coding circuit 9 is supplied to a framing and error correction coding circuit 15.

Further, to the framing and error correction encoding circuit 15, the DCT coefficient data is transmitted from the DCT conversion circuit 6, and the transmission area information (H, V) is transmitted from the transmission area determination circuit 11, Information on the selected quantizer is sent from the quantizer selection circuit 14. The framing and error correction encoding circuit 15 converts these data into a frame structure and adds an error correction code.

FIG. 16 shows the structure of each sync block of the frame structure. Each sync block is shown in FIG.
As shown in Fig. 6, it is composed of 90 bytes,
A 2-byte sink 51 is provided. Then, a 4-byte ID 52 is added. Subsequently, the DC data and the variable-coded frequency data are arranged as data 53 of 76 bytes. An 8-byte parity 54 is added to this.

As shown in FIG. 17, a product code in which parity for error correction is added in the horizontal direction and the vertical direction is used in the error correction encoding process. That is, the data is two-dimensionally arranged in (45 × 76). Then, an 8-byte Reed-Solomon code parity C1 is generated and added in the horizontal direction, and a 3-byte Reed-Solomon code parity C2 is generated and added in the vertical direction.

In the case of variable-length code data, if an error occurs in one byte, the delimiter of the variable-length code is not known, and even if no error occurs in subsequent bytes, all subsequent data will be in error. (Propagation error) occurs.

Therefore, in this example, data is arranged in each frame as shown in FIG. That is, at the beginning of the data 53, the block address BA
Is provided. Following this, one macroblock M
B1 (4DCT block of luminance signal and color difference signals U, V
Of each DCT block, which is a total of 6 DCT blocks)
, DC data DC1, DC2, DC3,...
DC5 is arranged. And one macroblock M
The variable-length frequency data AC0, AC1,... Of B1 are arranged in order from low-frequency to high-frequency.

When the data of one macro block MB1 is arranged in one sync block, if there is room in the area of the data 53, the data of the next macro block MB2 is arranged. At this time, the next macro block MB2
2 is arranged from the beginning of the symbol, and FIG.
In the area indicated by the hatching of the symbol Sa in FIG.
Dummy data is inserted. At the same time, the head position of the next macroblock MB2 is recorded in the block address BA.

In the case of DCT conversion, DC data and low frequency data are important, and high frequency data is less important. Read / write of variable length code data
When error correction processing is performed by the Solomon code, if an error occurs in one byte, all subsequent data cannot be reproduced. In this way, data is arranged in order from DC data with high importance and data of low frequency. Then, even if an error occurs in one byte and the subsequent data cannot be reproduced, the possibility of a serious problem is reduced.

Also, since the beginning of the next macroblock coincides with the beginning of the symbol, even if an error has occurred in the previous symbol, the next macroblock is not affected, and the next macroblock is not affected. The data from the block can be played.

In FIG. 1, the output of the framing and error correction circuit coding circuit 15 is a channel encoder 16.
And the recording data is modulated by a predetermined modulation method. The output of the channel encoder 16 is supplied to the heads 18A, 18B via recording amplifiers 17A, 17B, respectively.
Supplied to

FIG. 2 shows the structure of the reproducing system.
In FIG. 2, reproduction signals from the heads 21A and 21B are transmitted through reproduction amplifiers 22A and 22B to the channel decoder 2A.
3 is supplied. The channel decoder 23 performs a demodulation process corresponding to the channel encoder 16 of the recording system. The reproduction signal is demodulated by the channel decoder 16. The output of the channel decoder 23 is TBC (Time
Base Corrector) circuit 24. TBC circuit 2
At 4, the time axis fluctuation component is removed.

The output of the TBC circuit 24 is supplied to a frame decomposition and error correction processing circuit 25. The frame disassembly and error correction circuit 25 performs an error correction process on the reproduced data. From the frame decomposition and error correction circuit 25, data in the frequency domain of the variable-length code, DC data, transmission area information (H, V), information of a set of selected quantization steps (quantization number), and the like are output. The additional information is decomposed.

The variable-length code frequency domain data is supplied to a variable-length decoder 27. Variable length decoder 27
Performs decoding of a Huffman code, for example.
The output of the variable length decoder 27 is supplied to an inverse quantization circuit 28. In the inverse quantization circuit 28, the characteristics of the inverse quantizer are set based on the quantization numbers obtained by performing frame decomposition. The output of the inverse quantizer 28 is supplied to the inverse DCT transform circuit 29.

The inverse DCT conversion circuit 29 converts the data in the frequency domain into the data in the time domain. The output of the inverse DCT transform circuit 29 is supplied to the deshuffling circuit 30.
The deshuffling circuit 30 performs a deshuffling process corresponding to the recording shuffling circuit 5.

The output of the deshuffling circuit 30 is supplied to the distribution circuit 31. In the distribution circuit 31, the data of each DCT block of each component signal Y, U, V is decomposed from the macro block. The data of each DCT block is supplied to the block decomposition circuits 32A, 32B, 32C. The DCT blocks of the component signals Y, U, and V are decomposed by the block decomposing circuits 32A, 32B, and 32C. The block decomposition circuits 32A, 32B, 32C
From the output of each component signal Y in the effective screen,
U and V data are obtained. The data of each of the component signals Y, U, and V in the effective screen is supplied to the information interpolation circuit 33.

The information interpolation circuit 33 performs data interpolation on the color difference signals U and V. Further, information on the horizontal blanking period and the vertical blanking period is added to the data of each of the component signals Y, U, and V. These component signals Y, U, V are output terminals 34A, 34B, 3
Output from 4C.

Next, an embodiment of shuffling to which the present invention is applied will be described. In one embodiment of the present invention, one buffering unit is five macroblocks.

As shown in FIG. 19A, (4) of one frame
The video data of the (5 × (m + 1)) macro block is divided into five in the horizontal direction. This is because the buffering unit is composed of five macro blocks. In addition, 1
The data of the frame is vertically
Divide into k sub-areas. In the case of the NTSC system,
(K = 9). As a result of this division, as shown in FIG. 19B, a (9 × 3 = 27 macroblock) subarea is formed. In the case of the NTSC system, within one frame,
(5 × 10 = 50 sub-areas).

As shown in FIG. 19A, subarea numbers 0 to k are defined for the subareas in each column. The sub area number corresponds to the track number on which one frame of data is recorded. Shuffling is achieved by changing the arrangement of subarea numbers between each column. That is, the distance between sub-areas having the same number between adjacent columns (divided areas) is the maximum (6 sub-areas in this example).
Numbering is performed so that

The 27 macroblocks in each subarea are:
As shown in FIG. 19B, macroblock numbers from 0 to 26 are assigned. When collecting five macroblocks of the buffering unit, the five macroblocks are collected from five positions of (sub area number-macroblock number). For example, (0-0) of the buffering unit BUF0 is a collection of macroblocks of number 0 from the subarea of number 0 in each column.

As described above, the shuffled video data is subjected to DCT conversion, buffering processing, variable-length coding, and the like, and then recorded on a magnetic tape. Recording data corresponding to video data of two consecutive frames is recorded in the track format shown in FIG. The recording order is changed between the track of the odd frame and the track of the even frame. By the above-described shuffling process, errors caused by clogging of one of the two rotary heads, scratching of the tape, and the like can be dispersed, and as a result, error correction becomes easy.

More specifically, in the odd-numbered frames, the sub-area numbers are set from 0 to k for each of the (k + 1) tracks in order from the first track. In each track, macroblock numbers from 0 to 26 are set in order from the bottom in the scanning direction from the bottom to the top of the head. Therefore, A corresponding to one rotating head
Data of an even-numbered sub-area number is recorded on a channel track, and data of an odd-numbered sub-area number is recorded on a B-channel track corresponding to the other rotary head.

In the even-numbered frame, data of the odd-numbered sub-area number is recorded on the track of channel A,
The data of the even-numbered sub-area number is recorded on the track of the channel. Further, regarding the 27 buffering units BU0-BU26 of each track, BU0-B
Macroblock numbers 13 to 26 are arranged in U13, respectively, and macroblock numbers 0 to 12 are arranged in BU14 to BU26, respectively.

In the above-described shuffling, as shown in FIG. 21, when a head clog occurs in a channel of one head, for example, a B channel, data can be effectively interpolated. That is, as shown in FIG.
B-channel data that cannot be reproduced is complementary between odd-numbered frames and even-numbered frames. Therefore, the clogged B-channel data can be interpolated using the A-channel data that has not been clogged (the data of the previous frame).

Further, as shown in FIG. 23, it is assumed that a scratch occurs in the longitudinal direction of the tape, and as a result, the data of the three buffering units BU0, BU1, and BU2 on the lower side of the track becomes an error. Suppose. As shown in FIG. 24, in an odd frame, the macroblock number (0, 1, 2) of each sub area becomes error data. On the other hand, in an even-numbered frame, the macroblock number (1
3, 14, 15) become error data. in this way,
Since the macroblock numbers serving as the error data in the subarea do not overlap, the error data can be interpolated by the data of the macroblock of the subblock at the same position in the previous frame.

[0050]

According to the present invention, the signals from the two heads are shuffled so that the positions on the screen are different from each other between the two frames. Therefore, when clogging occurs in the head or clogging occurs in the head. The interpolation processing is easy even when it occurs or when a scratch occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a recording system of a digital VTR to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a reproduction system of a digital VTR to which the present invention is applied.

FIG. 3 is a schematic drawing used to explain DCT conversion in a digital VTR to which the present invention is applied.

FIG. 4 is a schematic diagram used for describing DCT conversion in a digital VTR to which the present invention is applied.

FIG. 5 is a schematic view illustrating a digital VTR to which the present invention is applied;

FIG. 6 is a schematic view illustrating a digital VTR to which the present invention is applied;

FIG. 7 is a schematic diagram used for describing a DCT block in a digital VTR to which the present invention is applied.

FIG. 8 is a schematic diagram used to explain a macroblock in a digital VTR to which the present invention is applied.

FIG. 9 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 10 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 11 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 12 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 13 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 14 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 15 is a schematic diagram used for describing a quantizer in a digital VTR to which the present invention is applied.

FIG. 16 is a schematic diagram used to describe a frame in a digital VTR to which the present invention has been applied.

FIG. 17 is a schematic diagram used for describing blocks in a digital VTR to which the present invention is applied.

FIG. 18 is a schematic diagram used to describe a frame in a digital VTR to which the present invention is applied.

FIG. 19 is a schematic diagram used for describing an example of shuffling of a digital VTR to which the present invention has been applied.

FIG. 20 is a schematic diagram of a track pattern showing an example of shuffling.

FIG. 21 is a schematic diagram used for describing a one-channel head clog.

FIG. 22 is a schematic diagram illustrating a position of error data when a head clog of one channel occurs.

FIG. 23 is a schematic diagram showing occurrence of a longitudinal error on the tape.

FIG. 24 is a schematic diagram showing the position of error data when an error occurs in the longitudinal direction on the tape.

[Explanation of symbols]

 5 shuffling circuit 6 DCT conversion circuit 15 framing and error correction coding circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-220270 (JP, A) JP-A-4-86195 (JP, A) JP-A 4-139978 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N ^7/ 24-7/68 H04N 5/782-5/783

Claims (8)

(57) [Claims] A signal processing apparatus according to claim 1 digital image, dividing means for dividing the digital image signal inputted to the plurality of blocks, the digital image signal, the vertical frame images
Divide by the number of signal recording tracks, divide by integer in the horizontal direction
Te, dividing means for dividing the sub-area consisting of the plurality of blocks, a shuffling means for shuffling in the collect from discrete above subareas multiple of said digital image signal in the block units, were shuffled A signal processing device having coding means for coding the digital image signal. 2. The signal processing apparatus according to claim 1, wherein the sub-area is configured by dividing the digital image signal into ten parts in a vertical direction and five parts in a horizontal direction. Wherein said shuffling means, the discrete above subareas multiple, among the plurality of blocks constituting the sub-area, wherein performing the shuffling a collection of digital image signals of a predetermined position Item 2. The signal processing device according to item 1. 4. Each of the adjacent horizontal division areas.
Select non-adjacent sub-areas in the vertical
From each of the above sub-areas of the divided area
Record the above macro blocks together on a tape
2. The signal processing device according to claim 1, wherein the signal processing is performed. 5. A method for processing a digital image signal.
The input digital image signal into multiple blocks
Then, the digital image signal is converted into one frame image in the vertical direction.
Divide by the number of signal recording tracks, divide by integer in the horizontal direction
The digital image is divided into a plurality of sub-areas,
Collect signals in block units as described above, and
And encodes the shuffled digital image signal.
Signal processing method. 6. The digital image processing apparatus according to claim 1, wherein the sub-area includes the digital image.
Divide the signal into 10 parts vertically and five parts horizontally
The signal processing method according to claim 5, which is configured. 7. A plurality of predetermined discrete sub-areas.
A) of the plurality of blocks constituting the sub area
Among them, digital image signals at predetermined positions are collected
The signal processing method according to claim 5, wherein shuffling is performed. 8. For each of the adjacent horizontal divided areas.
Select sub-areas that are not vertically adjacent to each other
From each of the above sub-areas of the divided area
Record the above macro blocks together on a tape
The signal processing method according to claim 5, wherein the signal processing is performed.