JP3191410B2 - Method of forming superconducting plug and multilayer wiring layer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a superconducting plug and a multilayer wiring layer in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of design rules for semiconductor devices, contact holes, via holes, through holes, and the like (hereinafter, also collectively referred to as connection holes) have been reduced in size. Generally, a connection hole is formed by providing an opening in an interlayer insulating layer and embedding a metal wiring material in the opening. The wiring material embedded in the opening is called a plug. Further, the wiring material forming the plug is called a plug material. Embedding a conventional metal such as aluminum into the opening by sputtering is becoming difficult due to problems such as coverage of the metal wiring material. Therefore, in recent years, attention has been focused on a selective CVD method using tungsten as a technique for embedding a fine opening. Since the connection holes are formed by the selective CVD method, there is no problem in coverage of tungsten, and a plug made of tungsten can be favorably formed in the opening.

The outline of the selective CVD method using tungsten will be described below with reference to FIG. (A) An element isolation region 12 is formed in a semiconductor substrate 10 by a conventional method. (B) Perform gate oxidation to form a polysilicon layer and WSi ₂
Deposit the layer. Next, the gate oxide film, the polysilicon layer and the WSi ₂ layer are patterned, and the gate oxide film,
A gate electrode region 14 composed of a polysilicon layer and a WSi ₂ layer is formed, and then ion implantation is performed to form an LDD structure, thereby forming a shallow impurity diffusion region 16. (C) Next, an SiO ₂ film is deposited on the entire surface. afterwards,
The SiO ₂ film is etched back to form a sidewall 18 on the side of the gate electrode region (see FIG. 6A). Next, ion implantation is performed to form the source / drain regions 24. (D) Then, after depositing the interlayer insulating layer 26, an activation annealing process is performed. Then, an opening 28 is formed by patterning the interlayer insulating layer (see FIG. 6B). (E) Next, tungsten 50 is deposited only on the opening 28 by the selective tungsten CVD method to complete a plug made of tungsten. (F) Metal wiring layer (for example, Al-1% Si / Ti / T
(iON / Ti structure). Next, resist patterning is performed, and the metal wiring portion 52 is formed by dry etching.
Is formed (see FIG. 6C).

[0004]

When the resistance value of the connection hole formed by the selective tungsten CVD method as described above is examined, it is about 10 .mu..OMEGA.cm, and the resistance value of the connection hole formed from the aluminum-based wiring material. There is a problem that it is about three times larger. In a semiconductor device having a rule of 0.35 μm or later, if the degree of integration of semiconductor elements increases in the future,
About 10 ⁹ to 10 ¹⁰ or more connection holes are formed in one semiconductor device. Therefore, the voltage drop at the connection hole cannot be ignored, and it is necessary to reduce the resistance of the plug material.

In order to reduce the electric resistance of the connection hole, Cu
O _X based material have been studied. In recent studies of high-temperature superconductivity, it has been suggested that CuO _X itself is superconducting material. In other words, Ba-Y-CuO _X
In the ceramic systems such as, the area at which the resistance becomes zero, i.e., the portion in which a current flows is considered current is dominant flows portion along the CuO _X plane.

[0006] In order to reduce the electrical resistance of the connection hole, the superconductor devices using plug material made of superconducting material,
For example, it is disclosed in JP-A-63-275144.

[0007] The superconductor device described in this publication is a superconductor device.
It has a multilayer structure of copper, gold, platinum, or a material containing these as a main component in close contact with a conductive material, and a heat-resistant metal material in close contact with the material or a compound material of the metal and a material constituting a substrate. The heat-resistant metal and copper, gold, or platinum are formed by a sputtering method. Materials that should exhibit superconductivity are (A _1-X
Consisting B _X) Cu _Z O _W. Then, a material to exhibit superconductivity is formed into a thin film by a sputtering method or a CVD method. The formed superconducting thin film was formed at 400 ° C. (1
30 hours, for example, 10 hours).
It becomes conductive .

In the method of manufacturing a superconductor device described in this publication, a heat-resistant metal and copper, gold or platinum are formed by sputtering, so that a fine opening has good coverage and a stable film thickness. It is difficult to deposit these materials. Therefore, it is extremely difficult to form a thin film to exhibit superconductivity on a thin film of copper, gold or platinum after depositing these materials in the openings. Further, it is necessary to anneal the formed superconducting thin film in oxygen at 400 ° C. for a long time, and it takes a long time to manufacture a superconductor device.

Japanese Patent Application Laid-Open No. 63-265473 discloses a method for producing a superconducting electronic circuit. In this method, Y ⁺ ions are implanted into an insulating substrate made of Ba ₂ Cu ₃ O ₃ at an accelerating voltage of 200 keV, and YBa ₂ Cu
A superconducting wiring layer made of ₃ O ₃ is formed.

[0010] In a ceramic-based superconducting material, the most important factor causing the superconductivity phenomenon is stable CuO _x.
Forming a layer. However, C containing Ba in advance
It is difficult to stably form the uO _X layer.

Accordingly, an object of the present invention is to provide a method for forming a superconducting plug and a method for forming a multilayer wiring layer, which can reliably form a stable high-temperature superconducting plug in a fine opening in a relatively short time. To provide.

[0012]

The object of the present invention is to provide a method of forming a superconducting plug for electrically connecting a lower wiring layer and an upper wiring layer formed on a semiconductor substrate,
(A) forming, on a semiconductor substrate, a lower wiring layer and a conductor layer made of a metal or a metal compound thereon;
(B) forming a metal layer selected from the group consisting of gold, silver or copper on the conductor layer by a selective CVD method;
Crystallizing the CuO _x material while forming a layer made of the CuO _x material on the metal layer by a selective CVD method;
(D) a step of implanting ions of Group 3A atoms and ions of Group 2A atoms into a layer made of a CuO _x -based material, respectively, to form a high-temperature superconducting plug; This can be achieved by a plug forming method.

In the method of forming a superconducting plug of the present invention, the step of forming a conductor layer includes forming a silicon oxide film on a lower wiring layer, forming a metal film, and then performing heat treatment to form a metal silicide layer. Preferably, it comprises a step of forming.

The Group 3A atom can be an atom selected from lanthanoid elements such as Y or Yb. Also,
The group 2A atom can be an atom selected from Ba, Sr, and Ca.

A further object of the present invention is to provide a method of forming a multilayer wiring layer comprising a lower wiring layer, an upper wiring layer, and a superconducting plug for electrically connecting these wiring layers formed on a semiconductor substrate. And (b) forming a lower wiring layer and a conductor layer made of a metal or a metal compound on the lower wiring layer on the semiconductor substrate; and (b) forming a gold, silver or copper group on the conductor layer. Select the first metal layer selected CV
Forming by the method D; and (c) forming Cu on the first metal layer.
After crystallization of the CuO _x material while forming a first layer made of an O _x material by a selective CVD method, ions of group 3A atoms and group 2A atoms are added to the first layer made of CuO _x material. (D) forming a second metal layer selected from the group consisting of gold, silver or copper on the superconducting plug, and then forming a second metal layer on the superconducting plug. After crystallizing this CuO _x -based material while forming a second layer made of CuO _x -based material on the metal layer of
O to a second layer of _X-based material Group 3A atom ions and Group 2A atom ions are implanted, respectively, the multilayer interconnection structure of the present invention characterized by comprising the step, of forming a superconducting upper wiring layer This can be achieved by a layer forming method.

In the method for forming a multilayer wiring layer according to the present invention,
In the step of forming the conductor layer, a metal film is formed after forming a silicon oxide film on the lower wiring layer, and then heat treatment is performed,
It preferably comprises a step of forming a metal silicide layer.

The group 3A atom can be an atom selected from lanthanoid elements such as Y or Yb. Also,
The group 2A atom can be an atom selected from Ba, Sr, and Ca.

[0018]

In the method for forming a superconducting plug and the method for forming a multilayer wiring layer according to the present invention, the (first) metal layer and the CuO _x
Since the (first) layer made of a base material is formed by the selective CVD method, the (first) metal layer and the CuO
_The (first) layer made of the _X- based material can be deposited with good coverage and a stable film thickness. Also, Cu
Since consisting O _X based material (first) layer to crystallize the CuO _X-based material according while forming at selective CVD method, it can be shortened compared with the conventional method the time required for forming a superconducting plug .

Further, since a layer made of a CuO _x -based material is formed before ion implantation, a more stable layer can be formed. In addition, the amount of each ion to be implanted can be controlled accurately, and appropriate conditions for forming a superconducting material can be easily and accurately set.

[0020]

【Example】

Example 1 Example 1 relates to a method for forming a superconducting plug according to the present invention. (A) In [Step-100] to [Step-120],
A conductor layer is formed on a lower wiring layer formed on a semiconductor substrate. (B) Then, in [Step-130] to [Step-140], a metal layer selected from the group consisting of gold, silver or copper is formed on the conductor layer by a selective CVD method. (C) Next, in [Step-150], to crystallize the CuO _X-based material while forming a CuO _X-based material by selective CVD method on the metal layer. (D) Further, in [Step-160] to [Step-170], ions of Group 3A atoms and ions of Group 2A atoms are ion-implanted into the CuO _x -based material to form a high-temperature superconducting layer. The first embodiment will be described below with reference to FIGS.

[Step-100] First, based on a conventional method, an element isolation region 1 is formed on a semiconductor substrate 10 made of silicon.
Next, a gate electrode region 14 made of a gate oxide film and polysilicon is formed. Then LDD
In order to form a (Lightly Doped Drain) structure, ion implantation is performed to form a shallow impurity diffusion region 16. The conditions for this ion implantation are as follows when forming an NMOS:
For example, it can be As 40 KeV 1 × 10 ¹⁴ / cm ^2, and when forming a PMOS, it can be BF ₂ 30 KeV 5 × 10 ¹³ / cm ² , for example. Next, an approximately 400 nm thick SiO
_Two layers are formed on the entire surface by the CVD method. The conditions for forming the SiO ₂ layer are as follows, for example, using gas SiH ₄ / O ₂ / N ₂ = 250/250/1.
The temperature can be as low as 00 sccm and 420 ° C. Thereafter, the SiO ₂ layer is etched by anisotropic dry etching to form sidewalls 18 made of SiO ₂ on the sidewalls of the gate electrode region 14. The etching conditions for the SiO ₂ layer can be set, for example, as follows: gas used C ₄ F ₈ = 50 sccm RF power 1200 W pressure 2 Pa Through the above steps, a semiconductor element having a structure as shown in a schematic partial cross-sectional view in FIG.

[Step-110] Next, a thickness of 30
An nm Ti layer 20 is formed (see FIG. 1B). T
The conditions for forming the i-layer 20 may be, for example, RF bias −50 W DC sputtering power 1 kW Ar flow rate 40 sccm pressure 0.4 Pa forming temperature 200 ° C. film forming rate 60 nm / min. Then, RTA (Rapid Thermal
Annealing) method at 650 ° C, 30 in inert gas
A first annealing process is performed to silicide the Ti layer to form TiSi _x . Next, unreacted Ti is selectively removed by immersion in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide for 10 minutes. Then, at 900 ° C., 30 ° C. in an inert gas (eg, N ₂ )
Then, a second annealing process is performed to convert TiSi _X into low-resistance and stable TiSi ₂ . As a result, the source / drain region formation region and the gate electrode region 14 are formed.
On top, a conductor layer consisting of a uniform TiSi ₂ layer 22 is selectively formed.

[Step-120] Thereafter, ion implantation is performed on the entire surface to form the source / drain regions 24. The ion implantation conditions, the case of forming the NMOS, for example, be a ^{As 50KeV 3 × 10 15 / cm} 2, when forming a PMOS, for example, be a ^{_{BF 2 20KeV 1 × 10 15 /}} cm 2 Can be. Thereafter, an interlayer insulating layer 26 made of SiO ₂ and having a thickness of about 500 nm is deposited on the entire surface by a CVD method. The conditions for depositing SiO ₂ are, for example, as follows: gas flow rate: SiH ₄ / O ₂ / N ₂ = 250/250/1
00 sccm temperature 420 ° C pressure 13.3 Pa. Next, 1100 ° in N ₂ atmosphere
C, a short annealing process of 10 seconds is performed by the RTA method.
As a result, simultaneously with the activation of Si and TiSi ₂ , the diffusion of impurities in the source / drain region 24 is performed to form a junction region. As a result, a reduction in the sheet resistance of the TiSi ₂ layer 22 (for example, 8 Ω / sq.) Can be realized. The TiSi ₂ layer 22 functions as a barrier metal layer that prevents a CuO _x -based superconducting layer formed in a later step from diffusing into a semiconductor substrate.

[Step-100] to [Step-12]
0], the TiSi ₂ layer 2 is formed on the lower wiring layer composed of the source / drain regions 24 formed on the semiconductor substrate.
2 is formed (see FIG. 1C).

[Step-130] Next, resist patterning is performed on the interlayer insulating layer 26, an opening 28 is formed in the interlayer insulating layer 26 by dry etching, and the resist is removed (see FIG. 2A). . The dry etching conditions can be, for example, a used gas of C ₄ F ₈ = 50 sccm, an RF power of 1200 W and a pressure of 2 Pa. In order to form a good contact, a mixed solution of ammonia water and hydrogen peroxide solution (NH
₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 7) by immersion for 10 minutes to obtain Ti fluoride such as TiF ₃ which is a by-product generated by dry etching when forming the opening 28. From the bottom of the opening 28.

[Step-140] Next, the metal layer 30, which functions as an adhesion layer for a superconducting material, for example, has a thickness of 50
metal layer 30 made of Au having a thickness of
It is deposited by the VD method. The conditions for forming the metal layer 30 made of Au are, for example, as follows: Gas source Dimethyl (1,1,1-trifluoro-2,4-pentandio
nato) gold (3) = 100 sccm temperature 170 ° C. Here, Au is exemplified, but Ag
Alternatively, Cu may be formed by a selective CVD method. in this case,
Ag (C ₅ H ₇ O ₂ ) or Cu (C ₅ H ₇
A metal layer made of Ag or Cu is selectively deposited in the opening 28 using an organic gas source such as O ₂ ) ₂ .

[Step-150] Next, a layer made of a CuO _x -based material is placed on the metal layer 30 formed in the opening 28.
It is deposited to a thickness of 250 nm by a selective CVD method. CuO
_The conditions for forming the layer made of the _X- based material are, for example, gas source Bis-hexa-fluoro-acethylacetonato cuppe
r Cu (HFA) ₂ ) / O ₂ = 100/50 sccm Temperature 250 ° C. Under such temperature conditions, a layer made of a CuO _x material is crystallized while being deposited on the metal layer 30.

[Step-160] Thereafter, Ba belonging to Group 2A and Y belonging to Group 3A are ion-implanted over the entire surface. The ion implantation conditions for Ba and Y can be set to an implantation energy of 100 keV and an implantation amount of about 1 × 10 ²⁰ / cm ³ or more. Through the above steps, the opening 28
The high-temperature superconducting layer 32 is formed only inside, and the superconducting plug is completed (see FIG. 2C).

[Step-180] Next, a barrier metal layer 34 for an upper wiring layer is formed. The barrier metal layer 34 has a three-layer structure of, for example, Ti / TiON / Ti, and can be sequentially formed by a sputtering method under the following conditions. Ti: Ar flow rate 40 sccm DC sputtering power 1 kW Pressure 0.4 Pa temperature 150 ° C TiON: Ar / N ₂ -6% O ₂ 40/70 sccm DC sputtering power 5 kW Pressure 0.4 Pa temperature 150 ° C Ti: Ar flow rate 40 sccm DC sputtering Power 1kW Pressure 0.4Pa Temperature 150 ° C

[Step-190] Next, an upper wiring layer 36 made of Al-1% Si is formed (see FIG. 3). First,
For example, Al-1% Si is sputtered under the following conditions. Ar flow rate 40 sccm Pressure 0.4 Pa DC sputtering power 6 kW Sputtering rate 800 nm / min Thickness 800 nm Then, resist patterning is performed, and then dry etching is performed to obtain the sputtered A.
By patterning the 1-1% Si layer and removing the resist, the aluminum-based upper wiring layer 36 is completed.
The dry etching of the Al-1% Si layer is performed by, for example, RF
It can be performed under the following conditions using an application type ECR etcher. BCl ₃ / Cl ₂ 60/90 sccm Microwave power 1000 W DC sputtering power 1 kW Ar flow rate 40 sccm RF power 50 W Pressure 13.3 Pa The lower wiring layer composed of the source / drain regions 24 formed on the semiconductor substrate by the above process, A superconducting plug for electrically connecting the aluminum-based upper wiring layer 36 is completed.

(Embodiment 2) In Embodiment 2, the step of forming a conductor layer comprises forming a silicon oxide film on a lower wiring layer, forming a metal film made of titanium, and then performing heat treatment to form a titanium silicide. A superconducting plug is completed in the same process as in Example 1 except that a metal silicide layer made of a layer is formed.

[Step-200] Step-200 is the same as step-100 in Example 1, and the description thereof is omitted.

[Step-210] Next, a 3 nm-thick silicon oxide film 20A is formed on the entire surface by thermal oxidation. The conditions for forming the silicon oxide film 20A can be as follows. Working gas O ₂ 6 liter / min Temperature 850 ° C. Then, a 30 nm-thick Ti film is formed on the silicon oxide film 20A by the same method and under the same conditions as [Step-110] of the first embodiment.
A metal film composed of the layer 20 is formed (see FIG. 4). Thereafter, a first annealing process is performed in an inert gas at 650 ° C. for 30 minutes in an inert gas by RTA (Rapid Thermal Annealing) to silicify the Ti layer to form TiSi _x . Next, unreacted Ti is selectively removed by immersion in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide for 10 minutes. Next, a second annealing process is performed in an inert gas (for example, N ₂ ) atmosphere at 900 ° C. for 30 minutes to convert TiSi _X into low-resistance and stable TiSi ₂ . As a result, a uniform conductive layer composed of the TiSi ₂ layer 22 is selectively formed on the source / drain region formation region and the gate electrode region 14.

[Step-220] After that, a superconducting plug is completed in the same steps as [Step-120] to [Step-190] of the first embodiment.

Embodiment 3 Embodiment 3 relates to a method for forming a multilayer wiring layer according to the present invention.
That is, (a) In [Step-300] to [Step-320],
A lower wiring layer is formed on a semiconductor substrate, and a conductor layer is formed on the lower wiring layer. (B) Next, in [Step-330] to [Step-340], a first metal layer selected from the group consisting of gold, silver or copper is formed on the conductor layer by a selective CVD method. (C) Thereafter, in [Step -350], after crystallizing the CuO _X-based material while forming a first layer of CuO _X-based material on the first metal layer by a selective CVD method, [step in -360] - [step -370], the first layer 3A group atom consisting of CuO _X based material ions and group 2A atom ions are implanted, respectively, to form a superconducting plug. (D) Next, in [Step-380] to [Step-390], a second metal layer selected from the group consisting of gold, silver or copper is formed on the superconducting plug, and then the second metal layer is formed. After crystallizing the CuO _x -based material while forming a second layer made of a CuO _x -based material on the metal layer, ions of group 3A atoms and ions of group 2A atoms are added to the second layer made of CuO _x -based material. Are respectively ion-implanted, and the second layer is used as a superconducting upper wiring layer to complete a multilayer wiring layer.

[Step-300] This step is the same as [Step-100] in Example 1, and a detailed description thereof will be omitted. Through this step, a semiconductor element having a structure as shown in a schematic partial cross-sectional view in FIG.

[Step-310] to [Step-320] These steps are also the same as those of [Step-110] to [Step-12] in Example 1.
0], and a detailed description thereof will be omitted. Through the above [Step-300] to [Step-320], a conductor layer made of a TiSi ₂ layer is formed on the lower wiring layer made of the source / drain regions formed on the semiconductor substrate ((FIG. 1) B) and (C)).

[Step-330] This step is the same as [Step-130] of the first embodiment, and a detailed description thereof will be omitted.

[Step-340] Then, a first metal layer 30A functioning as an adhesion layer for a superconducting material, for example, Au having a thickness of 50 nm, is formed on the conductor layer made of the TiSi ₂ layer 22 in the opening 28. A first metal layer 30A made of Ag, Cu, or Cu is grown by a selective CVD method (see FIG. 2B). This step is the same as [Step-14] in Example 1.
0], and a detailed description thereof will be omitted.

[0040] [Step -350] - [Step -360] Next, the first layer 32A consisting of CuO _X-based material, on the first metal layer 30A which is formed in the opening 28, 250 n
Crystallization is performed while depositing the layer to a thickness of m by the selective CVD method.
Then, ion implantation is performed to CuO _X-based materials, a high temperature superconducting the first layer 32A consisting of CuO _X-based material. Thus, a high-temperature superconducting plug is completed (see FIG. 5A). These steps are also the same as those described in [Step-150] of Example 1.
This is the same as [Step-160], and a detailed description thereof will be omitted.

[Step-370] Next, the second metal layer 3 as an adhesion layer for the upper wiring layer made of a superconductive material
8 is grown on the entire surface by CVD, for example, under the following conditions. The second metal layer 38 can be formed from Au. Gas source Dimethyl (1,1,1-trifluoro-2,4-pentandio
nato) gold (3) = 100 sccm Temperature 250 ° C. Here, Au is taken as an example, but Ag or Cu may be grown by CVD. In this case, the gas source is A
_{g (C 5 H 7 O 2} ) or _{Cu (C 5 H 7 O 2} ) , or the like can be used ₂ or the like organic gas source. Also, the second metal layer 3
8 need not be formed in the opening,
Instead of depositing a metal layer 38 of
It can also be deposited using a sputtering method.

[Step-380] Next, in order to form an upper wiring layer, a second layer 40 made of a CuO _x -based material is formed on the second metal layer 38 (adhesion layer) by, eg, CVD. (See FIG. 5B). The conditions for forming the second layer 40 made of a CuO _x -based material are, for example, as follows: gas source Bis-hexa-fluoro-acethylacetonato cuppe
r Cu (HFA) ₂ / O ₂ = 100/50 sccm Temperature 250 ° C. Thickness 250 nm With such temperature conditions, the second layer 40 made of a CuO _x -based material is
Is crystallized while being deposited on the metal layer 38 of FIG. In addition, CV
Instead of D method, for example it is possible to form the second layer 40 consisting of CuO _X-based material at a high temperature sputtering method under the following conditions. Sputter gas Ar / O ₂ = 45/3 sccm DC power 5 kW Pressure 0.47 Pa Film thickness 250 nm Film formation temperature 600 ° C. Thereafter, Ba and Y are ion-implanted over the entire surface. The ion implantation conditions for Ba and Y can be set to an implantation energy of 100 keV and an implantation amount of about 1 × 10 ²⁰ / cm ³ or more. Thus, the second layer 40 is made superconductive at a high temperature.

[Step-390] Next, after resist patterning, the second layer 40 made of a CuO _x -based material into which Ba and Y have been ion-implanted by dry etching, and A
The second metal layer 38 made of u is etched. Etching can be performed, for example, under the following conditions. Gas CCl ₂ F ₂ / Cl ₂ = 60 / 50s
The superconducting plug and the superconducting upper wiring layer are formed by the steps of ccm microwave power 1000 W RF power 50 W pressure 2 Pa or more, and the multilayer wiring layer is completed.

(Embodiment 4) In Embodiment 4, the step of forming a conductor layer comprises forming a silicon oxide film on a lower wiring layer, forming a metal film made of titanium, and then performing heat treatment to form a titanium silicide. A multilayer wiring layer is completed in the same process as in Example 3 except that a metal silicide layer composed of a layer is formed.

[Step-400] Step-400 is the same as step-100 of Example 1, and the description thereof is omitted.

[Step-410] Next, a 3 nm-thick silicon oxide film 20A is formed on the entire surface by thermal oxidation. The conditions for forming the silicon oxide film 20A can be as follows. Working gas O ₂ 6 liter / min Temperature 850 ° C. Then, a 30 nm-thick Ti film is formed on the silicon oxide film 20A by the same method and under the same conditions as [Step-110] of the first embodiment.
A metal film composed of the layer 20 is formed (see FIG. 4). Thereafter, a first annealing process is performed in an inert gas at 650 ° C. for 30 minutes in an inert gas by RTA (Rapid Thermal Annealing) to silicify the Ti layer to form TiSi _x . Next, unreacted Ti is selectively removed by immersion in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide for 10 minutes. Next, a second annealing process is performed in an inert gas (for example, N ₂ ) atmosphere at 900 ° C. for 30 minutes to convert TiSi _X into low-resistance and stable TiSi ₂ . As a result, a uniform conductive layer composed of the TiSi ₂ layer 22 is selectively formed on the source / drain region formation region and the gate electrode region 14.

[Step-420] After that, a multilayer wiring layer is completed in the same steps as [Step-320] to [Step-390] of the third embodiment.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The conditions in each step can be appropriately changed depending on the equipment used and the like.

The conductor layer is made of a low-resistance and superconducting material or C instead of a metal silicide layer made of TiSi _2.
Any metal silicide layer that functions as a barrier to a metal layer made of u, Au, or Ag can be used. For example, CoSi ₂ , WSi ₂ , MoSi
₂ can be exemplified. Further, it may be made of a high melting point metal such as W or Mo, or a so-called barrier metal such as TiN, TiB or TiW.

Although the source / drain region has been described as an example of the lower wiring layer, it may be a gate electrode region or a lower wiring layer made of a metal wiring material or a superconductive material. For the upper wiring layer in the method of forming a superconducting plug of the present invention, various wiring materials conventionally used can be used in addition to the aluminum-based wiring material.

[0051]

According to the present invention, since the plug formed in the connection hole is made of a superconductive material, the resistance in the connection hole or the wiring resistance is almost eliminated, and the performance of the semiconductor device is improved.

In the method for forming a superconducting plug and the method for forming a multilayer wiring layer according to the present invention, the (first) metal layer and the Cu
Consisting O _X based material since the (first) layer is formed by selective CVD, a metal layer and CuO _X-based material in the minute opening portion (first) layer of good coverage and stably film thickness Can be deposited. Further, since the crystallized according CuO _X-based material while forming consists CuO _X based material (first) layer by selective CVD method, to shorten the time required for forming the superconducting plugs than conventional methods Can be.

Further, since the (first) layer made of the CuO _x material is formed before the ion implantation is performed, a more stable layer can be formed. In addition, the amount of each ion to be implanted can be controlled accurately, and appropriate conditions for forming a superconducting material can be easily and accurately set. Therefore, it is easy to mass-produce the superconducting plug or the multilayer wiring layer.

Further, since the surface of the semiconductor substrate is covered with the conductor layer, diffusion of Cu or the like constituting the superconducting material into the semiconductor substrate can be prevented. Further, since a metal layer made of gold, silver, or copper, which is a substance that facilitates crystal growth of a CuO _x -based material, is used as an underlayer, C
The uO _X-based material may easily and stably by crystal growth.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of a method for forming a superconducting plug of the present invention.

FIG. 2 is a schematic partial cross-sectional view of the semiconductor device for illustrating each step of the method for forming a superconducting plug of the present invention, following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of a semiconductor device manufactured by a method for forming a superconducting plug of the present invention.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor device for illustrating a part of the steps of a preferred embodiment of the method for forming a superconducting plug of the present invention.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor device for illustrating a part of steps of a method for forming a multilayer wiring layer according to the present invention.

FIG. 6 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of a conventional selective CVD method.

[Explanation of symbols]

Reference Signs List 10 semiconductor substrate 12 element isolation region 14 gate electrode region 16 shallow impurity diffusion region 18 sidewall 20 Ti layer 20A silicon oxide film 22 TiSi ₂ layer 24 source / drain region 26 interlayer insulating layer 28 opening 30 metal layer 30A first metal Layer 32 high-temperature superconducting layer 32A first high-temperature superconducting layer 34 barrier metal layer 36 upper wiring layer 38 second metal layer 40 superconducting upper wiring layer

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/3205 ZAA H01L 39/06 ZAA 39/06 ZAA 39/24 ZAAF 39/24 ZAA 21/88 ZAAM (58) (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768 H01L 39/06

Claims (4)

(57) [Claims] 1. A method of forming a superconducting plug for electrically connecting a lower wiring layer and an upper wiring layer formed on a semiconductor substrate, comprising: (a) forming a lower wiring layer and a lower wiring layer on the semiconductor substrate; (B) forming a metal layer selected from the group consisting of gold, silver or copper on the conductive layer by a selective CVD method; (C) selecting a layer made of a CuO _x -based material on the metal layer
Crystallizing the CuO _x -based material while forming it by the VD method; and (d) ion-implanting ions of group 3A atoms and ions of group 2A atoms into the layer made of the CuO _x -based material,
Forming a high-temperature superconducting plug. 2. The method according to claim 1, wherein the step of forming the conductor layer comprises a step of forming a metal film after forming a silicon oxide film on the lower wiring layer, and then performing a heat treatment to form a metal silicide layer. The method for forming a superconducting plug according to claim 1. 3. A method for forming a multilayer wiring layer including a lower wiring layer, an upper wiring layer, and a superconducting plug for electrically connecting these wiring layers formed on a semiconductor substrate, comprising: A) forming a lower wiring layer and a conductor layer made of a metal or a metal compound thereon on the semiconductor substrate; and (b) forming a lower layer selected from the group consisting of gold, silver or copper on the conductor layer. (C) forming a first metal layer by a selective CVD method; and (c) forming a first layer of CuO _x -based material on the first metal layer.
After the CuO _x -based material is crystallized while forming a layer by selective CVD, ions of group 3A atoms and 2
Forming a superconducting plug by ion-implanting ions of Group A atoms, and (d) forming a second metal layer selected from the group consisting of gold, silver or copper on the superconducting plug. Then, after crystallizing the CuO _x -based material while forming a second layer made of a CuO _x -based material on the second metal layer, 3A is added to the second layer.
Forming a superconducting upper wiring layer by ion-implanting ions of Group 2 atoms and ions of Group 2A atoms, respectively. 4. The method according to claim 1, wherein the step of forming the conductor layer comprises a step of forming a metal film after forming a silicon oxide film on the lower wiring layer, and then performing a heat treatment to form a metal silicide layer. The method for forming a multilayer wiring layer according to claim 3.