JPH05326720A - Method for formation of superconducting plug and multilayer interconnection layer - Google Patents

Abstract

PURPOSE:To obtain a superconducting plug forming method and a multilayer interconnection layer forming method with which a stabilized high temperature superconducting plug can be formed accurately on a microscopic aperture in a relatively short period of time. CONSTITUTION:The superconducting plug forming method, by which the lower wiring layer and the upper wiring layer formed on a semiconductor substrate 10 is electrically connected, consists of the following processes: (A) a process in which a lower wiring layer 24 and a conductive layer 22, consisting of metal or a metal compound, are formed on a semiconductor substrate 10, (B) a process in which a metal layer 30, made of a metal selected from a group consisting of gold, silver and copper, is formed on the conductive layer 22 by a CVD method, (C) a process in which a layer 32, consisting of CuOx material, is formed on the metal layer 30 by a CVD method and the CuOx material is crystallized, and (D) a process in which 3A-group atomic ions and 2A-group atomic ions are implanted into the CuOx layer and a high temperature superconducting plug is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a superconducting plug and a multilayer wiring layer in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, contact holes, via holes, through holes, etc. (hereinafter, also collectively referred to as connection holes) have been reduced in size with the miniaturization of design rules of semiconductor devices. Generally, the connection hole is formed by providing an opening in the interlayer insulating layer and embedding a metal wiring material in the opening. The wiring material embedded in the opening is called a plug. Further, the wiring material forming the plug is called a plug material. It is becoming difficult to embed a conventional metal such as aluminum into the opening by a sputtering method because of problems such as coverage of metal wiring material. Therefore, in recent years, a selective CVD method using tungsten has attracted attention as a technique for filling fine openings. Since the connection hole is formed by the selective CVD method, there is no problem in the coverage of tungsten, and the plug made of tungsten can be well formed in the opening.

An outline of the selective CVD method using this tungsten will be described below with reference to FIG. (A) The element isolation region 12 is formed in the semiconductor substrate 10 by the conventional method. (B) Gate oxidation is performed to form a polysilicon layer and WSi ₂
Deposit layers. Next, patterning of the gate oxide film, the polysilicon layer and the WSi ₂ layer is performed, and the gate oxide film,
A gate electrode region 14 made of a polysilicon layer and a WSi ₂ layer is formed, and then ion implantation is performed to form an LDD structure to form a shallow impurity diffusion region 16. (C) Next, a SiO ₂ film is deposited on the entire surface. afterwards,
The SiO ₂ film is etched back to form sidewalls 18 on the sides of the gate electrode region (see FIG. 6A). Then, ion implantation is performed to form the source / drain regions 24. (D) Then, after depositing the interlayer insulating layer 26, activation annealing treatment is performed. Then, the interlayer insulating layer is patterned to form the opening 28 (see FIG. 6B). (E) Next, tungsten 50 is deposited only in the opening 26 by the selective tungsten CVD method to complete a plug made of tungsten. (F) Metal wiring layer (for example, Al-1% Si / Ti / T
iON / Ti structure) is formed. Next, resist patterning is performed, and the metal wiring portion 52 is dry-etched.
Are formed (see FIG. 6C).

[0004]

When the resistance value of the connection hole formed by the selective tungsten CVD method as described above is examined, it is about 10 μΩcm, and the resistance value of the connection hole formed of the aluminum-based wiring material. There is a problem that it is about three times as large. Further, in the semiconductor device of the 0.35 μm rule or later, if the degree of integration of semiconductor elements increases in the future,
About 10 ⁹ to 10 ¹⁰ or more connection holes are formed in one semiconductor device. Therefore, the voltage drop in the connection hole cannot be ignored, and it is necessary to reduce the resistance of the plug material.

In order to reduce the electric resistance of the connection hole, Cu
O _X based material have been studied. Recent studies on high-temperature superconductivity have suggested that CuO _x itself is a superconducting substance. In other words, Ba-Y-CuO _X
In a ceramic such as a system, a region where electric resistance is zero, that is, a portion where a current flows is considered to be a portion where a current mainly flows along the CuO _x plane.

In order to reduce the electric resistance of the connection hole, a superconductor device using a plug material made of a superconducting material is disclosed.
For example, it is disclosed in JP-A-63-275144.

The superconducting device described in this publication includes a superconducting material in close contact with copper, gold, platinum, or a material containing these as a main component, and a superconducting material in close contact with a heat-resistant metal material or the metal. It has a multi-layer structure of a compound material of the material forming the substrate. The refractory metal and copper, gold or platinum are formed by the sputtering method. Materials that should exhibit superconductivity are (A _{1- X}
B _X ) Cu _Z O _W. Then, a material that should exhibit superconductivity is formed into a thin film by a sputtering method or a CVD method. The formed thin film that should exhibit superconductivity is heated to 400 ° C (1 to
Annealing treatment is performed for 30 hours, for example, 10 hours to make it superconducting.

In the method for manufacturing a superconductor device described in this publication, the refractory metal and copper, gold or platinum are formed by the sputtering method, so that the fine openings have good coverage and a stable film thickness. It is difficult to deposit these materials. Therefore, it is extremely difficult to form a thin film which should exhibit superconductivity on a copper, gold or platinum thin film after depositing these materials in the opening. Further, it is necessary to anneal the formed thin film which should exhibit superconductivity in oxygen at 400 ° C. for a long time, and it takes a long time to manufacture a superconductor device.

Japanese Unexamined Patent Publication No. 63-265473 discloses a method for producing a superconducting electronic circuit. In this manufacturing method, Y ⁺ ions are implanted into an insulating substrate made of Ba ₂ Cu ₃ O ₃ at an accelerating voltage of 200 keV to obtain YBa ₂ Cu.
A superconducting wiring layer made of ₃ O ₃ is formed.

In the ceramic superconducting material, the most important factor causing the superconducting phenomenon is stable CuO _x.
Forming a layer. However, C containing Ba in advance
It is difficult to stably form the uO _x layer.

Therefore, an object of the present invention is to provide a method for forming a superconducting plug and a method for forming a multi-layer wiring layer, which can reliably form a stable high temperature superconducting plug in a fine opening in a relatively short time. To provide.

[0012]

The above-mentioned object is a method of forming a superconducting plug for electrically connecting a lower wiring layer and an upper wiring layer formed on a semiconductor substrate.
(A) A step of forming a lower wiring layer on the semiconductor substrate and a conductor layer made of a metal or a metal compound thereon,
(B) a step of forming a metal layer selected from the group consisting of gold, silver or copper on the conductor layer by a selective CVD method, and (c)
A step of crystallizing the CuO _x -based material while forming a layer of the CuO _x -based material on the metal layer by a selective CVD method;
(D) A step of forming a high temperature superconducting plug by implanting ions of a 3A group atom and 2A group atom into a layer made of a CuO _x material, respectively. This can be achieved by the method of forming the plug.

In the method of forming a superconducting plug of the present invention, in the step of forming the conductor layer, a silicon oxide film is formed on the lower wiring layer, then a metal film is formed, and then heat treatment is performed to form a metal silicide layer. Preferably, it comprises a forming step.

The Group 3A atom can be an atom selected from lanthanoid elements such as Y or Yb. Also,
The 2A group atom can be an atom selected from Ba, Sr, and Ca.

Further, the above-mentioned object is a method of forming a multilayer wiring layer including a lower wiring layer, an upper wiring layer formed on a semiconductor substrate and a superconducting plug for electrically connecting these wiring layers. And (b) a step of forming a lower wiring layer and a conductor layer made of a metal or a metal compound on the lower wiring layer on a semiconductor substrate; and (b) a group made of gold, silver or copper on the conductor layer. Select the selected first metal layer CV
Step of forming by D method, and (C) Cu on the first metal layer
While forming a first layer of O _X based material by selective CVD method after the CuO _X based material was crystallized, ions and Group 2A atom group 3A atom to the first layer of CuO _X-based material Forming a superconducting plug by ion-implanting each of the ions of (4), and (d) forming a second metal layer selected from the group consisting of gold, silver or copper on the superconducting plug, and then forming a second metal layer. After crystallizing the CuO _x -based material while forming a second layer of the CuO _x -based material on the second metal layer, Cu
O to a second layer of _X-based material Group 3A atom ions and Group 2A atom ions are implanted, respectively, the multilayer interconnection structure of the present invention characterized by comprising the step, of forming a superconducting upper wiring layer This can be achieved by a layer forming method.

In the multi-layer wiring layer forming method of the present invention,
In the step of forming the conductor layer, a silicon oxide film is formed on the lower wiring layer, a metal film is formed, and then heat treatment is performed.
It preferably comprises a step of forming a metal silicide layer.

The Group 3A atom can be an atom selected from lanthanoid elements such as Y or Yb. Also,
The 2A group atom can be an atom selected from Ba, Sr, and Ca.

[0018]

In the method of forming the superconducting plug and the method of forming the multilayer wiring layer of the present invention, the (first) metal layer and CuO _{x are formed.}
Since the (first) layer made of a system material is formed by the selective CVD method, the (first) metal layer and CuO are formed in the fine openings.
_The (first) layer made of an _X- based material can be deposited with good coverage and a stable film thickness. Also, Cu
Since consisting O _X based material (first) layer to crystallize the CuO _X-based material according while forming at selective CVD method, it can be shortened compared with the conventional method the time required for forming a superconducting plug ..

Further, since the layer made of the CuO _x type material is formed before the ion implantation, a more stable layer can be formed. Moreover, the implantation amount of each ion can be accurately controlled, and appropriate conditions for forming the superconducting substance can be easily and accurately set.

[0020]

【Example】

(Example 1) Example 1 relates to a method for forming a superconducting plug of the present invention. That is, (a) in [Step-100] to [Step-120],
A conductor layer is formed on the lower wiring layer formed on the semiconductor substrate. (B) Then, in [Step-130] to [Step-140], a metal layer selected from the group consisting of gold, silver or copper is formed on the conductor layer by the selective CVD method. (C) Next, in [Step-150], to crystallize the CuO _X-based material while forming a CuO _X-based material by selective CVD method on the metal layer. (D) Further, in [Step-160] to [Step-170], ions of a 3A group atom and 2A group atom are ion-implanted into the CuO _x based material to form a high temperature superconducting layer. The first embodiment will be described below with reference to FIGS. 1 to 3.

[Step-100] First, the element isolation region 1 is formed on the semiconductor substrate 10 made of silicon based on the conventional method.
2 is formed, and then a gate electrode region 14 made of a gate oxide film and polysilicon is formed. Then LDD
In order to form a (Lightly Doped Drain) structure, ion implantation is performed to form a shallow impurity diffusion region 16. The conditions for this ion implantation are as follows when forming an NMOS:
For example, As 40 Kev 1 × 10 ¹⁴ / cm ² can be used, and in the case of forming a PMOS, for example, BF ₂ 30 KeV 5 × 10 ¹³ / cm ² can be used. Next, about 400 nm thick SiO
_Two layers are formed on the entire surface by the CVD method. The conditions for forming the SiO ₂ layer are, for example, using gas SiH ₄ / O ₂ / N ₂ = 250/250/1.
The temperature can be 00 sccm and 420 ° C. After that, the SiO ₂ layer is etched by anisotropic dry etching to form sidewalls 18 made of SiO ₂ on the sidewalls of the gate electrode region 14. The etching conditions for the SiO ₂ layer can be, for example, used gas C ₄ F ₈ = 50 sccm RF power 1200 W and pressure 2 Pa. Through the above steps, a semiconductor element having a structure as shown in the schematic partial cross-sectional view of FIG. 1A can be formed.

[Step-110] Next, a thickness of 30 is applied to the entire surface.
A Ti layer 20 having a thickness of 10 nm is formed (see FIG. 1B). T
The conditions for forming the i layer 20 can be, for example, RF bias -50 W DC sputter power 1 kW Ar flow rate 40 sccm pressure 0.4 Pa formation temperature 200 ° C. film formation rate 60 nm / min. After that, RTA (Rapid Thermal
Annealing) method, 650 ° C in inert gas, 30
Performing a first round of annealing minute, silicided Ti layer, to form a TiSi _X. Next, unreacted Ti is selectively removed by immersing in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide for 10 minutes. Then, in an inert gas (for example, N ₂ ) atmosphere, 900 ° C., 30
Then, the second annealing process is performed to convert TiSi _x into stable low resistance TiSi ₂ . As a result, on the source / drain region formation planned region and the gate electrode region 14
A conductor layer made of a uniform TiSi ₂ layer 22 is selectively formed on the upper surface.

[Step-120] After that, in order to form the source / drain regions 24, ion implantation is performed on the entire surface. The ion implantation conditions, the case of forming the NMOS, for example, be a ^{As 50KeV 3 × 10 15 / cm} 2, when forming a PMOS, for example, be a ^{_{BF 2 20KeV 1 × 10 15 /}} cm 2 You can After that, an interlayer insulating layer 26 made of SiO ₂ and having a thickness of about 500 nm is deposited on the entire surface by the CVD method. The deposition conditions of SiO ₂ are, for example, gas flow rate SiH ₄ / O ₂ / N ₂ = 250/250/1
The temperature may be 00 sccm, the temperature may be 420 ° C, and the pressure may be 13.3 Pa. Next, in a N ₂ atmosphere, 1100 °
C. A short-time annealing process of 10 seconds is performed by the RTA method.
As a result, Si and TiSi ₂ are activated, and at the same time, impurities are diffused in the source / drain regions 24 to form a junction region. As a result, reduction of the sheet resistance of the TiSi ₂ layer 22 (for example, 8Ω / sq.) Can be realized. The TiSi ₂ layer 22 functions as a barrier metal layer that prevents a CuO _x -based superconducting layer formed in a later step from diffusing into the semiconductor substrate.

[Step-100] to [Step-12]
0], the TiSi ₂ layer 2 is formed on the lower wiring layer composed of the source / drain regions 24 formed on the semiconductor substrate.
A conductor layer composed of 2 is formed (see FIG. 1C).

[Step-130] Next, resist patterning is performed on the interlayer insulating layer 26, the opening 28 is formed in the interlayer insulating layer 26 by dry etching, and then the resist is removed (see FIG. 2A). .. The conditions of dry etching can be, for example, used gas C ₄ F ₈ = 50 sccm RF power 1200 W pressure 2 Pa. In order to form a good contact, a mixed solution of ammonia water and hydrogen peroxide solution (NH
₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 7), and a fluoride of Ti such as TiF ₃ which is a by-product produced by dry etching when the opening 28 is formed. Is preferably removed from the bottom of opening 28.

[Step-140] Next, the metal layer 30 functioning as an adhesion layer for the superconducting material, for example, a thickness of 50.
nm of Au metal layer 30 selected in opening 28
It is deposited by the VD method. The conditions for forming the metal layer 30 made of Au are, for example, gas source Dimethyl (1,1,1-trifluoro-2,4-pentandio).
nato) gold (3) = 100 sccm and temperature 170 ° C. Here, Au is exemplified, but Ag is
Alternatively, Cu may be formed by a selective CVD method. in this case,
As a gas source, Ag (C ₅ H ₇ O ₂ ) or Cu (C ₅ H ₇
A metal layer made of Ag or Cu is selectively deposited in the opening 28 using an organic gas source such as O ₂ ) ₂ .

[Step-150] Next, a layer made of a CuO _x system material is formed on the metal layer 30 formed in the opening 28.
It is deposited to a thickness of 250 nm by the selective CVD method. CuO
_The conditions for forming a layer made of an _X- based material are, for example, gas source Bis-hexa-fluoro-acethylacetonato cuppe.
r Cu (HFA) ₂ ) / O ₂ = 100/50 sccm Temperature can be 250 ° C. Under such a temperature condition, the layer made of the CuO _x material is crystallized while being deposited on the metal layer 30.

[Step-160] After that, Ba belonging to the 2A group and Y belonging to the 3A group are ion-implanted over the entire surface. B
The ion implantation conditions for a and Y can be: implantation energy 100 keV implantation amount 1 × 10 ²⁰ / cm ² or more. Through the above steps, the opening 28
The high temperature superconducting layer 32 is formed only in the inside, and the superconducting plug is completed (see FIG. 2C).

[Step-180] Next, a barrier metal layer 34 for the upper wiring layer is formed. The barrier metal layer 34 has, for example, a three-layer structure of Ti / TiON / Ti and can be sequentially formed by the sputtering method under the following conditions. Ti: Ar flow rate 40sccm DC sputtering power 1kW pressure 0.4Pa temperature 150 ° C TiON: Ar / N ₂ -6% O ₂ 40 / 70sccm DC sputter power 5kW pressure 0.4Pa temperature 150 ° C Ti: Ar flow rate 40sccm DC sputtering Power 1kW Pressure 0.4Pa Temperature 150 ° C

[Step-190] Next, the upper wiring layer 36 made of Al-1% Si is formed (see FIG. 3). First,
For example, Al-1% Si is sputtered under the following conditions. Ar flow rate 40 sccm pressure 0.4 Pa DC sputter power 6 kW sputter rate 800 nm / min thickness 800 nm After that, resist patterning was performed, and then dry etching was performed to sputter A.
The 1-1% Si layer is patterned and the resist is removed to complete the aluminum-based upper wiring layer 36.
Dry etching of the Al-1% Si layer is performed by RF, for example.
It can be performed under the following conditions using an application type ECR etcher. BCl ₃ / Cl ₂ 60/90 sccm microwave power 1000 W DC sputter power 1 kW Ar flow rate 40 sccm RF power 50 W pressure 13.3 Pa A lower wiring layer consisting of the source / drain regions 24 formed on the semiconductor substrate by the above steps, A superconducting plug for electrically connecting the aluminum-based upper wiring layer 36 is completed.

(Embodiment 2) In Embodiment 2, in the step of forming the conductor layer, a silicon oxide film is formed on the lower wiring layer, and then a metal film made of titanium is formed, and then heat treatment is performed to form titanium silicide. A superconducting plug is completed by the same steps as in Example 1 except that a metal silicide layer composed of layers is formed.

[Step-200] Step-200 is the same as Step-100 of Example 1, and the description thereof is omitted.

[Step-210] Next, a silicon oxide film 20A having a thickness of 3 nm is formed on the entire surface by thermal oxidation. The conditions for forming the silicon oxide film 20A can be set as follows. Gas used O ₂ 6 liter / min Temperature 850 ° C. Then, in the same manner and conditions as in [Step-110] of Example 1, Ti having a thickness of 30 nm was formed on the silicon oxide film 20A.
A metal film composed of the layer 20 is formed (see FIG. 4). After that, a first annealing process is performed in an inert gas at 650 ° C. for 30 minutes by RTA (Rapid Thermal Annealing) method to silicify the Ti layer to form TiSi _x . Next, unreacted Ti is selectively removed by immersing in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide for 10 minutes. Then, a second annealing treatment is performed at 900 ° C. for 30 minutes in an inert gas (for example, N ₂ ) atmosphere to convert TiSi _x to stable TiSi ₂ having low resistance. As a result, a uniform conductor layer made of the TiSi ₂ layer 22 is selectively formed on the source / drain region formation planned region and the gate electrode region 14.

After [Step-220], the superconducting plug is completed by the same steps as [Step-120] to [Step-190] of the first embodiment.

(Embodiment 3) Embodiment 3 relates to a method for forming a multilayer wiring layer of the present invention. That is, in (a) [step-300] to [step-320],
A lower wiring layer is formed on the semiconductor substrate, and a conductor layer is formed on the lower wiring layer. (B) Next, in [Step-330] to [Step-340], a first metal layer selected from the group consisting of gold, silver, or copper is formed on the conductor layer by the selective CVD method. (C) Thereafter, in [Step -350], after crystallizing the CuO _X-based material while forming a first layer of CuO _X-based material on the first metal layer by a selective CVD method, [step -360] to [Step-370], ions of group 3A atoms and ions of group 2A atoms are individually ion-implanted into the first layer made of the CuO _x material to form a superconducting plug. (D) Next, in [Step-380] to [Step-390], a second metal layer selected from the group consisting of gold, silver, or copper is formed on the superconducting plug, and then a second metal layer is formed. After crystallizing the CuO _x -based material while forming the second layer made of the CuO _x -based material on the metal layer, ions of 3A group atoms and 2A group atoms are added to the second layer made of CuO _x -based material. Are ion-implanted into the second layer as a superconducting upper wiring layer to complete a multilayer wiring layer.

[Step-300] This step is the same as [Step-100] of Example 1, and detailed description thereof will be omitted. Through this step, a semiconductor element having a structure shown in the schematic partial cross-sectional view of FIG. 1A can be formed.

[Step-310] to [Step-320] These steps are also [Step-110] to [Step-12] of the first embodiment.
0], and detailed description thereof will be omitted. Through the above [Step-300] to [Step-320], the conductor layer made of the TiSi ₂ layer is formed on the lower wiring layer made of the source / drain regions formed on the semiconductor substrate ((in FIG. 1). See B) and (C)).

[Step-330] This step is also the same as [Step-130] of the first embodiment, and the detailed description thereof will be omitted.

[Step-340] Next, on the conductor layer made of the TiSi ₂ layer 22 in the opening 28, a first metal layer 30A functioning as an adhesion layer for the superconducting substance, for example, Au having a thickness of 50 nm is formed. A first metal layer 30A made of Ag, Cu or Cu is grown by a selective CVD method (see FIG. 2B). This step is the same as that of [Step-14 in Example 1].
0], and detailed description thereof will be omitted.

[Step-350] to [Step-360] Next, a first layer 32A made of a CuO _x material is formed on the first metal layer 30A formed in the opening 28 by 250 n.
Crystallization is performed while depositing to a thickness of m by the selective CVD method.
Then, ion implantation is performed to CuO _X-based materials, a high temperature superconducting the first layer 32A consisting of CuO _X-based material. Thus, the high temperature superconducting plug is completed (see FIG. 5A). These steps are also described in [Step-150] of Example 1-
This is the same as [Step-160] and its detailed description is omitted.

[Step-370] Next, the second metal layer 3 as an adhesion layer for the upper wiring layer made of a superconducting material.
8 is grown on the entire surface by the CVD method, for example, under the following conditions. The second metal layer 38 can be formed of Au. Gas source Dimethyl (1,1,1-trifluoro-2,4-pentandio
nato) gold (3) = 100 sccm Temperature 250 ° C. Here, although Au is taken as an example, Ag or Cu may be grown by the CVD method. In this case, A as the gas source
An organic gas source such as g (C ₅ H ₇ O ₂ ) or Cu (C ₅ H ₇ O ₂ ) ₂ can be used. In addition, the second metal layer 3
8 does not need to be formed in the opening, so these second
Instead of depositing the metal layer 38 of
It can also be deposited using a sputtering method.

[Step-380] Next, in order to form an upper wiring layer, a second layer 40 made of a CuO _x material is formed on the second metal layer 38 (adhesion layer) by, for example, a CVD method. Formed (see FIG. 5B). The conditions for forming the second layer 40 made of the CuO _x material are, for example, gas source Bis-hexa-fluoro-acethylacetonato cuppe.
r Cu (HFA) ₂ ) / O ₂ = 100/50 sccm Temperature 250 ° C. Thickness 250 nm can be used. By setting the temperature conditions as described above, the second layer 40 made of the CuO _x- based material is changed into the second layer 40
Is crystallized while being deposited on the metal layer 38. Incidentally, CV
Instead of the D method, the second layer 40 made of a CuO _x material can be formed by, for example, a high temperature sputtering method under the following conditions. Sputtering gas Ar / O ₂ = 45/3 sccm DC power 5 kW Pressure 0.47 Pa Film thickness 250 nm Film formation temperature 600 ° C. Then, Ba and Y are ion-implanted on the entire surface. The Ba and Y ion implantation conditions may be: implantation energy 100 keV implantation amount 1 × 10 ²⁰ / cm ² or more. In this way, the second layer 40 becomes high temperature superconductivity.

[Step-390] Next, after patterning the resist, the second layer 40 made of CuO _x material into which Ba and Y are ion-implanted by dry etching, and A
The second metal layer 38 of u is etched. The etching can be performed, for example, under the following conditions. Gas CCl ₂ F ₂ / Cl ₂ = 60 / 50s
ccm Microwave power 1000W RF power 50W Pressure 2Pa A superconducting plug and a superconducting upper wiring layer are formed by the above process, and a multilayer wiring layer is completed.

(Embodiment 4) In Embodiment 4, in the step of forming a conductor layer, a silicon oxide film is formed on a lower wiring layer, and then a metal film made of titanium is formed, and then heat treatment is performed to form titanium silicide. A multilayer wiring layer is completed by the same steps as in Example 3 except that a metal silicide layer composed of layers is formed.

[Step-400] Step-400 is the same as Step-100 of Example 1, and the description thereof is omitted.

[Step-410] Next, a silicon oxide film 20A having a thickness of 3 nm is formed on the entire surface by thermal oxidation. The conditions for forming the silicon oxide film 20A can be set as follows. Gas used O ₂ 6 liter / min Temperature 850 ° C. Then, in the same manner and conditions as in [Step-110] of Example 1, Ti having a thickness of 30 nm was formed on the silicon oxide film 20A.
A metal film composed of the layer 20 is formed (see FIG. 4). After that, a first annealing process is performed in an inert gas at 650 ° C. for 30 minutes by RTA (Rapid Thermal Annealing) method to silicify the Ti layer to form TiSi _x . Next, unreacted Ti is selectively removed by immersing in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide for 10 minutes. Then, a second annealing treatment is performed at 900 ° C. for 30 minutes in an inert gas (for example, N ₂ ) atmosphere to convert TiSi _x to stable TiSi ₂ having low resistance. As a result, a uniform conductor layer made of the TiSi ₂ layer 22 is selectively formed on the source / drain region formation planned region and the gate electrode region 14.

After [Step-420], the multilayer wiring layer is completed by the same steps as [Step-320] to [Step-390] of the third embodiment.

The present invention has been described above based on the preferred embodiments, but the present invention is not limited to these embodiments. The conditions in each step can be appropriately changed depending on the device used and the like.

The conductor layer has a low resistance and a superconducting material or C instead of the metal silicide layer made of TiSi _2.
Any metal silicide layer can be used as long as it has a function as a barrier against a metal layer made of u, Au, or Ag. For example, CoSi ₂ , WSi ₂ , MoSi.
₂ can be illustrated. Further, it may be composed of a refractory metal such as W or Mo or a so-called barrier metal such as TiN, TiB or TiW.

As the lower wiring layer, the source / drain regions have been described as an example, but the lower wiring layer may be a gate electrode region or a lower wiring layer made of a metal wiring material or a superconducting material. For the upper wiring layer in the method for forming a superconducting plug of the present invention, various wiring materials conventionally used can be used in addition to the aluminum-based wiring material.

[0051]

Since the plug formed in the connection hole is made of a superconducting material, the resistance or wiring resistance in the connection hole is almost eliminated, and the performance of the semiconductor device is improved.

In the method of forming a superconducting plug and the method of forming a multilayer wiring layer of the present invention, the (first) metal layer and Cu
Consisting O _X based material since the (first) layer is formed by selective CVD, a metal layer and CuO _X-based material in the minute opening portion (first) layer of good coverage and stably film thickness Can be deposited at. Further, since the crystallized according CuO _X-based material while forming consists CuO _X based material (first) layer by selective CVD method, to shorten the time required for forming the superconducting plugs than conventional methods You can

Further, since the (first) layer made of the CuO _x system material is formed before the ion implantation, a more stable layer can be formed. Moreover, the implantation amount of each ion can be accurately controlled, and appropriate conditions for forming the superconducting substance can be easily and accurately set. Therefore, it is easy to mass-produce the superconducting plug or the multilayer wiring layer.

Moreover, since the surface of the semiconductor substrate is covered with the conductor layer, it is possible to prevent diffusion of Cu or the like constituting the superconducting material into the semiconductor substrate. Further, since a metal layer made of gold, silver, or copper, which is a substance that facilitates crystal growth of CuO _x type material, is used as an underlayer, C
It is possible to easily and stably grow a crystal of the uO _x based material.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a method for forming a superconducting plug of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of the method for forming a superconducting plug of the present invention, following FIG.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor element manufactured by the method for forming a superconducting plug of the present invention.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor device for explaining a part of the steps of the preferred embodiment of the method for forming a superconducting plug of the present invention.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor element for explaining some steps of the method for forming a multilayer wiring layer of the present invention.

FIG. 6 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a conventional selective CVD method.

[Explanation of symbols]

10 semiconductor substrate 12 element isolation region 14 gate electrode region 16 shallow impurity diffusion region 18 sidewall 20 Ti layer 20A silicon oxide film 22 TiSi ₂ layer 24 source / drain region 26 interlayer insulating layer 28 opening 30 metal layer 30A first metal Layer 32 High Temperature Superconducting Layer 32A First High Temperature Superconducting Layer 34 Barrier Metal Layer 36 Upper Wiring Layer 38 Second Metal Layer 40 Superconducting Upper Wiring Layer

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 39/06 ZAA 8728-4M 39/24 ZAA F 8728-4M

Claims (4)

[Claims] 1. A method of forming a superconducting plug for electrically connecting a lower wiring layer and an upper wiring layer formed on a semiconductor substrate, comprising: (a) a lower wiring layer on a semiconductor substrate; A step of forming a conductor layer made of a metal or a metal compound thereon, and (b) a step of forming a metal layer selected from the group consisting of gold, silver or copper on the conductor layer by a selective CVD method. (C) Select a layer made of CuO _x based material on the metal layer C
A step of crystallizing the CuO _X-based material while forming at VD method, a layer made of (d) the CuO _X-based materials, the Group 3A atom ions and Group 2A atom ions are implanted, respectively,
And a step of forming a high temperature superconducting plug. 2. The step of forming the conductor layer comprises the steps of forming a silicon oxide film on the lower wiring layer, forming a metal film, and then performing heat treatment to form a metal silicide layer. The method of forming a superconducting plug according to claim 1. 3. A method for forming a multi-layer wiring layer comprising a lower wiring layer, an upper wiring layer formed on a semiconductor substrate, and a superconducting plug for electrically connecting these wiring layers, comprising: A) a step of forming a lower wiring layer and a conductor layer made of a metal or a metal compound on the lower wiring layer on a semiconductor substrate; and (b) a first layer selected from the group consisting of gold, silver or copper on the conductor layer. A step of forming a first metal layer by a selective CVD method, and (c) a first layer made of a CuO _x material on the first metal layer.
Layer is formed by the selective CVD method while the CuO _x based material is crystallized, ions of a group 3A atom and 2 are added to the first layer.
Forming a superconducting plug by ion-implanting ions of group A atoms; and (d) forming a second metal layer selected from the group consisting of gold, silver or copper on the superconducting plug. Then, the CuO _x -based material is crystallized while forming a second layer made of the CuO _x -based material on the second metal layer, and then 3A is formed on the second layer.
Forming a superconducting upper wiring layer by ion-implanting ions of group atoms and ions of group 2A atoms, respectively. 4. The step of forming the conductor layer comprises the step of forming a silicon oxide film on the lower wiring layer, then forming a metal film, and then performing heat treatment to form a metal silicide layer. The method for forming a multilayer wiring layer according to claim 3.