JP3188042B2 - Table search device in digital computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention has a data memory,
The present invention relates to a digital computer that performs processing based on the contents of the data memory, and more particularly to a table search device that searches the contents of the data memory for the maximum and minimum values of data and the addresses where the values are stored.

[0002]

2. Description of the Related Art Due to advances in semiconductor technology and microprocessor architecture, RISC processors and digital signal processors employing a Harvard architecture which divides the memory space of a processor into a program memory space and a data memory space to increase the speed of instruction execution. (DSP) and the like are in practical use.

[0003] The signal processing performed by such a DSP can be performed with higher precision than the processing by analog parts, and arbitrary characteristics such as filter characteristics can be stably and uniformly obtained by setting parameters. Furthermore, the use of the DSP has such a feature that fine adjustment due to the accuracy of components is not required as compared with the configuration using analog components, and has been rapidly spreading in various fields in recent years. As an application field of this DSP, it is used in a wide range of digital signal processing such as audio signal processing, communication signal processing, measurement signal processing, image signal processing, and sound processing.

For example, when performing audio signal processing in a DSP, a maximum value is obtained from a predetermined number of data, and the data is generally normalized based on the maximum value. In the case of searching for the maximum value, while reading the data into the data register, each data is compared and determined, and an instruction to store the larger value of the compared data in the accumulator is repeated, The desired maximum was obtained.

[0005] This comparison is realized by providing a comparator for judging the magnitude relationship between newly read data in the DSP and data stored in the DSP.

FIG. 4 is a schematic block diagram of an embodiment of a table search apparatus in a conventional digital computer.

In FIG. 4, 1 is a program counter storing the address of a program to be executed next, 2 is a program memory storing instruction codes of the program, and 3 is an instruction code stored in the program memory 2. An instruction register that reads and decodes data, 4 is a data memory that stores data used for the operation, 5 is an address allocation unit that specifies an address of the data memory 4, and 6 and 7 are bases of addresses generated by the address allocation unit 5. First and second address registers storing addresses to be used, 8 is a data register for storing data used for calculation, 9 is data for storing data in the data register 8 in accordance with a comparison determination result of a comparator 10 described later. Accumulator, 1
0 is a comparator for comparing the contents of the data register 8 with the contents of the accumulator 9 to determine the magnitude relation between the contents, 11 is a loop counter for storing the number of loops of the program, and 12 is a loop end address. Is a loop address register storing the program counter 1
Is an address comparator for determining whether or not the address of the loop address register 12 matches the address of the loop address register 12, and a system clock 14 serving as a clock pulse of the digital computer.

Next, FIG. 5 shows an example of a program including a comparison judgment instruction.
This is a program for checking the maximum value of data stored at address 03 (see FIG. 7) and the address where the maximum value is stored.

In FIG. 5, n-8, n-7,..., N +
2, n + 3 indicates the address of the program memory 2, and the frame indicates the program. A0 indicates the first address register 6, A1 indicates the second address register 7, R0 indicates the data register 8, and Acc indicates the accumulator 9. ing.

Also, load A0,100 is a machine language meaning that it is an instruction for storing a constant <100> in the first address register 6, and load A1,200 is a constant <200> in the second address register 7. Load Acc, 0, which means that the instruction is an instruction for storing
Is a machine language meaning that it is an instruction to store 0 in the accumulator 9, and move R0, (A0) transfers the contents of the data memory 4 indicated by the address stored in the first address register 6 to the data register. A machine language that means an instruction, do 4 n + 2, is a machine language that means that the next instruction of the do instruction, that is, an instruction that repeats the program from the program at address n to the program at address n + 4 four times, cmpgs R0 Is the accumulator 9
And the value of the data register 8 are compared. If the value of the data stored in the accumulator 9 is large, the next instruction is skipped. If the value of the data stored in the accumulator 9 is small, A machine language that means an instruction to store a value in the accumulator 9, m
ove (A1), A0 is a machine language that means that an instruction to store the contents of the first address register 6 at the address indicated in the second address register 7 is inr A
0; move R0, (A0) is an instruction for incrementing the content of the first address register 6 by 1 and transferring the content indicated by the address stored in the first address register 6 to the data register 8. It is a machine language meaning.

FIG. 6 shows a flowchart of the program shown in FIG. 5. In S1, the data <100> stored at the address n-7 of the program memory 2 is read into the first address register 6; Further S2
, The data <200> stored at the address n-5 of the program memory 2 is read into the second address register 7. In S3, data <0> is set in the accumulator 9. In S4, the contents of the data memory 4 indicated by the address stored in the first address register 6 are stored in the data register 8. In S5, the loop counter 11 reads the loop count <4> and the loop address register reads the loop end address <n + 2>.

In S6, the contents of the data register 8 and the contents of the accumulator 9 are compared. In S7, the data having the larger value is stored in the accumulator 9 in accordance with the comparison result in S6, and the address of the first address register 6 is transferred to the data memory 4 in accordance with the address generated by the second address register 7. I do. In S8, the number of loops of the loop counter 11 is decremented by one, and the address value of the first address register 6 is incremented by one. In S9, it is determined whether or not the number of loops of the loop counter 11 has become 0, and if the number of loops of the loop counter 11 is not 0,
Returning to S6, S6 to S9 are repeated, and if the number of loops of the loop counter 11 is 0, the process proceeds to the next process.

The flow of the program shown in FIG. 5 will be described with reference to FIGS. 4 and 6. N-8 of program memory 2
When the instructions stored at addresses, addresses n-6 and n-4 are executed, the first address register 6 stores <100
>, The second address register 7 stores <200>, and the accumulator 9 stores <0>. It is assumed that data is already stored at addresses 100 to 103 in the data memory 4 as shown in FIG. 7 (see S1 to S3).

The instruction move R0, (A
When (0) is executed, the address allocation unit 5 outputs the address of the data memory 4, the address of the data memory 4 is determined, and the contents of the address are stored in the data register 8 via the data bus. Therefore, the data <30> stored at the address 100 of the data memory 4 is read into the data register 8 (see S4).

Subsequently, an instruction do 4 n + 2 at address n−1
Is executed, the loop counter 11 stores the number of loops <4.
> Stores the loop end address <n + 2> in the loop address register 12 (see S5).

When the instruction cmpgs R0 at address n + 1 is executed, the content <30> of the data register 8 is compared with the content <0> of the accumulator 9 (see S6). Since the content <30> of the data register 8 is large, The contents <30> of the data register 8 are transferred to the accumulator 9, and thereafter, the instructions move (A1) and A0 at address n + 2 are executed. The first address register 6 is <200>,
Therefore, <100> which is the value of the first address register 6 is stored at address 200 of the data memory 4 (see S7).

Next, the instruction at address n + 3 inr A0; mo
ve R0, (A0) is executed, the value of the first address register 6 becomes <101>, and 10 is stored in the data register 8. When this instruction is executed, the address comparator 13 detects that the address stored in the loop address register 12 matches the value of the program counter 1 (see S8), and the instruction do 4 n + 2
Again from the next instruction cmpgsR0,
Decrement the loop count of the loop counter 11 by 1,
<3> (see S9).

When the instruction cmpgs R0 at address n + 1 is executed, the contents <10> of the data register 8 and the contents <0> of the accumulator 9 are compared. Since the contents <30> of the accumulator 9 are large, the instruction inr at address n + 3 is obtained. A
0; move R0, (A0) is executed.

Thereafter, the same process is repeated until the number of loops of the loop counter 11 becomes zero.

By the above operation, the accumulator 9 stores <100>, which is the maximum value of the contents of addresses 100 to 103 of the data memory 4, and
At address 200, the address value <102> of the data memory 4 in which the maximum value is stored is stored.

[0021]

As described above, in a digital computer, a comparison / judgment instruction is used to search for a maximum value or a minimum value from data stored in a data memory. For example, when searching for the maximum value, a comparison determination is made while reading data into the data register, and a command for storing the maximum value in the accumulator is repeated to obtain a desired maximum value. However, when such an operation is performed, the address of the data memory in which the maximum value is stored together with the maximum value is often used as information in subsequent operations. In such a case, as disclosed in the conventional example, when a new maximum value is obtained after performing a magnitude determination, an instruction to store the address in another area is executed, thereby obtaining the maximum value. The address giving the value was stored. Therefore, every time the maximum value changes, it is necessary to execute an instruction to store the address giving the maximum value in another area, which has hindered an increase in the operation time. In particular, in a DSP premised on pipeline processing, since the address of data stored in the comparator and the address stored in the address register are different, it is necessary to calculate the address again and store the address. , Processing overhead has arisen.

Therefore, the present invention has been made in view of the above-mentioned problem, and accumulates, by hardware, an address of a memory in which a maximum value or a minimum value detected by a comparator is stored. It is an object of the present invention to provide a table search device capable of performing a search.

[0023]

In order to solve the above-mentioned problems, a table retrieval apparatus of the present invention comprises a data memory storing data, an address allocation unit for generating an address of the data memory, an address allocation. An address register storing an address that is a basis of an address generated by the unit, a data register storing data of a data memory, an accumulator storing a desired maximum value or a minimum value, A comparator is provided for comparing the magnitude relationship between the data stored in the data register and the data stored in the accumulator, a table register for storing the output of the address allocation unit, and a signal generated according to the operation result of the comparator. And a table register write signal. When the result of the comparison indicates that the value of the data register is stored in the accumulator, a table register write signal is generated, and the data stored in the accumulator is stored in the table register according to the signal. Has the function of writing the address of

[0024]

According to the above means, the address of the data memory, which is the output of the address allocation unit, is sequentially stored in the table register in synchronization with the system clock, and is stored in the data register when the comparison instruction is executed. When the data stored in the data register is newly written to the accumulator by comparing and comparing the stored data with the data stored in the accumulator, the value of the table register is stored in the data stored in the accumulator. It is saved by newly rewriting the address of the data memory.

[0025]

FIG. 1 is a schematic block diagram showing an embodiment of a digital computer provided with a table search apparatus according to the present invention.

In FIG. 1, components having the same functions as those of the conventional example shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

The present invention is different from the conventional example in that it has a table register 15 and a table register write signal 16, and the table register 15 is composed of a plurality of buffers. For example, when the execution of the operation is performed by three-stage pipeline processing, the table register 15 has a three-stage buffer configuration. The table register write signal 16 is used to store the address of the data memory 4 where the data of the data register 8 is stored when the value of the data register 8 is a desired value as a result of the comparison judgment in the comparator 10. Signal. The first buffer 15a and the second buffer 15b of the table register 15 are updated in synchronization with the system clock 14, and the third buffer 15c responds to the table register write signal 16 based on the operation result of the comparator 10. It can be rewritten.

FIG. 2 shows an example of a program of a digital computer provided with the table search device of the present invention. n
-4, n-3,..., N + 2 indicate addresses, and the frame indicates a program. The description of the same program as that of the conventional example shown in FIG. 5 is omitted. This embodiment differs from the conventional example in that the instruction R0 stored at address n + 2
= (A0 +); cmpg R0; and this instruction is:
The content stored at the address indicated by the first address register 6 is transferred to the data register 8, the content of the first address register 6 is incremented by 1, and
The value read into the data register 8 and the accumulator 9
Are compared, and if the value of the data register 8 is large, the data register 8 is stored in the accumulator 9.
Is a machine language that means an instruction for storing the value of the table register and generating the table register write signal 16.

FIG. 3 shows a timing chart when the program shown in FIG. 2 is executed. In FIG. 3, CL
K is a waveform of the system clock 14 which is a clock pulse wave of the digital computer, and PCQ is a program counter 1
, IRQ is the waveform of the instruction register 3, AALU1 is the waveform of the address allocation unit 5, XR0 is the waveform of the data register 8, ACCR is the waveform of the accumulator 9, TBLR1, TBLR2, and TB.
LR3 is the waveform of the first, second, and third buffers of the table register 15, and TBLWR is the waveform of the table register write signal 16.

The operation when the program shown in FIG. 2 is implemented by the circuit configuration of FIG. 1 will be described with reference to the timing chart of FIG. The instructions at addresses n-4, n-2, and n are the same as those in the conventional example, and will not be described.

The case where the comparison instruction at address n + 2 is executed will be described below. The execution of the instruction is a pipeline process. For example, the instruction R0 at address n + 2 = (A0 +); cmpg R in synchronization with the rising B of CLK.
0; is read into the instruction register 3, and the instruction is decoded. Subsequently, the address is output from the address allocation unit 5 in synchronization with the rising C of the CLK. The content of the data memory 4 is stored in the data register 8 in synchronization with the rising edge D of CLK,
The content of the accumulator 9 is compared with the content of the data register 8 in the comparator 10 in synchronization with the rise E of the data.

On the other hand, the output <100> of the address allocation unit 5 is stored in the first buffer 15a of the table register 15 in synchronization with the rising C of CLK. Similarly, in synchronism with the rising edge D of the CLK, the value of the first buffer 15a of the table register 15 is stored in the second buffer 15b of the table register 15 <1.
00> is transferred, and the output <101> of the address allocation unit 5 is stored in the first buffer 15a of the table register 15.

The comparator 1 is synchronized with the rising edge E of CLK.
At 0, the value <0> of the accumulator 9 is compared with the value <30> of the data register 8. At this time, since the value of the data register 8 is large, the table register write signal 16 is generated, and the third buffer 15 c of the table register 15 receives the table register write signal 16 and receives the table register write signal 16. Is written to the third buffer 15c. On the other hand, the comparator 10 stores the content <30> of the data register 8 in the accumulator 9.

The instruction do 4, n + 2 at address n is n + 2
This means that the instruction is repeated four times up to the address, and the second to fourth times are similarly executed.

In the second time, the value <30> of the accumulator 9 is compared with the value <10> of the data register 8 in the comparator 10 in synchronization with the rising F of the CLK. Since the value of the accumulator 10 is large, the table register write signal 16 is not generated. Since the third buffer 15c of the table register 15 does not receive the table register write signal 16, the data is held as it is.

The above operation is performed by comparing the value of the data register 8 with
The comparison of the value of the accumulator 9 with the comparator 10 is repeated. When the repetition is completed, the maximum value <100> of the data stored at addresses 100 to 103 of the data memory 8 is stored in the accumulator 9, and is stored in the third buffer 15 c of the table register 15. Is the address <102> of the data memory 8 where the maximum value <100> is stored.

Although the table register of the present invention uses a buffer having a three-stage configuration, the number of stages depends on the number of stages of pipeline processing, and does not limit the content of the present invention.

In this embodiment, the case where the maximum value of the data is obtained has been described as an example of the criterion for comparison. However, the present invention is also applicable to the case where the minimum value, the minimum value and the maximum value of the absolute value are obtained. it can. Further, even when the comparison and determination results are equal, the table register can be rewritten.

As described above, it is necessary to execute the instruction for storing the address by providing the table register for storing the address where the data used for the comparison and determination is stored according to the result of the comparison and determination instruction. Therefore, it is possible to speed up the execution of the program.

[0040]

As is apparent from the above description, the present invention provides a table register and a table register write signal, and the comparator compares the contents of the data register and the accumulator at the time of execution of the comparison judgment instruction. If the value is the desired value, the desired value is newly stored in the accumulator and a table register write signal is sent to the table register. As a result, the table register receives the table register write signal and stores the address of the data memory where the data of the data register is stored. As a result, the instruction of storing the address of the data memory giving the desired value, which has been executed by the DSP program, can be reduced, and the address of the data memory giving the desired value is stored in the table register simultaneously with the execution of the comparison / determination instruction. be able to. As a result, the comparison operation can be performed efficiently and at high speed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of a digital computer equipped with a table search device of the present invention.

FIG. 2 shows an example of a program including a comparison / determination instruction in a digital computer provided with the table search device of the present invention.

FIG. 3 is a timing chart when a comparison / determination instruction is executed in a digital computer provided with the table search device of the present invention.

FIG. 4 is a schematic configuration diagram of a digital computer including a conventional table search device.

FIG. 5 shows an example of a program including a comparison / determination instruction in a digital computer having a conventional table search device.

FIG. 6 is a flowchart when a comparison / determination instruction is executed in a digital computer having a conventional table search device.

FIG. 7 shows the contents of a data memory targeted by a comparison / determination instruction.

[Explanation of symbols]

 4 Data Memory 5 Address Allocation Unit 6 First Address Register 8 Data Register 9 Accumulator 10 Comparator 15 Table Register 15a First Buffer 15b Second Buffer 15c Third Buffer 16 Table Register Write Signal

Continuation of the front page (72) Akira Yoshida 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-60-108973 (JP, A) JP-A-2-28828 (JP, A) JP-A-4-65713 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 7/02 G06F 7/00 G06F 9/38 310

Claims (2)

(57) [Claims] 1. A data memory storing data used for an operation, an address allocation unit for specifying an address of the data memory, and a data register for storing data of the data memory specified by the address allocation unit. A comparator for comparing and judging a data value, an accumulator for storing desired data based on the judgment result of the comparator, and a table for storing an address output from the address allocation unit in accordance with a table register write signal And a register, in the comparator, when a comparison determination command is executed, when desired data is obtained, the data is stored in the accumulator, the table register write signal is generated, and according to the signal, And the data is stored Table search unit in a digital computer address of said data memory are characterized by that stored in the table register. 2. The table register includes a plurality of serially connected buffers. The buffers store addresses sequentially output from the address allocation unit in accordance with a predetermined timing of pipeline processing, and store the next addresses. 2. A table search apparatus in a digital computer according to claim 1, wherein the data is transferred to the last buffer, and the writing of the address to the last buffer among the buffers is determined by the table register write signal.